fsl_upm.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale UPM NAND driver.
  4. *
  5. * Copyright © 2007-2008 MontaVista Software, Inc.
  6. *
  7. * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/delay.h>
  12. #include <linux/mtd/rawnand.h>
  13. #include <linux/mtd/partitions.h>
  14. #include <linux/mtd/mtd.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/io.h>
  18. #include <linux/slab.h>
  19. #include <asm/fsl_lbc.h>
  20. struct fsl_upm_nand {
  21. struct nand_controller base;
  22. struct device *dev;
  23. struct nand_chip chip;
  24. struct fsl_upm upm;
  25. uint8_t upm_addr_offset;
  26. uint8_t upm_cmd_offset;
  27. void __iomem *io_base;
  28. struct gpio_desc *rnb_gpio[NAND_MAX_CHIPS];
  29. uint32_t mchip_offsets[NAND_MAX_CHIPS];
  30. uint32_t mchip_count;
  31. uint32_t mchip_number;
  32. };
  33. static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
  34. {
  35. return container_of(mtd_to_nand(mtdinfo), struct fsl_upm_nand,
  36. chip);
  37. }
  38. static int fun_chip_init(struct fsl_upm_nand *fun,
  39. const struct device_node *upm_np,
  40. const struct resource *io_res)
  41. {
  42. struct mtd_info *mtd = nand_to_mtd(&fun->chip);
  43. int ret;
  44. struct device_node *flash_np;
  45. fun->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
  46. fun->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
  47. fun->chip.controller = &fun->base;
  48. mtd->dev.parent = fun->dev;
  49. flash_np = of_get_next_child(upm_np, NULL);
  50. if (!flash_np)
  51. return -ENODEV;
  52. nand_set_flash_node(&fun->chip, flash_np);
  53. mtd->name = devm_kasprintf(fun->dev, GFP_KERNEL, "0x%llx.%pOFn",
  54. (u64)io_res->start,
  55. flash_np);
  56. if (!mtd->name) {
  57. ret = -ENOMEM;
  58. goto err;
  59. }
  60. ret = nand_scan(&fun->chip, fun->mchip_count);
  61. if (ret)
  62. goto err;
  63. ret = mtd_device_register(mtd, NULL, 0);
  64. err:
  65. of_node_put(flash_np);
  66. return ret;
  67. }
  68. static int func_exec_instr(struct nand_chip *chip,
  69. const struct nand_op_instr *instr)
  70. {
  71. struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
  72. u32 mar, reg_offs = fun->mchip_offsets[fun->mchip_number];
  73. unsigned int i;
  74. const u8 *out;
  75. u8 *in;
  76. switch (instr->type) {
  77. case NAND_OP_CMD_INSTR:
  78. fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
  79. mar = (instr->ctx.cmd.opcode << (32 - fun->upm.width)) |
  80. reg_offs;
  81. fsl_upm_run_pattern(&fun->upm, fun->io_base + reg_offs, mar);
  82. fsl_upm_end_pattern(&fun->upm);
  83. return 0;
  84. case NAND_OP_ADDR_INSTR:
  85. fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
  86. for (i = 0; i < instr->ctx.addr.naddrs; i++) {
  87. mar = (instr->ctx.addr.addrs[i] << (32 - fun->upm.width)) |
  88. reg_offs;
  89. fsl_upm_run_pattern(&fun->upm, fun->io_base + reg_offs, mar);
  90. }
  91. fsl_upm_end_pattern(&fun->upm);
  92. return 0;
  93. case NAND_OP_DATA_IN_INSTR:
  94. in = instr->ctx.data.buf.in;
  95. for (i = 0; i < instr->ctx.data.len; i++)
  96. in[i] = in_8(fun->io_base + reg_offs);
  97. return 0;
  98. case NAND_OP_DATA_OUT_INSTR:
  99. out = instr->ctx.data.buf.out;
  100. for (i = 0; i < instr->ctx.data.len; i++)
  101. out_8(fun->io_base + reg_offs, out[i]);
  102. return 0;
  103. case NAND_OP_WAITRDY_INSTR:
  104. if (!fun->rnb_gpio[fun->mchip_number])
  105. return nand_soft_waitrdy(chip, instr->ctx.waitrdy.timeout_ms);
  106. return nand_gpio_waitrdy(chip, fun->rnb_gpio[fun->mchip_number],
  107. instr->ctx.waitrdy.timeout_ms);
  108. default:
  109. return -EINVAL;
  110. }
  111. return 0;
  112. }
  113. static int fun_exec_op(struct nand_chip *chip, const struct nand_operation *op,
  114. bool check_only)
  115. {
  116. struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
  117. unsigned int i;
  118. int ret;
  119. if (op->cs >= NAND_MAX_CHIPS)
  120. return -EINVAL;
  121. if (check_only)
  122. return 0;
  123. fun->mchip_number = op->cs;
  124. for (i = 0; i < op->ninstrs; i++) {
  125. ret = func_exec_instr(chip, &op->instrs[i]);
  126. if (ret)
  127. return ret;
  128. if (op->instrs[i].delay_ns)
  129. ndelay(op->instrs[i].delay_ns);
  130. }
  131. return 0;
  132. }
  133. static const struct nand_controller_ops fun_ops = {
  134. .exec_op = fun_exec_op,
  135. };
  136. static int fun_probe(struct platform_device *ofdev)
  137. {
  138. struct fsl_upm_nand *fun;
  139. struct resource *io_res;
  140. const __be32 *prop;
  141. int ret;
  142. int size;
  143. int i;
  144. fun = devm_kzalloc(&ofdev->dev, sizeof(*fun), GFP_KERNEL);
  145. if (!fun)
  146. return -ENOMEM;
  147. fun->io_base = devm_platform_get_and_ioremap_resource(ofdev, 0, &io_res);
  148. if (IS_ERR(fun->io_base))
  149. return PTR_ERR(fun->io_base);
  150. ret = fsl_upm_find(io_res->start, &fun->upm);
  151. if (ret) {
  152. dev_err(&ofdev->dev, "can't find UPM\n");
  153. return ret;
  154. }
  155. prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
  156. &size);
  157. if (!prop || size != sizeof(uint32_t)) {
  158. dev_err(&ofdev->dev, "can't get UPM address offset\n");
  159. return -EINVAL;
  160. }
  161. fun->upm_addr_offset = *prop;
  162. prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
  163. if (!prop || size != sizeof(uint32_t)) {
  164. dev_err(&ofdev->dev, "can't get UPM command offset\n");
  165. return -EINVAL;
  166. }
  167. fun->upm_cmd_offset = *prop;
  168. prop = of_get_property(ofdev->dev.of_node,
  169. "fsl,upm-addr-line-cs-offsets", &size);
  170. if (prop && (size / sizeof(uint32_t)) > 0) {
  171. fun->mchip_count = size / sizeof(uint32_t);
  172. if (fun->mchip_count >= NAND_MAX_CHIPS) {
  173. dev_err(&ofdev->dev, "too much multiple chips\n");
  174. return -EINVAL;
  175. }
  176. for (i = 0; i < fun->mchip_count; i++)
  177. fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
  178. } else {
  179. fun->mchip_count = 1;
  180. }
  181. for (i = 0; i < fun->mchip_count; i++) {
  182. fun->rnb_gpio[i] = devm_gpiod_get_index_optional(&ofdev->dev,
  183. NULL, i,
  184. GPIOD_IN);
  185. if (IS_ERR(fun->rnb_gpio[i])) {
  186. dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
  187. return PTR_ERR(fun->rnb_gpio[i]);
  188. }
  189. }
  190. nand_controller_init(&fun->base);
  191. fun->base.ops = &fun_ops;
  192. fun->dev = &ofdev->dev;
  193. ret = fun_chip_init(fun, ofdev->dev.of_node, io_res);
  194. if (ret)
  195. return ret;
  196. dev_set_drvdata(&ofdev->dev, fun);
  197. return 0;
  198. }
  199. static void fun_remove(struct platform_device *ofdev)
  200. {
  201. struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
  202. struct nand_chip *chip = &fun->chip;
  203. struct mtd_info *mtd = nand_to_mtd(chip);
  204. int ret;
  205. ret = mtd_device_unregister(mtd);
  206. WARN_ON(ret);
  207. nand_cleanup(chip);
  208. }
  209. static const struct of_device_id of_fun_match[] = {
  210. { .compatible = "fsl,upm-nand" },
  211. {},
  212. };
  213. MODULE_DEVICE_TABLE(of, of_fun_match);
  214. static struct platform_driver of_fun_driver = {
  215. .driver = {
  216. .name = "fsl,upm-nand",
  217. .of_match_table = of_fun_match,
  218. },
  219. .probe = fun_probe,
  220. .remove_new = fun_remove,
  221. };
  222. module_platform_driver(of_fun_driver);
  223. MODULE_LICENSE("GPL");
  224. MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
  225. MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
  226. "LocalBus User-Programmable Machine");