qcom-spmi-sdam.c 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017, 2020-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/device.h>
  6. #include <linux/module.h>
  7. #include <linux/of.h>
  8. #include <linux/nvmem-provider.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/regmap.h>
  11. #define SDAM_MEM_START 0x40
  12. #define REGISTER_MAP_ID 0x40
  13. #define REGISTER_MAP_VERSION 0x41
  14. #define SDAM_SIZE 0x44
  15. #define SDAM_PBS_TRIG_SET 0xE5
  16. #define SDAM_PBS_TRIG_CLR 0xE6
  17. struct sdam_chip {
  18. struct regmap *regmap;
  19. struct nvmem_config sdam_config;
  20. unsigned int base;
  21. unsigned int size;
  22. };
  23. /* read only register offsets */
  24. static const u8 sdam_ro_map[] = {
  25. REGISTER_MAP_ID,
  26. REGISTER_MAP_VERSION,
  27. SDAM_SIZE
  28. };
  29. static bool sdam_is_valid(struct sdam_chip *sdam, unsigned int offset,
  30. size_t len)
  31. {
  32. unsigned int sdam_mem_end = SDAM_MEM_START + sdam->size - 1;
  33. if (!len)
  34. return false;
  35. if (offset >= SDAM_MEM_START && offset <= sdam_mem_end
  36. && (offset + len - 1) <= sdam_mem_end)
  37. return true;
  38. else if ((offset == SDAM_PBS_TRIG_SET || offset == SDAM_PBS_TRIG_CLR)
  39. && (len == 1))
  40. return true;
  41. return false;
  42. }
  43. static bool sdam_is_ro(unsigned int offset, size_t len)
  44. {
  45. int i;
  46. for (i = 0; i < ARRAY_SIZE(sdam_ro_map); i++)
  47. if (offset <= sdam_ro_map[i] && (offset + len) > sdam_ro_map[i])
  48. return true;
  49. return false;
  50. }
  51. static int sdam_read(void *priv, unsigned int offset, void *val,
  52. size_t bytes)
  53. {
  54. struct sdam_chip *sdam = priv;
  55. struct device *dev = sdam->sdam_config.dev;
  56. int rc;
  57. if (!sdam_is_valid(sdam, offset, bytes)) {
  58. dev_err(dev, "Invalid SDAM offset %#x len=%zd\n",
  59. offset, bytes);
  60. return -EINVAL;
  61. }
  62. rc = regmap_bulk_read(sdam->regmap, sdam->base + offset, val, bytes);
  63. if (rc < 0)
  64. dev_err(dev, "Failed to read SDAM offset %#x len=%zd, rc=%d\n",
  65. offset, bytes, rc);
  66. return rc;
  67. }
  68. static int sdam_write(void *priv, unsigned int offset, void *val,
  69. size_t bytes)
  70. {
  71. struct sdam_chip *sdam = priv;
  72. struct device *dev = sdam->sdam_config.dev;
  73. int rc;
  74. if (!sdam_is_valid(sdam, offset, bytes)) {
  75. dev_err(dev, "Invalid SDAM offset %#x len=%zd\n",
  76. offset, bytes);
  77. return -EINVAL;
  78. }
  79. if (sdam_is_ro(offset, bytes)) {
  80. dev_err(dev, "Invalid write offset %#x len=%zd\n",
  81. offset, bytes);
  82. return -EINVAL;
  83. }
  84. rc = regmap_bulk_write(sdam->regmap, sdam->base + offset, val, bytes);
  85. if (rc < 0)
  86. dev_err(dev, "Failed to write SDAM offset %#x len=%zd, rc=%d\n",
  87. offset, bytes, rc);
  88. return rc;
  89. }
  90. static int sdam_probe(struct platform_device *pdev)
  91. {
  92. struct sdam_chip *sdam;
  93. struct nvmem_device *nvmem;
  94. unsigned int val;
  95. int rc;
  96. sdam = devm_kzalloc(&pdev->dev, sizeof(*sdam), GFP_KERNEL);
  97. if (!sdam)
  98. return -ENOMEM;
  99. sdam->regmap = dev_get_regmap(pdev->dev.parent, NULL);
  100. if (!sdam->regmap) {
  101. dev_err(&pdev->dev, "Failed to get regmap handle\n");
  102. return -ENXIO;
  103. }
  104. rc = of_property_read_u32(pdev->dev.of_node, "reg", &sdam->base);
  105. if (rc < 0) {
  106. dev_err(&pdev->dev, "Failed to get SDAM base, rc=%d\n", rc);
  107. return -EINVAL;
  108. }
  109. rc = regmap_read(sdam->regmap, sdam->base + SDAM_SIZE, &val);
  110. if (rc < 0) {
  111. dev_err(&pdev->dev, "Failed to read SDAM_SIZE rc=%d\n", rc);
  112. return -EINVAL;
  113. }
  114. sdam->size = val * 32;
  115. sdam->sdam_config.dev = &pdev->dev;
  116. sdam->sdam_config.name = "spmi_sdam";
  117. sdam->sdam_config.id = NVMEM_DEVID_AUTO;
  118. sdam->sdam_config.owner = THIS_MODULE;
  119. sdam->sdam_config.add_legacy_fixed_of_cells = true;
  120. sdam->sdam_config.stride = 1;
  121. sdam->sdam_config.size = sdam->size;
  122. sdam->sdam_config.word_size = 1;
  123. sdam->sdam_config.reg_read = sdam_read;
  124. sdam->sdam_config.reg_write = sdam_write;
  125. sdam->sdam_config.priv = sdam;
  126. nvmem = devm_nvmem_register(&pdev->dev, &sdam->sdam_config);
  127. if (IS_ERR(nvmem)) {
  128. dev_err(&pdev->dev,
  129. "Failed to register SDAM nvmem device rc=%ld\n",
  130. PTR_ERR(nvmem));
  131. return -ENXIO;
  132. }
  133. dev_dbg(&pdev->dev,
  134. "SDAM base=%#x size=%u registered successfully\n",
  135. sdam->base, sdam->size);
  136. return 0;
  137. }
  138. static const struct of_device_id sdam_match_table[] = {
  139. { .compatible = "qcom,spmi-sdam" },
  140. {},
  141. };
  142. MODULE_DEVICE_TABLE(of, sdam_match_table);
  143. static struct platform_driver sdam_driver = {
  144. .driver = {
  145. .name = "qcom,spmi-sdam",
  146. .of_match_table = sdam_match_table,
  147. },
  148. .probe = sdam_probe,
  149. };
  150. module_platform_driver(sdam_driver);
  151. MODULE_DESCRIPTION("QCOM SPMI SDAM driver");
  152. MODULE_LICENSE("GPL v2");