phy-qcom-qmp-pcs-pcie-v5_20.h 871 B

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2017, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
  6. #define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
  7. /* Only for QMP V5_20 PHY - PCIe PCS registers */
  8. #define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c
  9. #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
  10. #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
  11. #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
  12. #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
  13. #define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
  14. #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
  15. #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
  16. #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
  17. #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
  18. #define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0xa24
  19. #define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0xa28
  20. #endif