phy-rcar-gen3-usb2.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas R-Car Gen3 for USB2.0 PHY driver
  4. *
  5. * Copyright (C) 2015-2017 Renesas Electronics Corporation
  6. *
  7. * This is based on the phy-rcar-gen2 driver:
  8. * Copyright (C) 2014 Renesas Solutions Corp.
  9. * Copyright (C) 2014 Cogent Embedded, Inc.
  10. */
  11. #include <linux/extcon-provider.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/module.h>
  15. #include <linux/mutex.h>
  16. #include <linux/of.h>
  17. #include <linux/phy/phy.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/reset.h>
  22. #include <linux/string.h>
  23. #include <linux/usb/of.h>
  24. #include <linux/workqueue.h>
  25. /******* USB2.0 Host registers (original offset is +0x200) *******/
  26. #define USB2_INT_ENABLE 0x000
  27. #define USB2_AHB_BUS_CTR 0x008
  28. #define USB2_USBCTR 0x00c
  29. #define USB2_SPD_RSM_TIMSET 0x10c
  30. #define USB2_OC_TIMSET 0x110
  31. #define USB2_COMMCTRL 0x600
  32. #define USB2_OBINTSTA 0x604
  33. #define USB2_OBINTEN 0x608
  34. #define USB2_VBCTRL 0x60c
  35. #define USB2_LINECTRL1 0x610
  36. #define USB2_ADPCTRL 0x630
  37. /* INT_ENABLE */
  38. #define USB2_INT_ENABLE_UCOM_INTEN BIT(3)
  39. #define USB2_INT_ENABLE_USBH_INTB_EN BIT(2) /* For EHCI */
  40. #define USB2_INT_ENABLE_USBH_INTA_EN BIT(1) /* For OHCI */
  41. /* AHB_BUS_CTR */
  42. #define USB2_AHB_BUS_CTR_MBL_MASK GENMASK(1, 0)
  43. #define USB2_AHB_BUS_CTR_MBL_INCR4 2
  44. /* USBCTR */
  45. #define USB2_USBCTR_DIRPD BIT(2)
  46. #define USB2_USBCTR_PLL_RST BIT(1)
  47. /* SPD_RSM_TIMSET */
  48. #define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
  49. /* OC_TIMSET */
  50. #define USB2_OC_TIMSET_INIT 0x000209ab
  51. /* COMMCTRL */
  52. #define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */
  53. /* OBINTSTA and OBINTEN */
  54. #define USB2_OBINT_SESSVLDCHG BIT(12)
  55. #define USB2_OBINT_IDDIGCHG BIT(11)
  56. #define USB2_OBINT_BITS (USB2_OBINT_SESSVLDCHG | \
  57. USB2_OBINT_IDDIGCHG)
  58. /* VBCTRL */
  59. #define USB2_VBCTRL_OCCLREN BIT(16)
  60. #define USB2_VBCTRL_DRVVBUSSEL BIT(8)
  61. #define USB2_VBCTRL_VBOUT BIT(0)
  62. /* LINECTRL1 */
  63. #define USB2_LINECTRL1_DPRPD_EN BIT(19)
  64. #define USB2_LINECTRL1_DP_RPD BIT(18)
  65. #define USB2_LINECTRL1_DMRPD_EN BIT(17)
  66. #define USB2_LINECTRL1_DM_RPD BIT(16)
  67. #define USB2_LINECTRL1_OPMODE_NODRV BIT(6)
  68. /* ADPCTRL */
  69. #define USB2_ADPCTRL_OTGSESSVLD BIT(20)
  70. #define USB2_ADPCTRL_IDDIG BIT(19)
  71. #define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
  72. #define USB2_ADPCTRL_DRVVBUS BIT(4)
  73. /* RZ/G2L specific */
  74. #define USB2_OBINT_IDCHG_EN BIT(0)
  75. #define USB2_LINECTRL1_USB2_IDMON BIT(0)
  76. #define NUM_OF_PHYS 4
  77. enum rcar_gen3_phy_index {
  78. PHY_INDEX_BOTH_HC,
  79. PHY_INDEX_OHCI,
  80. PHY_INDEX_EHCI,
  81. PHY_INDEX_HSUSB
  82. };
  83. static const u32 rcar_gen3_int_enable[NUM_OF_PHYS] = {
  84. USB2_INT_ENABLE_USBH_INTB_EN | USB2_INT_ENABLE_USBH_INTA_EN,
  85. USB2_INT_ENABLE_USBH_INTA_EN,
  86. USB2_INT_ENABLE_USBH_INTB_EN,
  87. 0
  88. };
  89. struct rcar_gen3_phy {
  90. struct phy *phy;
  91. struct rcar_gen3_chan *ch;
  92. u32 int_enable_bits;
  93. bool initialized;
  94. bool otg_initialized;
  95. bool powered;
  96. };
  97. struct rcar_gen3_chan {
  98. void __iomem *base;
  99. struct device *dev; /* platform_device's device */
  100. struct extcon_dev *extcon;
  101. struct rcar_gen3_phy rphys[NUM_OF_PHYS];
  102. struct regulator *vbus;
  103. struct reset_control *rstc;
  104. struct work_struct work;
  105. struct mutex lock; /* protects rphys[...].powered */
  106. enum usb_dr_mode dr_mode;
  107. int irq;
  108. u32 obint_enable_bits;
  109. bool extcon_host;
  110. bool is_otg_channel;
  111. bool uses_otg_pins;
  112. bool soc_no_adp_ctrl;
  113. };
  114. struct rcar_gen3_phy_drv_data {
  115. const struct phy_ops *phy_usb2_ops;
  116. bool no_adp_ctrl;
  117. bool init_bus;
  118. };
  119. /*
  120. * Combination about is_otg_channel and uses_otg_pins:
  121. *
  122. * Parameters || Behaviors
  123. * is_otg_channel | uses_otg_pins || irqs | role sysfs
  124. * ---------------------+---------------++--------------+------------
  125. * true | true || enabled | enabled
  126. * true | false || disabled | enabled
  127. * false | any || disabled | disabled
  128. */
  129. static void rcar_gen3_phy_usb2_work(struct work_struct *work)
  130. {
  131. struct rcar_gen3_chan *ch = container_of(work, struct rcar_gen3_chan,
  132. work);
  133. if (ch->extcon_host) {
  134. extcon_set_state_sync(ch->extcon, EXTCON_USB_HOST, true);
  135. extcon_set_state_sync(ch->extcon, EXTCON_USB, false);
  136. } else {
  137. extcon_set_state_sync(ch->extcon, EXTCON_USB_HOST, false);
  138. extcon_set_state_sync(ch->extcon, EXTCON_USB, true);
  139. }
  140. }
  141. static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
  142. {
  143. void __iomem *usb2_base = ch->base;
  144. u32 val = readl(usb2_base + USB2_COMMCTRL);
  145. dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, host);
  146. if (host)
  147. val &= ~USB2_COMMCTRL_OTG_PERI;
  148. else
  149. val |= USB2_COMMCTRL_OTG_PERI;
  150. writel(val, usb2_base + USB2_COMMCTRL);
  151. }
  152. static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
  153. {
  154. void __iomem *usb2_base = ch->base;
  155. u32 val = readl(usb2_base + USB2_LINECTRL1);
  156. dev_vdbg(ch->dev, "%s: %08x, %d, %d\n", __func__, val, dp, dm);
  157. val &= ~(USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
  158. if (dp)
  159. val |= USB2_LINECTRL1_DP_RPD;
  160. if (dm)
  161. val |= USB2_LINECTRL1_DM_RPD;
  162. writel(val, usb2_base + USB2_LINECTRL1);
  163. }
  164. static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
  165. {
  166. void __iomem *usb2_base = ch->base;
  167. u32 vbus_ctrl_reg = USB2_ADPCTRL;
  168. u32 vbus_ctrl_val = USB2_ADPCTRL_DRVVBUS;
  169. u32 val;
  170. dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, vbus);
  171. if (ch->soc_no_adp_ctrl) {
  172. if (ch->vbus)
  173. regulator_hardware_enable(ch->vbus, vbus);
  174. vbus_ctrl_reg = USB2_VBCTRL;
  175. vbus_ctrl_val = USB2_VBCTRL_VBOUT;
  176. }
  177. val = readl(usb2_base + vbus_ctrl_reg);
  178. if (vbus)
  179. val |= vbus_ctrl_val;
  180. else
  181. val &= ~vbus_ctrl_val;
  182. writel(val, usb2_base + vbus_ctrl_reg);
  183. }
  184. static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable)
  185. {
  186. void __iomem *usb2_base = ch->base;
  187. u32 val = readl(usb2_base + USB2_OBINTEN);
  188. if (ch->uses_otg_pins && enable)
  189. val |= ch->obint_enable_bits;
  190. else
  191. val &= ~ch->obint_enable_bits;
  192. writel(val, usb2_base + USB2_OBINTEN);
  193. }
  194. static void rcar_gen3_init_for_host(struct rcar_gen3_chan *ch)
  195. {
  196. rcar_gen3_set_linectrl(ch, 1, 1);
  197. rcar_gen3_set_host_mode(ch, 1);
  198. rcar_gen3_enable_vbus_ctrl(ch, 1);
  199. ch->extcon_host = true;
  200. schedule_work(&ch->work);
  201. }
  202. static void rcar_gen3_init_for_peri(struct rcar_gen3_chan *ch)
  203. {
  204. rcar_gen3_set_linectrl(ch, 0, 1);
  205. rcar_gen3_set_host_mode(ch, 0);
  206. rcar_gen3_enable_vbus_ctrl(ch, 0);
  207. ch->extcon_host = false;
  208. schedule_work(&ch->work);
  209. }
  210. static void rcar_gen3_init_for_b_host(struct rcar_gen3_chan *ch)
  211. {
  212. void __iomem *usb2_base = ch->base;
  213. u32 val;
  214. val = readl(usb2_base + USB2_LINECTRL1);
  215. writel(val | USB2_LINECTRL1_OPMODE_NODRV, usb2_base + USB2_LINECTRL1);
  216. rcar_gen3_set_linectrl(ch, 1, 1);
  217. rcar_gen3_set_host_mode(ch, 1);
  218. rcar_gen3_enable_vbus_ctrl(ch, 0);
  219. val = readl(usb2_base + USB2_LINECTRL1);
  220. writel(val & ~USB2_LINECTRL1_OPMODE_NODRV, usb2_base + USB2_LINECTRL1);
  221. }
  222. static void rcar_gen3_init_for_a_peri(struct rcar_gen3_chan *ch)
  223. {
  224. rcar_gen3_set_linectrl(ch, 0, 1);
  225. rcar_gen3_set_host_mode(ch, 0);
  226. rcar_gen3_enable_vbus_ctrl(ch, 1);
  227. }
  228. static void rcar_gen3_init_from_a_peri_to_a_host(struct rcar_gen3_chan *ch)
  229. {
  230. rcar_gen3_control_otg_irq(ch, 0);
  231. rcar_gen3_enable_vbus_ctrl(ch, 1);
  232. rcar_gen3_init_for_host(ch);
  233. rcar_gen3_control_otg_irq(ch, 1);
  234. }
  235. static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
  236. {
  237. if (!ch->uses_otg_pins)
  238. return (ch->dr_mode == USB_DR_MODE_HOST) ? false : true;
  239. if (ch->soc_no_adp_ctrl)
  240. return !!(readl(ch->base + USB2_LINECTRL1) & USB2_LINECTRL1_USB2_IDMON);
  241. return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
  242. }
  243. static void rcar_gen3_device_recognition(struct rcar_gen3_chan *ch)
  244. {
  245. if (!rcar_gen3_check_id(ch))
  246. rcar_gen3_init_for_host(ch);
  247. else
  248. rcar_gen3_init_for_peri(ch);
  249. }
  250. static bool rcar_gen3_is_host(struct rcar_gen3_chan *ch)
  251. {
  252. return !(readl(ch->base + USB2_COMMCTRL) & USB2_COMMCTRL_OTG_PERI);
  253. }
  254. static enum phy_mode rcar_gen3_get_phy_mode(struct rcar_gen3_chan *ch)
  255. {
  256. if (rcar_gen3_is_host(ch))
  257. return PHY_MODE_USB_HOST;
  258. return PHY_MODE_USB_DEVICE;
  259. }
  260. static bool rcar_gen3_is_any_rphy_initialized(struct rcar_gen3_chan *ch)
  261. {
  262. int i;
  263. for (i = 0; i < NUM_OF_PHYS; i++) {
  264. if (ch->rphys[i].initialized)
  265. return true;
  266. }
  267. return false;
  268. }
  269. static bool rcar_gen3_needs_init_otg(struct rcar_gen3_chan *ch)
  270. {
  271. int i;
  272. for (i = 0; i < NUM_OF_PHYS; i++) {
  273. if (ch->rphys[i].otg_initialized)
  274. return false;
  275. }
  276. return true;
  277. }
  278. static bool rcar_gen3_are_all_rphys_power_off(struct rcar_gen3_chan *ch)
  279. {
  280. int i;
  281. for (i = 0; i < NUM_OF_PHYS; i++) {
  282. if (ch->rphys[i].powered)
  283. return false;
  284. }
  285. return true;
  286. }
  287. static ssize_t role_store(struct device *dev, struct device_attribute *attr,
  288. const char *buf, size_t count)
  289. {
  290. struct rcar_gen3_chan *ch = dev_get_drvdata(dev);
  291. bool is_b_device;
  292. enum phy_mode cur_mode, new_mode;
  293. if (!ch->is_otg_channel || !rcar_gen3_is_any_rphy_initialized(ch))
  294. return -EIO;
  295. if (sysfs_streq(buf, "host"))
  296. new_mode = PHY_MODE_USB_HOST;
  297. else if (sysfs_streq(buf, "peripheral"))
  298. new_mode = PHY_MODE_USB_DEVICE;
  299. else
  300. return -EINVAL;
  301. /* is_b_device: true is B-Device. false is A-Device. */
  302. is_b_device = rcar_gen3_check_id(ch);
  303. cur_mode = rcar_gen3_get_phy_mode(ch);
  304. /* If current and new mode is the same, this returns the error */
  305. if (cur_mode == new_mode)
  306. return -EINVAL;
  307. if (new_mode == PHY_MODE_USB_HOST) { /* And is_host must be false */
  308. if (!is_b_device) /* A-Peripheral */
  309. rcar_gen3_init_from_a_peri_to_a_host(ch);
  310. else /* B-Peripheral */
  311. rcar_gen3_init_for_b_host(ch);
  312. } else { /* And is_host must be true */
  313. if (!is_b_device) /* A-Host */
  314. rcar_gen3_init_for_a_peri(ch);
  315. else /* B-Host */
  316. rcar_gen3_init_for_peri(ch);
  317. }
  318. return count;
  319. }
  320. static ssize_t role_show(struct device *dev, struct device_attribute *attr,
  321. char *buf)
  322. {
  323. struct rcar_gen3_chan *ch = dev_get_drvdata(dev);
  324. if (!ch->is_otg_channel || !rcar_gen3_is_any_rphy_initialized(ch))
  325. return -EIO;
  326. return sprintf(buf, "%s\n", rcar_gen3_is_host(ch) ? "host" :
  327. "peripheral");
  328. }
  329. static DEVICE_ATTR_RW(role);
  330. static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
  331. {
  332. void __iomem *usb2_base = ch->base;
  333. u32 val;
  334. /* Should not use functions of read-modify-write a register */
  335. val = readl(usb2_base + USB2_LINECTRL1);
  336. val = (val & ~USB2_LINECTRL1_DP_RPD) | USB2_LINECTRL1_DPRPD_EN |
  337. USB2_LINECTRL1_DMRPD_EN | USB2_LINECTRL1_DM_RPD;
  338. writel(val, usb2_base + USB2_LINECTRL1);
  339. if (!ch->soc_no_adp_ctrl) {
  340. val = readl(usb2_base + USB2_VBCTRL);
  341. val &= ~USB2_VBCTRL_OCCLREN;
  342. writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
  343. val = readl(usb2_base + USB2_ADPCTRL);
  344. writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
  345. }
  346. msleep(20);
  347. writel(0xffffffff, usb2_base + USB2_OBINTSTA);
  348. writel(ch->obint_enable_bits, usb2_base + USB2_OBINTEN);
  349. rcar_gen3_device_recognition(ch);
  350. }
  351. static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
  352. {
  353. struct rcar_gen3_chan *ch = _ch;
  354. void __iomem *usb2_base = ch->base;
  355. u32 status = readl(usb2_base + USB2_OBINTSTA);
  356. irqreturn_t ret = IRQ_NONE;
  357. if (status & ch->obint_enable_bits) {
  358. dev_vdbg(ch->dev, "%s: %08x\n", __func__, status);
  359. writel(ch->obint_enable_bits, usb2_base + USB2_OBINTSTA);
  360. rcar_gen3_device_recognition(ch);
  361. ret = IRQ_HANDLED;
  362. }
  363. return ret;
  364. }
  365. static int rcar_gen3_phy_usb2_init(struct phy *p)
  366. {
  367. struct rcar_gen3_phy *rphy = phy_get_drvdata(p);
  368. struct rcar_gen3_chan *channel = rphy->ch;
  369. void __iomem *usb2_base = channel->base;
  370. u32 val;
  371. int ret;
  372. if (!rcar_gen3_is_any_rphy_initialized(channel) && channel->irq >= 0) {
  373. INIT_WORK(&channel->work, rcar_gen3_phy_usb2_work);
  374. ret = request_irq(channel->irq, rcar_gen3_phy_usb2_irq,
  375. IRQF_SHARED, dev_name(channel->dev), channel);
  376. if (ret < 0) {
  377. dev_err(channel->dev, "No irq handler (%d)\n", channel->irq);
  378. return ret;
  379. }
  380. }
  381. /* Initialize USB2 part */
  382. val = readl(usb2_base + USB2_INT_ENABLE);
  383. val |= USB2_INT_ENABLE_UCOM_INTEN | rphy->int_enable_bits;
  384. writel(val, usb2_base + USB2_INT_ENABLE);
  385. writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
  386. writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
  387. /* Initialize otg part */
  388. if (channel->is_otg_channel) {
  389. if (rcar_gen3_needs_init_otg(channel))
  390. rcar_gen3_init_otg(channel);
  391. rphy->otg_initialized = true;
  392. }
  393. rphy->initialized = true;
  394. return 0;
  395. }
  396. static int rcar_gen3_phy_usb2_exit(struct phy *p)
  397. {
  398. struct rcar_gen3_phy *rphy = phy_get_drvdata(p);
  399. struct rcar_gen3_chan *channel = rphy->ch;
  400. void __iomem *usb2_base = channel->base;
  401. u32 val;
  402. rphy->initialized = false;
  403. if (channel->is_otg_channel)
  404. rphy->otg_initialized = false;
  405. val = readl(usb2_base + USB2_INT_ENABLE);
  406. val &= ~rphy->int_enable_bits;
  407. if (!rcar_gen3_is_any_rphy_initialized(channel))
  408. val &= ~USB2_INT_ENABLE_UCOM_INTEN;
  409. writel(val, usb2_base + USB2_INT_ENABLE);
  410. if (channel->irq >= 0 && !rcar_gen3_is_any_rphy_initialized(channel))
  411. free_irq(channel->irq, channel);
  412. return 0;
  413. }
  414. static int rcar_gen3_phy_usb2_power_on(struct phy *p)
  415. {
  416. struct rcar_gen3_phy *rphy = phy_get_drvdata(p);
  417. struct rcar_gen3_chan *channel = rphy->ch;
  418. void __iomem *usb2_base = channel->base;
  419. u32 val;
  420. int ret = 0;
  421. mutex_lock(&channel->lock);
  422. if (!rcar_gen3_are_all_rphys_power_off(channel))
  423. goto out;
  424. if (channel->vbus) {
  425. ret = regulator_enable(channel->vbus);
  426. if (ret)
  427. goto out;
  428. }
  429. val = readl(usb2_base + USB2_USBCTR);
  430. val |= USB2_USBCTR_PLL_RST;
  431. writel(val, usb2_base + USB2_USBCTR);
  432. val &= ~USB2_USBCTR_PLL_RST;
  433. writel(val, usb2_base + USB2_USBCTR);
  434. out:
  435. /* The powered flag should be set for any other phys anyway */
  436. rphy->powered = true;
  437. mutex_unlock(&channel->lock);
  438. return 0;
  439. }
  440. static int rcar_gen3_phy_usb2_power_off(struct phy *p)
  441. {
  442. struct rcar_gen3_phy *rphy = phy_get_drvdata(p);
  443. struct rcar_gen3_chan *channel = rphy->ch;
  444. int ret = 0;
  445. mutex_lock(&channel->lock);
  446. rphy->powered = false;
  447. if (!rcar_gen3_are_all_rphys_power_off(channel))
  448. goto out;
  449. if (channel->vbus)
  450. ret = regulator_disable(channel->vbus);
  451. out:
  452. mutex_unlock(&channel->lock);
  453. return ret;
  454. }
  455. static const struct phy_ops rcar_gen3_phy_usb2_ops = {
  456. .init = rcar_gen3_phy_usb2_init,
  457. .exit = rcar_gen3_phy_usb2_exit,
  458. .power_on = rcar_gen3_phy_usb2_power_on,
  459. .power_off = rcar_gen3_phy_usb2_power_off,
  460. .owner = THIS_MODULE,
  461. };
  462. static const struct phy_ops rz_g1c_phy_usb2_ops = {
  463. .init = rcar_gen3_phy_usb2_init,
  464. .exit = rcar_gen3_phy_usb2_exit,
  465. .owner = THIS_MODULE,
  466. };
  467. static const struct rcar_gen3_phy_drv_data rcar_gen3_phy_usb2_data = {
  468. .phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
  469. .no_adp_ctrl = false,
  470. };
  471. static const struct rcar_gen3_phy_drv_data rz_g1c_phy_usb2_data = {
  472. .phy_usb2_ops = &rz_g1c_phy_usb2_ops,
  473. .no_adp_ctrl = false,
  474. };
  475. static const struct rcar_gen3_phy_drv_data rz_g2l_phy_usb2_data = {
  476. .phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
  477. .no_adp_ctrl = true,
  478. };
  479. static const struct rcar_gen3_phy_drv_data rz_g3s_phy_usb2_data = {
  480. .phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
  481. .no_adp_ctrl = true,
  482. .init_bus = true,
  483. };
  484. static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
  485. {
  486. .compatible = "renesas,usb2-phy-r8a77470",
  487. .data = &rz_g1c_phy_usb2_data,
  488. },
  489. {
  490. .compatible = "renesas,usb2-phy-r8a7795",
  491. .data = &rcar_gen3_phy_usb2_data,
  492. },
  493. {
  494. .compatible = "renesas,usb2-phy-r8a7796",
  495. .data = &rcar_gen3_phy_usb2_data,
  496. },
  497. {
  498. .compatible = "renesas,usb2-phy-r8a77965",
  499. .data = &rcar_gen3_phy_usb2_data,
  500. },
  501. {
  502. .compatible = "renesas,rzg2l-usb2-phy",
  503. .data = &rz_g2l_phy_usb2_data,
  504. },
  505. {
  506. .compatible = "renesas,usb2-phy-r9a08g045",
  507. .data = &rz_g3s_phy_usb2_data,
  508. },
  509. {
  510. .compatible = "renesas,rcar-gen3-usb2-phy",
  511. .data = &rcar_gen3_phy_usb2_data,
  512. },
  513. { /* sentinel */ },
  514. };
  515. MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table);
  516. static const unsigned int rcar_gen3_phy_cable[] = {
  517. EXTCON_USB,
  518. EXTCON_USB_HOST,
  519. EXTCON_NONE,
  520. };
  521. static struct phy *rcar_gen3_phy_usb2_xlate(struct device *dev,
  522. const struct of_phandle_args *args)
  523. {
  524. struct rcar_gen3_chan *ch = dev_get_drvdata(dev);
  525. if (args->args_count == 0) /* For old version dts */
  526. return ch->rphys[PHY_INDEX_BOTH_HC].phy;
  527. else if (args->args_count > 1) /* Prevent invalid args count */
  528. return ERR_PTR(-ENODEV);
  529. if (args->args[0] >= NUM_OF_PHYS)
  530. return ERR_PTR(-ENODEV);
  531. return ch->rphys[args->args[0]].phy;
  532. }
  533. static enum usb_dr_mode rcar_gen3_get_dr_mode(struct device_node *np)
  534. {
  535. enum usb_dr_mode candidate = USB_DR_MODE_UNKNOWN;
  536. int i;
  537. /*
  538. * If one of device nodes has other dr_mode except UNKNOWN,
  539. * this function returns UNKNOWN. To achieve backward compatibility,
  540. * this loop starts the index as 0.
  541. */
  542. for (i = 0; i < NUM_OF_PHYS; i++) {
  543. enum usb_dr_mode mode = of_usb_get_dr_mode_by_phy(np, i);
  544. if (mode != USB_DR_MODE_UNKNOWN) {
  545. if (candidate == USB_DR_MODE_UNKNOWN)
  546. candidate = mode;
  547. else if (candidate != mode)
  548. return USB_DR_MODE_UNKNOWN;
  549. }
  550. }
  551. return candidate;
  552. }
  553. static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel)
  554. {
  555. struct device *dev = channel->dev;
  556. int ret;
  557. u32 val;
  558. channel->rstc = devm_reset_control_array_get_shared(dev);
  559. if (IS_ERR(channel->rstc))
  560. return PTR_ERR(channel->rstc);
  561. ret = pm_runtime_resume_and_get(dev);
  562. if (ret)
  563. return ret;
  564. ret = reset_control_deassert(channel->rstc);
  565. if (ret)
  566. goto rpm_put;
  567. val = readl(channel->base + USB2_AHB_BUS_CTR);
  568. val &= ~USB2_AHB_BUS_CTR_MBL_MASK;
  569. val |= USB2_AHB_BUS_CTR_MBL_INCR4;
  570. writel(val, channel->base + USB2_AHB_BUS_CTR);
  571. rpm_put:
  572. pm_runtime_put(dev);
  573. return ret;
  574. }
  575. static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
  576. {
  577. const struct rcar_gen3_phy_drv_data *phy_data;
  578. struct device *dev = &pdev->dev;
  579. struct rcar_gen3_chan *channel;
  580. struct phy_provider *provider;
  581. int ret = 0, i;
  582. if (!dev->of_node) {
  583. dev_err(dev, "This driver needs device tree\n");
  584. return -EINVAL;
  585. }
  586. channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL);
  587. if (!channel)
  588. return -ENOMEM;
  589. channel->base = devm_platform_ioremap_resource(pdev, 0);
  590. if (IS_ERR(channel->base))
  591. return PTR_ERR(channel->base);
  592. channel->obint_enable_bits = USB2_OBINT_BITS;
  593. /* get irq number here and request_irq for OTG in phy_init */
  594. channel->irq = platform_get_irq_optional(pdev, 0);
  595. channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
  596. if (channel->dr_mode != USB_DR_MODE_UNKNOWN) {
  597. channel->is_otg_channel = true;
  598. channel->uses_otg_pins = !of_property_read_bool(dev->of_node,
  599. "renesas,no-otg-pins");
  600. channel->extcon = devm_extcon_dev_allocate(dev,
  601. rcar_gen3_phy_cable);
  602. if (IS_ERR(channel->extcon))
  603. return PTR_ERR(channel->extcon);
  604. ret = devm_extcon_dev_register(dev, channel->extcon);
  605. if (ret < 0) {
  606. dev_err(dev, "Failed to register extcon\n");
  607. return ret;
  608. }
  609. }
  610. /*
  611. * devm_phy_create() will call pm_runtime_enable(&phy->dev);
  612. * And then, phy-core will manage runtime pm for this device.
  613. */
  614. pm_runtime_enable(dev);
  615. phy_data = of_device_get_match_data(dev);
  616. if (!phy_data) {
  617. ret = -EINVAL;
  618. goto error;
  619. }
  620. platform_set_drvdata(pdev, channel);
  621. channel->dev = dev;
  622. if (phy_data->init_bus) {
  623. ret = rcar_gen3_phy_usb2_init_bus(channel);
  624. if (ret)
  625. goto error;
  626. }
  627. channel->soc_no_adp_ctrl = phy_data->no_adp_ctrl;
  628. if (phy_data->no_adp_ctrl)
  629. channel->obint_enable_bits = USB2_OBINT_IDCHG_EN;
  630. mutex_init(&channel->lock);
  631. for (i = 0; i < NUM_OF_PHYS; i++) {
  632. channel->rphys[i].phy = devm_phy_create(dev, NULL,
  633. phy_data->phy_usb2_ops);
  634. if (IS_ERR(channel->rphys[i].phy)) {
  635. dev_err(dev, "Failed to create USB2 PHY\n");
  636. ret = PTR_ERR(channel->rphys[i].phy);
  637. goto error;
  638. }
  639. channel->rphys[i].ch = channel;
  640. channel->rphys[i].int_enable_bits = rcar_gen3_int_enable[i];
  641. phy_set_drvdata(channel->rphys[i].phy, &channel->rphys[i]);
  642. }
  643. if (channel->soc_no_adp_ctrl && channel->is_otg_channel)
  644. channel->vbus = devm_regulator_get_exclusive(dev, "vbus");
  645. else
  646. channel->vbus = devm_regulator_get_optional(dev, "vbus");
  647. if (IS_ERR(channel->vbus)) {
  648. if (PTR_ERR(channel->vbus) == -EPROBE_DEFER) {
  649. ret = PTR_ERR(channel->vbus);
  650. goto error;
  651. }
  652. channel->vbus = NULL;
  653. }
  654. provider = devm_of_phy_provider_register(dev, rcar_gen3_phy_usb2_xlate);
  655. if (IS_ERR(provider)) {
  656. dev_err(dev, "Failed to register PHY provider\n");
  657. ret = PTR_ERR(provider);
  658. goto error;
  659. } else if (channel->is_otg_channel) {
  660. ret = device_create_file(dev, &dev_attr_role);
  661. if (ret < 0)
  662. goto error;
  663. }
  664. return 0;
  665. error:
  666. pm_runtime_disable(dev);
  667. return ret;
  668. }
  669. static void rcar_gen3_phy_usb2_remove(struct platform_device *pdev)
  670. {
  671. struct rcar_gen3_chan *channel = platform_get_drvdata(pdev);
  672. if (channel->is_otg_channel)
  673. device_remove_file(&pdev->dev, &dev_attr_role);
  674. reset_control_assert(channel->rstc);
  675. pm_runtime_disable(&pdev->dev);
  676. };
  677. static struct platform_driver rcar_gen3_phy_usb2_driver = {
  678. .driver = {
  679. .name = "phy_rcar_gen3_usb2",
  680. .of_match_table = rcar_gen3_phy_usb2_match_table,
  681. },
  682. .probe = rcar_gen3_phy_usb2_probe,
  683. .remove_new = rcar_gen3_phy_usb2_remove,
  684. };
  685. module_platform_driver(rcar_gen3_phy_usb2_driver);
  686. MODULE_LICENSE("GPL v2");
  687. MODULE_DESCRIPTION("Renesas R-Car Gen3 USB 2.0 PHY");
  688. MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");