phy-twl4030-usb.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
  4. *
  5. * Copyright (C) 2004-2007 Texas Instruments
  6. * Copyright (C) 2008 Nokia Corporation
  7. * Contact: Felipe Balbi <felipe.balbi@nokia.com>
  8. *
  9. * Current status:
  10. * - HS USB ULPI mode works.
  11. * - 3-pin mode support may be added in future.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/of.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/workqueue.h>
  19. #include <linux/io.h>
  20. #include <linux/delay.h>
  21. #include <linux/usb/otg.h>
  22. #include <linux/phy/phy.h>
  23. #include <linux/pm_runtime.h>
  24. #include <linux/usb/musb.h>
  25. #include <linux/usb/ulpi.h>
  26. #include <linux/mfd/twl.h>
  27. #include <linux/regulator/consumer.h>
  28. #include <linux/err.h>
  29. #include <linux/slab.h>
  30. /* Register defines */
  31. #define MCPC_CTRL 0x30
  32. #define MCPC_CTRL_RTSOL (1 << 7)
  33. #define MCPC_CTRL_EXTSWR (1 << 6)
  34. #define MCPC_CTRL_EXTSWC (1 << 5)
  35. #define MCPC_CTRL_VOICESW (1 << 4)
  36. #define MCPC_CTRL_OUT64K (1 << 3)
  37. #define MCPC_CTRL_RTSCTSSW (1 << 2)
  38. #define MCPC_CTRL_HS_UART (1 << 0)
  39. #define MCPC_IO_CTRL 0x33
  40. #define MCPC_IO_CTRL_MICBIASEN (1 << 5)
  41. #define MCPC_IO_CTRL_CTS_NPU (1 << 4)
  42. #define MCPC_IO_CTRL_RXD_PU (1 << 3)
  43. #define MCPC_IO_CTRL_TXDTYP (1 << 2)
  44. #define MCPC_IO_CTRL_CTSTYP (1 << 1)
  45. #define MCPC_IO_CTRL_RTSTYP (1 << 0)
  46. #define MCPC_CTRL2 0x36
  47. #define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
  48. #define OTHER_FUNC_CTRL 0x80
  49. #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
  50. #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
  51. #define OTHER_IFC_CTRL 0x83
  52. #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
  53. #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
  54. #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
  55. #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3)
  56. #define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2)
  57. #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
  58. #define OTHER_INT_EN_RISE 0x86
  59. #define OTHER_INT_EN_FALL 0x89
  60. #define OTHER_INT_STS 0x8C
  61. #define OTHER_INT_LATCH 0x8D
  62. #define OTHER_INT_VB_SESS_VLD (1 << 7)
  63. #define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */
  64. #define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */
  65. #define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */
  66. #define OTHER_INT_MANU (1 << 1)
  67. #define OTHER_INT_ABNORMAL_STRESS (1 << 0)
  68. #define ID_STATUS 0x96
  69. #define ID_RES_FLOAT (1 << 4)
  70. #define ID_RES_440K (1 << 3)
  71. #define ID_RES_200K (1 << 2)
  72. #define ID_RES_102K (1 << 1)
  73. #define ID_RES_GND (1 << 0)
  74. #define POWER_CTRL 0xAC
  75. #define POWER_CTRL_OTG_ENAB (1 << 5)
  76. #define OTHER_IFC_CTRL2 0xAF
  77. #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
  78. #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
  79. #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
  80. #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */
  81. #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0)
  82. #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
  83. #define REG_CTRL_EN 0xB2
  84. #define REG_CTRL_ERROR 0xB5
  85. #define ULPI_I2C_CONFLICT_INTEN (1 << 0)
  86. #define OTHER_FUNC_CTRL2 0xB8
  87. #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
  88. /* following registers do not have separate _clr and _set registers */
  89. #define VBUS_DEBOUNCE 0xC0
  90. #define ID_DEBOUNCE 0xC1
  91. #define VBAT_TIMER 0xD3
  92. #define PHY_PWR_CTRL 0xFD
  93. #define PHY_PWR_PHYPWD (1 << 0)
  94. #define PHY_CLK_CTRL 0xFE
  95. #define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2)
  96. #define PHY_CLK_CTRL_CLK32K_EN (1 << 1)
  97. #define REQ_PHY_DPLL_CLK (1 << 0)
  98. #define PHY_CLK_CTRL_STS 0xFF
  99. #define PHY_DPLL_CLK (1 << 0)
  100. /* In module TWL_MODULE_PM_MASTER */
  101. #define STS_HW_CONDITIONS 0x0F
  102. /* In module TWL_MODULE_PM_RECEIVER */
  103. #define VUSB_DEDICATED1 0x7D
  104. #define VUSB_DEDICATED2 0x7E
  105. #define VUSB1V5_DEV_GRP 0x71
  106. #define VUSB1V5_TYPE 0x72
  107. #define VUSB1V5_REMAP 0x73
  108. #define VUSB1V8_DEV_GRP 0x74
  109. #define VUSB1V8_TYPE 0x75
  110. #define VUSB1V8_REMAP 0x76
  111. #define VUSB3V1_DEV_GRP 0x77
  112. #define VUSB3V1_TYPE 0x78
  113. #define VUSB3V1_REMAP 0x79
  114. /* In module TWL4030_MODULE_INTBR */
  115. #define PMBR1 0x0D
  116. #define GPIO_USB_4PIN_ULPI_2430C (3 << 0)
  117. static irqreturn_t twl4030_usb_irq(int irq, void *_twl);
  118. /*
  119. * If VBUS is valid or ID is ground, then we know a
  120. * cable is present and we need to be runtime-enabled
  121. */
  122. static inline bool cable_present(enum musb_vbus_id_status stat)
  123. {
  124. return stat == MUSB_VBUS_VALID ||
  125. stat == MUSB_ID_GROUND;
  126. }
  127. struct twl4030_usb {
  128. struct usb_phy phy;
  129. struct device *dev;
  130. /* TWL4030 internal USB regulator supplies */
  131. struct regulator *usb1v5;
  132. struct regulator *usb1v8;
  133. struct regulator *usb3v1;
  134. /* for vbus reporting with irqs disabled */
  135. struct mutex lock;
  136. /* pin configuration */
  137. enum twl4030_usb_mode usb_mode;
  138. int irq;
  139. enum musb_vbus_id_status linkstat;
  140. atomic_t connected;
  141. bool vbus_supplied;
  142. bool musb_mailbox_pending;
  143. unsigned long runtime_suspended:1;
  144. unsigned long needs_resume:1;
  145. struct delayed_work id_workaround_work;
  146. };
  147. /* internal define on top of container_of */
  148. #define phy_to_twl(x) container_of((x), struct twl4030_usb, phy)
  149. /*-------------------------------------------------------------------------*/
  150. static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
  151. u8 module, u8 data, u8 address)
  152. {
  153. u8 check = 0xFF;
  154. if ((twl_i2c_write_u8(module, data, address) >= 0) &&
  155. (twl_i2c_read_u8(module, &check, address) >= 0) &&
  156. (check == data))
  157. return 0;
  158. dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
  159. 1, module, address, check, data);
  160. /* Failed once: Try again */
  161. if ((twl_i2c_write_u8(module, data, address) >= 0) &&
  162. (twl_i2c_read_u8(module, &check, address) >= 0) &&
  163. (check == data))
  164. return 0;
  165. dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
  166. 2, module, address, check, data);
  167. /* Failed again: Return error */
  168. return -EBUSY;
  169. }
  170. #define twl4030_usb_write_verify(twl, address, data) \
  171. twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address))
  172. static inline int twl4030_usb_write(struct twl4030_usb *twl,
  173. u8 address, u8 data)
  174. {
  175. int ret = 0;
  176. ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address);
  177. if (ret < 0)
  178. dev_dbg(twl->dev,
  179. "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
  180. return ret;
  181. }
  182. static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
  183. {
  184. u8 data;
  185. int ret = 0;
  186. ret = twl_i2c_read_u8(module, &data, address);
  187. if (ret >= 0)
  188. ret = data;
  189. else
  190. dev_dbg(twl->dev,
  191. "TWL4030:readb[0x%x,0x%x] Error %d\n",
  192. module, address, ret);
  193. return ret;
  194. }
  195. static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
  196. {
  197. return twl4030_readb(twl, TWL_MODULE_USB, address);
  198. }
  199. /*-------------------------------------------------------------------------*/
  200. static inline int
  201. twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
  202. {
  203. return twl4030_usb_write(twl, ULPI_SET(reg), bits);
  204. }
  205. static inline int
  206. twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
  207. {
  208. return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
  209. }
  210. /*-------------------------------------------------------------------------*/
  211. static bool twl4030_is_driving_vbus(struct twl4030_usb *twl)
  212. {
  213. int ret;
  214. ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS);
  215. if (ret < 0 || !(ret & PHY_DPLL_CLK))
  216. /*
  217. * if clocks are off, registers are not updated,
  218. * but we can assume we don't drive VBUS in this case
  219. */
  220. return false;
  221. ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
  222. if (ret < 0)
  223. return false;
  224. return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false;
  225. }
  226. static enum musb_vbus_id_status
  227. twl4030_usb_linkstat(struct twl4030_usb *twl)
  228. {
  229. int status;
  230. enum musb_vbus_id_status linkstat = MUSB_UNKNOWN;
  231. twl->vbus_supplied = false;
  232. /*
  233. * For ID/VBUS sensing, see manual section 15.4.8 ...
  234. * except when using only battery backup power, two
  235. * comparators produce VBUS_PRES and ID_PRES signals,
  236. * which don't match docs elsewhere. But ... BIT(7)
  237. * and BIT(2) of STS_HW_CONDITIONS, respectively, do
  238. * seem to match up. If either is true the USB_PRES
  239. * signal is active, the OTG module is activated, and
  240. * its interrupt may be raised (may wake the system).
  241. */
  242. status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS);
  243. if (status < 0)
  244. dev_err(twl->dev, "USB link status err %d\n", status);
  245. else if (status & (BIT(7) | BIT(2))) {
  246. if (status & BIT(7)) {
  247. if (twl4030_is_driving_vbus(twl))
  248. status &= ~BIT(7);
  249. else
  250. twl->vbus_supplied = true;
  251. }
  252. if (status & BIT(2))
  253. linkstat = MUSB_ID_GROUND;
  254. else if (status & BIT(7))
  255. linkstat = MUSB_VBUS_VALID;
  256. else
  257. linkstat = MUSB_VBUS_OFF;
  258. } else {
  259. if (twl->linkstat != MUSB_UNKNOWN)
  260. linkstat = MUSB_VBUS_OFF;
  261. }
  262. kobject_uevent(&twl->dev->kobj, linkstat == MUSB_VBUS_VALID
  263. ? KOBJ_ONLINE : KOBJ_OFFLINE);
  264. dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
  265. status, status, linkstat);
  266. /* REVISIT this assumes host and peripheral controllers
  267. * are registered, and that both are active...
  268. */
  269. return linkstat;
  270. }
  271. static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
  272. {
  273. twl->usb_mode = mode;
  274. switch (mode) {
  275. case T2_USB_MODE_ULPI:
  276. twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
  277. ULPI_IFC_CTRL_CARKITMODE);
  278. twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
  279. twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
  280. ULPI_FUNC_CTRL_XCVRSEL_MASK |
  281. ULPI_FUNC_CTRL_OPMODE_MASK);
  282. break;
  283. case -1:
  284. /* FIXME: power on defaults */
  285. break;
  286. default:
  287. dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
  288. mode);
  289. break;
  290. }
  291. }
  292. static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
  293. {
  294. unsigned long timeout;
  295. int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
  296. if (val >= 0) {
  297. if (on) {
  298. /* enable DPLL to access PHY registers over I2C */
  299. val |= REQ_PHY_DPLL_CLK;
  300. WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
  301. (u8)val) < 0);
  302. timeout = jiffies + HZ;
  303. while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
  304. PHY_DPLL_CLK)
  305. && time_before(jiffies, timeout))
  306. udelay(10);
  307. if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
  308. PHY_DPLL_CLK))
  309. dev_err(twl->dev, "Timeout setting T2 HSUSB "
  310. "PHY DPLL clock\n");
  311. } else {
  312. /* let ULPI control the DPLL clock */
  313. val &= ~REQ_PHY_DPLL_CLK;
  314. WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
  315. (u8)val) < 0);
  316. }
  317. }
  318. }
  319. static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
  320. {
  321. u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
  322. if (on)
  323. pwr &= ~PHY_PWR_PHYPWD;
  324. else
  325. pwr |= PHY_PWR_PHYPWD;
  326. WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
  327. }
  328. static int twl4030_usb_runtime_suspend(struct device *dev);
  329. static int twl4030_usb_runtime_resume(struct device *dev);
  330. static int __maybe_unused twl4030_usb_suspend(struct device *dev)
  331. {
  332. struct twl4030_usb *twl = dev_get_drvdata(dev);
  333. /*
  334. * we need enabled runtime on resume,
  335. * so turn irq off here, so we do not get it early
  336. * note: wakeup on usb plug works independently of this
  337. */
  338. dev_dbg(twl->dev, "%s\n", __func__);
  339. disable_irq(twl->irq);
  340. if (!twl->runtime_suspended && !atomic_read(&twl->connected)) {
  341. twl4030_usb_runtime_suspend(dev);
  342. twl->needs_resume = 1;
  343. }
  344. return 0;
  345. }
  346. static int __maybe_unused twl4030_usb_resume(struct device *dev)
  347. {
  348. struct twl4030_usb *twl = dev_get_drvdata(dev);
  349. dev_dbg(twl->dev, "%s\n", __func__);
  350. enable_irq(twl->irq);
  351. if (twl->needs_resume)
  352. twl4030_usb_runtime_resume(dev);
  353. /* check whether cable status changed */
  354. twl4030_usb_irq(0, twl);
  355. twl->runtime_suspended = 0;
  356. return 0;
  357. }
  358. static int __maybe_unused twl4030_usb_runtime_suspend(struct device *dev)
  359. {
  360. struct twl4030_usb *twl = dev_get_drvdata(dev);
  361. dev_dbg(twl->dev, "%s\n", __func__);
  362. __twl4030_phy_power(twl, 0);
  363. regulator_disable(twl->usb1v5);
  364. regulator_disable(twl->usb1v8);
  365. regulator_disable(twl->usb3v1);
  366. twl->runtime_suspended = 1;
  367. return 0;
  368. }
  369. static int __maybe_unused twl4030_usb_runtime_resume(struct device *dev)
  370. {
  371. struct twl4030_usb *twl = dev_get_drvdata(dev);
  372. int res;
  373. dev_dbg(twl->dev, "%s\n", __func__);
  374. res = regulator_enable(twl->usb3v1);
  375. if (res)
  376. dev_err(twl->dev, "Failed to enable usb3v1\n");
  377. res = regulator_enable(twl->usb1v8);
  378. if (res)
  379. dev_err(twl->dev, "Failed to enable usb1v8\n");
  380. /*
  381. * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
  382. * in twl4030) resets the VUSB_DEDICATED2 register. This reset
  383. * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
  384. * SLEEP. We work around this by clearing the bit after usv3v1
  385. * is re-activated. This ensures that VUSB3V1 is really active.
  386. */
  387. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
  388. res = regulator_enable(twl->usb1v5);
  389. if (res)
  390. dev_err(twl->dev, "Failed to enable usb1v5\n");
  391. __twl4030_phy_power(twl, 1);
  392. twl4030_usb_write(twl, PHY_CLK_CTRL,
  393. twl4030_usb_read(twl, PHY_CLK_CTRL) |
  394. (PHY_CLK_CTRL_CLOCKGATING_EN |
  395. PHY_CLK_CTRL_CLK32K_EN));
  396. twl4030_i2c_access(twl, 1);
  397. twl4030_usb_set_mode(twl, twl->usb_mode);
  398. if (twl->usb_mode == T2_USB_MODE_ULPI)
  399. twl4030_i2c_access(twl, 0);
  400. /*
  401. * According to the TPS65950 TRM, there has to be at least 50ms
  402. * delay between setting POWER_CTRL_OTG_ENAB and enabling charging
  403. * so wait here so that a fully enabled phy can be expected after
  404. * resume
  405. */
  406. msleep(50);
  407. return 0;
  408. }
  409. static int twl4030_phy_power_off(struct phy *phy)
  410. {
  411. struct twl4030_usb *twl = phy_get_drvdata(phy);
  412. dev_dbg(twl->dev, "%s\n", __func__);
  413. return 0;
  414. }
  415. static int twl4030_phy_power_on(struct phy *phy)
  416. {
  417. struct twl4030_usb *twl = phy_get_drvdata(phy);
  418. dev_dbg(twl->dev, "%s\n", __func__);
  419. pm_runtime_get_sync(twl->dev);
  420. schedule_delayed_work(&twl->id_workaround_work, HZ);
  421. pm_runtime_mark_last_busy(twl->dev);
  422. pm_runtime_put_autosuspend(twl->dev);
  423. return 0;
  424. }
  425. static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
  426. {
  427. /* Enable writing to power configuration registers */
  428. twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
  429. TWL4030_PM_MASTER_PROTECT_KEY);
  430. twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
  431. TWL4030_PM_MASTER_PROTECT_KEY);
  432. /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
  433. /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
  434. /* input to VUSB3V1 LDO is from VBAT, not VBUS */
  435. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
  436. /* Initialize 3.1V regulator */
  437. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
  438. twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1");
  439. if (IS_ERR(twl->usb3v1))
  440. return -ENODEV;
  441. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
  442. /* Initialize 1.5V regulator */
  443. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
  444. twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5");
  445. if (IS_ERR(twl->usb1v5))
  446. return -ENODEV;
  447. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
  448. /* Initialize 1.8V regulator */
  449. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
  450. twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8");
  451. if (IS_ERR(twl->usb1v8))
  452. return -ENODEV;
  453. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
  454. /* disable access to power configuration registers */
  455. twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
  456. TWL4030_PM_MASTER_PROTECT_KEY);
  457. return 0;
  458. }
  459. static ssize_t vbus_show(struct device *dev,
  460. struct device_attribute *attr, char *buf)
  461. {
  462. struct twl4030_usb *twl = dev_get_drvdata(dev);
  463. int ret = -EINVAL;
  464. mutex_lock(&twl->lock);
  465. ret = sprintf(buf, "%s\n",
  466. twl->vbus_supplied ? "on" : "off");
  467. mutex_unlock(&twl->lock);
  468. return ret;
  469. }
  470. static DEVICE_ATTR_RO(vbus);
  471. static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
  472. {
  473. struct twl4030_usb *twl = _twl;
  474. enum musb_vbus_id_status status;
  475. int err;
  476. status = twl4030_usb_linkstat(twl);
  477. mutex_lock(&twl->lock);
  478. twl->linkstat = status;
  479. mutex_unlock(&twl->lock);
  480. if (cable_present(status)) {
  481. if (atomic_add_unless(&twl->connected, 1, 1)) {
  482. dev_dbg(twl->dev, "%s: cable connected %i\n",
  483. __func__, status);
  484. pm_runtime_get_sync(twl->dev);
  485. twl->musb_mailbox_pending = true;
  486. }
  487. } else {
  488. if (atomic_add_unless(&twl->connected, -1, 0)) {
  489. dev_dbg(twl->dev, "%s: cable disconnected %i\n",
  490. __func__, status);
  491. pm_runtime_mark_last_busy(twl->dev);
  492. pm_runtime_put_autosuspend(twl->dev);
  493. twl->musb_mailbox_pending = true;
  494. }
  495. }
  496. if (twl->musb_mailbox_pending) {
  497. err = musb_mailbox(status);
  498. if (!err)
  499. twl->musb_mailbox_pending = false;
  500. }
  501. /* don't schedule during sleep - irq works right then */
  502. if (status == MUSB_ID_GROUND && pm_runtime_active(twl->dev)) {
  503. cancel_delayed_work(&twl->id_workaround_work);
  504. schedule_delayed_work(&twl->id_workaround_work, HZ);
  505. }
  506. if (irq)
  507. sysfs_notify(&twl->dev->kobj, NULL, "vbus");
  508. return IRQ_HANDLED;
  509. }
  510. static void twl4030_id_workaround_work(struct work_struct *work)
  511. {
  512. struct twl4030_usb *twl = container_of(work, struct twl4030_usb,
  513. id_workaround_work.work);
  514. twl4030_usb_irq(0, twl);
  515. }
  516. static int twl4030_phy_init(struct phy *phy)
  517. {
  518. struct twl4030_usb *twl = phy_get_drvdata(phy);
  519. pm_runtime_get_sync(twl->dev);
  520. twl->linkstat = MUSB_UNKNOWN;
  521. schedule_delayed_work(&twl->id_workaround_work, HZ);
  522. pm_runtime_mark_last_busy(twl->dev);
  523. pm_runtime_put_autosuspend(twl->dev);
  524. return 0;
  525. }
  526. static int twl4030_set_peripheral(struct usb_otg *otg,
  527. struct usb_gadget *gadget)
  528. {
  529. if (!otg)
  530. return -ENODEV;
  531. otg->gadget = gadget;
  532. if (!gadget)
  533. otg->state = OTG_STATE_UNDEFINED;
  534. return 0;
  535. }
  536. static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
  537. {
  538. if (!otg)
  539. return -ENODEV;
  540. otg->host = host;
  541. if (!host)
  542. otg->state = OTG_STATE_UNDEFINED;
  543. return 0;
  544. }
  545. static const struct phy_ops ops = {
  546. .init = twl4030_phy_init,
  547. .power_on = twl4030_phy_power_on,
  548. .power_off = twl4030_phy_power_off,
  549. .owner = THIS_MODULE,
  550. };
  551. static const struct dev_pm_ops twl4030_usb_pm_ops = {
  552. SET_RUNTIME_PM_OPS(twl4030_usb_runtime_suspend,
  553. twl4030_usb_runtime_resume, NULL)
  554. SET_SYSTEM_SLEEP_PM_OPS(twl4030_usb_suspend, twl4030_usb_resume)
  555. };
  556. static int twl4030_usb_probe(struct platform_device *pdev)
  557. {
  558. struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev);
  559. struct twl4030_usb *twl;
  560. struct phy *phy;
  561. int status, err;
  562. struct usb_otg *otg;
  563. struct device_node *np = pdev->dev.of_node;
  564. struct phy_provider *phy_provider;
  565. twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL);
  566. if (!twl)
  567. return -ENOMEM;
  568. if (np)
  569. of_property_read_u32(np, "usb_mode",
  570. (enum twl4030_usb_mode *)&twl->usb_mode);
  571. else if (pdata) {
  572. twl->usb_mode = pdata->usb_mode;
  573. } else {
  574. dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
  575. return -EINVAL;
  576. }
  577. otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
  578. if (!otg)
  579. return -ENOMEM;
  580. twl->dev = &pdev->dev;
  581. twl->irq = platform_get_irq(pdev, 0);
  582. twl->vbus_supplied = false;
  583. twl->linkstat = MUSB_UNKNOWN;
  584. twl->musb_mailbox_pending = false;
  585. twl->phy.dev = twl->dev;
  586. twl->phy.label = "twl4030";
  587. twl->phy.otg = otg;
  588. twl->phy.type = USB_PHY_TYPE_USB2;
  589. otg->usb_phy = &twl->phy;
  590. otg->set_host = twl4030_set_host;
  591. otg->set_peripheral = twl4030_set_peripheral;
  592. phy = devm_phy_create(twl->dev, NULL, &ops);
  593. if (IS_ERR(phy)) {
  594. dev_dbg(&pdev->dev, "Failed to create PHY\n");
  595. return PTR_ERR(phy);
  596. }
  597. phy_set_drvdata(phy, twl);
  598. phy_provider = devm_of_phy_provider_register(twl->dev,
  599. of_phy_simple_xlate);
  600. if (IS_ERR(phy_provider))
  601. return PTR_ERR(phy_provider);
  602. /* init mutex for workqueue */
  603. mutex_init(&twl->lock);
  604. INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work);
  605. err = twl4030_usb_ldo_init(twl);
  606. if (err) {
  607. dev_err(&pdev->dev, "ldo init failed\n");
  608. return err;
  609. }
  610. usb_add_phy_dev(&twl->phy);
  611. platform_set_drvdata(pdev, twl);
  612. if (device_create_file(&pdev->dev, &dev_attr_vbus))
  613. dev_warn(&pdev->dev, "could not create sysfs file\n");
  614. ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier);
  615. pm_runtime_use_autosuspend(&pdev->dev);
  616. pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
  617. pm_runtime_enable(&pdev->dev);
  618. pm_runtime_get_sync(&pdev->dev);
  619. /* Our job is to use irqs and status from the power module
  620. * to keep the transceiver disabled when nothing's connected.
  621. *
  622. * FIXME we actually shouldn't start enabling it until the
  623. * USB controller drivers have said they're ready, by calling
  624. * set_host() and/or set_peripheral() ... OTG_capable boards
  625. * need both handles, otherwise just one suffices.
  626. */
  627. status = devm_request_threaded_irq(twl->dev, twl->irq, NULL,
  628. twl4030_usb_irq, IRQF_TRIGGER_FALLING |
  629. IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl);
  630. if (status < 0) {
  631. dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
  632. twl->irq, status);
  633. return status;
  634. }
  635. if (pdata)
  636. err = phy_create_lookup(phy, "usb", "musb-hdrc.0");
  637. if (err)
  638. return err;
  639. pm_runtime_mark_last_busy(&pdev->dev);
  640. pm_runtime_put_autosuspend(twl->dev);
  641. dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
  642. return 0;
  643. }
  644. static void twl4030_usb_remove(struct platform_device *pdev)
  645. {
  646. struct twl4030_usb *twl = platform_get_drvdata(pdev);
  647. int val;
  648. usb_remove_phy(&twl->phy);
  649. pm_runtime_get_sync(twl->dev);
  650. cancel_delayed_work_sync(&twl->id_workaround_work);
  651. device_remove_file(twl->dev, &dev_attr_vbus);
  652. /* set transceiver mode to power on defaults */
  653. twl4030_usb_set_mode(twl, -1);
  654. /* idle ulpi before powering off */
  655. if (cable_present(twl->linkstat))
  656. pm_runtime_put_noidle(twl->dev);
  657. pm_runtime_mark_last_busy(twl->dev);
  658. pm_runtime_dont_use_autosuspend(&pdev->dev);
  659. pm_runtime_put_sync(twl->dev);
  660. pm_runtime_disable(twl->dev);
  661. /* autogate 60MHz ULPI clock,
  662. * clear dpll clock request for i2c access,
  663. * disable 32KHz
  664. */
  665. val = twl4030_usb_read(twl, PHY_CLK_CTRL);
  666. if (val >= 0) {
  667. val |= PHY_CLK_CTRL_CLOCKGATING_EN;
  668. val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
  669. twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
  670. }
  671. /* disable complete OTG block */
  672. twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
  673. }
  674. #ifdef CONFIG_OF
  675. static const struct of_device_id twl4030_usb_id_table[] = {
  676. { .compatible = "ti,twl4030-usb" },
  677. {}
  678. };
  679. MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
  680. #endif
  681. static struct platform_driver twl4030_usb_driver = {
  682. .probe = twl4030_usb_probe,
  683. .remove_new = twl4030_usb_remove,
  684. .driver = {
  685. .name = "twl4030_usb",
  686. .pm = &twl4030_usb_pm_ops,
  687. .of_match_table = of_match_ptr(twl4030_usb_id_table),
  688. },
  689. };
  690. static int __init twl4030_usb_init(void)
  691. {
  692. return platform_driver_register(&twl4030_usb_driver);
  693. }
  694. subsys_initcall(twl4030_usb_init);
  695. static void __exit twl4030_usb_exit(void)
  696. {
  697. platform_driver_unregister(&twl4030_usb_driver);
  698. }
  699. module_exit(twl4030_usb_exit);
  700. MODULE_ALIAS("platform:twl4030_usb");
  701. MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
  702. MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
  703. MODULE_LICENSE("GPL");