cros_ec_lpc_mec.h 2.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * LPC variant I/O for Microchip EC
  4. *
  5. * Copyright (C) 2016 Google, Inc
  6. */
  7. #ifndef __CROS_EC_LPC_MEC_H
  8. #define __CROS_EC_LPC_MEC_H
  9. #include <linux/acpi.h>
  10. enum cros_ec_lpc_mec_emi_access_mode {
  11. /* 8-bit access */
  12. ACCESS_TYPE_BYTE = 0x0,
  13. /* 16-bit access */
  14. ACCESS_TYPE_WORD = 0x1,
  15. /* 32-bit access */
  16. ACCESS_TYPE_LONG = 0x2,
  17. /*
  18. * 32-bit access, read or write of MEC_EMI_EC_DATA_B3 causes the
  19. * EC data register to be incremented.
  20. */
  21. ACCESS_TYPE_LONG_AUTO_INCREMENT = 0x3,
  22. };
  23. enum cros_ec_lpc_mec_io_type {
  24. MEC_IO_READ,
  25. MEC_IO_WRITE,
  26. };
  27. /* EMI registers are relative to base */
  28. #define MEC_EMI_HOST_TO_EC(MEC_EMI_BASE) ((MEC_EMI_BASE) + 0)
  29. #define MEC_EMI_EC_TO_HOST(MEC_EMI_BASE) ((MEC_EMI_BASE) + 1)
  30. #define MEC_EMI_EC_ADDRESS_B0(MEC_EMI_BASE) ((MEC_EMI_BASE) + 2)
  31. #define MEC_EMI_EC_ADDRESS_B1(MEC_EMI_BASE) ((MEC_EMI_BASE) + 3)
  32. #define MEC_EMI_EC_DATA_B0(MEC_EMI_BASE) ((MEC_EMI_BASE) + 4)
  33. #define MEC_EMI_EC_DATA_B1(MEC_EMI_BASE) ((MEC_EMI_BASE) + 5)
  34. #define MEC_EMI_EC_DATA_B2(MEC_EMI_BASE) ((MEC_EMI_BASE) + 6)
  35. #define MEC_EMI_EC_DATA_B3(MEC_EMI_BASE) ((MEC_EMI_BASE) + 7)
  36. /**
  37. * cros_ec_lpc_mec_init() - Initialize MEC I/O.
  38. *
  39. * @base: MEC EMI Base address
  40. * @end: MEC EMI End address
  41. */
  42. void cros_ec_lpc_mec_init(unsigned int base, unsigned int end);
  43. /**
  44. * cros_ec_lpc_mec_acpi_mutex() - Find and set ACPI mutex for MEC
  45. *
  46. * @adev: Parent ACPI device
  47. * @pathname: Name of AML mutex
  48. * @return: Negative error code, or zero for success
  49. */
  50. int cros_ec_lpc_mec_acpi_mutex(struct acpi_device *adev, const char *pathname);
  51. /**
  52. * cros_ec_lpc_mec_in_range() - Determine if addresses are in MEC EMI range.
  53. *
  54. * @offset: Address offset
  55. * @length: Number of bytes to check
  56. *
  57. * Return: 1 if in range, 0 if not, and -EINVAL on failure
  58. * such as the mec range not being initialized
  59. */
  60. int cros_ec_lpc_mec_in_range(unsigned int offset, unsigned int length);
  61. /**
  62. * cros_ec_lpc_io_bytes_mec - Read / write bytes to MEC EMI port
  63. *
  64. * @io_type: MEC_IO_READ or MEC_IO_WRITE, depending on request
  65. * @offset: Base read / write address
  66. * @length: Number of bytes to read / write
  67. * @buf: Destination / source buffer
  68. *
  69. * @return: A negative error code on error, or 8-bit checksum of all
  70. * bytes read / written
  71. */
  72. int cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type,
  73. unsigned int offset, unsigned int length, u8 *buf);
  74. #endif /* __CROS_EC_LPC_MEC_H */