r8a779h0-sysc.c 2.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas R-Car V4M System Controller
  4. *
  5. * Copyright (C) 2023 Renesas Electronics Corp
  6. */
  7. #include <linux/kernel.h>
  8. #include <dt-bindings/power/renesas,r8a779h0-sysc.h>
  9. #include "rcar-gen4-sysc.h"
  10. static struct rcar_gen4_sysc_area r8a779h0_areas[] __initdata = {
  11. { "always-on", R8A779H0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
  12. { "c4", R8A779H0_PD_C4, R8A779H0_PD_ALWAYS_ON },
  13. { "a2e0d0", R8A779H0_PD_A2E0D0, R8A779H0_PD_C4, PD_SCU },
  14. { "a1e0d0c0", R8A779H0_PD_A1E0D0C0, R8A779H0_PD_A2E0D0, PD_CPU_NOCR },
  15. { "a1e0d0c1", R8A779H0_PD_A1E0D0C1, R8A779H0_PD_A2E0D0, PD_CPU_NOCR },
  16. { "a1e0d0c2", R8A779H0_PD_A1E0D0C2, R8A779H0_PD_A2E0D0, PD_CPU_NOCR },
  17. { "a1e0d0c3", R8A779H0_PD_A1E0D0C3, R8A779H0_PD_A2E0D0, PD_CPU_NOCR },
  18. { "a3cr0", R8A779H0_PD_A3CR0, R8A779H0_PD_ALWAYS_ON, PD_CPU_NOCR },
  19. { "a3cr1", R8A779H0_PD_A3CR1, R8A779H0_PD_ALWAYS_ON, PD_CPU_NOCR },
  20. { "a3cr2", R8A779H0_PD_A3CR2, R8A779H0_PD_ALWAYS_ON, PD_CPU_NOCR },
  21. { "a33dga", R8A779H0_PD_A33DGA, R8A779H0_PD_C4 },
  22. { "a23dgb", R8A779H0_PD_A23DGB, R8A779H0_PD_A33DGA },
  23. { "a3vip0", R8A779H0_PD_A3VIP0, R8A779H0_PD_C4 },
  24. { "a3vip2", R8A779H0_PD_A3VIP2, R8A779H0_PD_C4 },
  25. { "a3dul", R8A779H0_PD_A3DUL, R8A779H0_PD_C4 },
  26. { "a3isp0", R8A779H0_PD_A3ISP0, R8A779H0_PD_C4 },
  27. { "a2cn0", R8A779H0_PD_A2CN0, R8A779H0_PD_C4 },
  28. { "a1cn0", R8A779H0_PD_A1CN0, R8A779H0_PD_A2CN0 },
  29. { "a1dsp0", R8A779H0_PD_A1DSP0, R8A779H0_PD_A2CN0 },
  30. { "a1dsp1", R8A779H0_PD_A1DSP1, R8A779H0_PD_A2CN0 },
  31. { "a2imp01", R8A779H0_PD_A2IMP01, R8A779H0_PD_C4 },
  32. { "a2psc", R8A779H0_PD_A2PSC, R8A779H0_PD_C4 },
  33. { "a2dma", R8A779H0_PD_A2DMA, R8A779H0_PD_C4 },
  34. { "a2cv0", R8A779H0_PD_A2CV0, R8A779H0_PD_C4 },
  35. { "a2cv1", R8A779H0_PD_A2CV1, R8A779H0_PD_C4 },
  36. { "a2cv2", R8A779H0_PD_A2CV2, R8A779H0_PD_C4 },
  37. { "a2cv3", R8A779H0_PD_A2CV3, R8A779H0_PD_C4 },
  38. { "a3imr0", R8A779H0_PD_A3IMR0, R8A779H0_PD_C4 },
  39. { "a3imr1", R8A779H0_PD_A3IMR1, R8A779H0_PD_C4 },
  40. { "a3imr2", R8A779H0_PD_A3IMR2, R8A779H0_PD_C4 },
  41. { "a3imr3", R8A779H0_PD_A3IMR3, R8A779H0_PD_C4 },
  42. { "a3vc", R8A779H0_PD_A3VC, R8A779H0_PD_C4 },
  43. { "a3pci", R8A779H0_PD_A3PCI, R8A779H0_PD_C4 },
  44. { "a2pciphy", R8A779H0_PD_A2PCIPHY, R8A779H0_PD_A3PCI },
  45. };
  46. const struct rcar_gen4_sysc_info r8a779h0_sysc_info __initconst = {
  47. .areas = r8a779h0_areas,
  48. .num_areas = ARRAY_SIZE(r8a779h0_areas),
  49. };