pwm-lpc32xx.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/err.h>
  7. #include <linux/io.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_address.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/pwm.h>
  14. #include <linux/slab.h>
  15. struct lpc32xx_pwm_chip {
  16. struct clk *clk;
  17. void __iomem *base;
  18. };
  19. #define PWM_ENABLE BIT(31)
  20. #define PWM_PIN_LEVEL BIT(30)
  21. static inline struct lpc32xx_pwm_chip *to_lpc32xx_pwm_chip(struct pwm_chip *chip)
  22. {
  23. return pwmchip_get_drvdata(chip);
  24. }
  25. static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  26. int duty_ns, int period_ns)
  27. {
  28. struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  29. unsigned long long c;
  30. int period_cycles, duty_cycles;
  31. u32 val;
  32. c = clk_get_rate(lpc32xx->clk);
  33. /* The highest acceptable divisor is 256, which is represented by 0 */
  34. period_cycles = div64_u64(c * period_ns,
  35. (unsigned long long)NSEC_PER_SEC * 256);
  36. if (!period_cycles || period_cycles > 256)
  37. return -ERANGE;
  38. if (period_cycles == 256)
  39. period_cycles = 0;
  40. /* Compute 256 x #duty/period value and care for corner cases */
  41. duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
  42. period_ns);
  43. if (!duty_cycles)
  44. duty_cycles = 1;
  45. if (duty_cycles > 255)
  46. duty_cycles = 255;
  47. val = readl(lpc32xx->base);
  48. val &= ~0xFFFF;
  49. val |= (period_cycles << 8) | duty_cycles;
  50. writel(val, lpc32xx->base);
  51. return 0;
  52. }
  53. static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  54. {
  55. struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  56. u32 val;
  57. int ret;
  58. ret = clk_prepare_enable(lpc32xx->clk);
  59. if (ret)
  60. return ret;
  61. val = readl(lpc32xx->base);
  62. val |= PWM_ENABLE;
  63. writel(val, lpc32xx->base);
  64. return 0;
  65. }
  66. static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  67. {
  68. struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  69. u32 val;
  70. val = readl(lpc32xx->base);
  71. val &= ~PWM_ENABLE;
  72. writel(val, lpc32xx->base);
  73. clk_disable_unprepare(lpc32xx->clk);
  74. }
  75. static int lpc32xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  76. const struct pwm_state *state)
  77. {
  78. int err;
  79. if (state->polarity != PWM_POLARITY_NORMAL)
  80. return -EINVAL;
  81. if (!state->enabled) {
  82. if (pwm->state.enabled)
  83. lpc32xx_pwm_disable(chip, pwm);
  84. return 0;
  85. }
  86. err = lpc32xx_pwm_config(chip, pwm, state->duty_cycle, state->period);
  87. if (err)
  88. return err;
  89. if (!pwm->state.enabled)
  90. err = lpc32xx_pwm_enable(chip, pwm);
  91. return err;
  92. }
  93. static const struct pwm_ops lpc32xx_pwm_ops = {
  94. .apply = lpc32xx_pwm_apply,
  95. };
  96. static int lpc32xx_pwm_probe(struct platform_device *pdev)
  97. {
  98. struct pwm_chip *chip;
  99. struct lpc32xx_pwm_chip *lpc32xx;
  100. int ret;
  101. u32 val;
  102. chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*lpc32xx));
  103. if (IS_ERR(chip))
  104. return PTR_ERR(chip);
  105. lpc32xx = to_lpc32xx_pwm_chip(chip);
  106. lpc32xx->base = devm_platform_ioremap_resource(pdev, 0);
  107. if (IS_ERR(lpc32xx->base))
  108. return PTR_ERR(lpc32xx->base);
  109. lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
  110. if (IS_ERR(lpc32xx->clk))
  111. return PTR_ERR(lpc32xx->clk);
  112. chip->ops = &lpc32xx_pwm_ops;
  113. /* If PWM is disabled, configure the output to the default value */
  114. val = readl(lpc32xx->base);
  115. val &= ~PWM_PIN_LEVEL;
  116. writel(val, lpc32xx->base);
  117. ret = devm_pwmchip_add(&pdev->dev, chip);
  118. if (ret < 0) {
  119. dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
  120. return ret;
  121. }
  122. return 0;
  123. }
  124. static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
  125. { .compatible = "nxp,lpc3220-pwm", },
  126. { /* sentinel */ }
  127. };
  128. MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);
  129. static struct platform_driver lpc32xx_pwm_driver = {
  130. .driver = {
  131. .name = "lpc32xx-pwm",
  132. .of_match_table = lpc32xx_pwm_dt_ids,
  133. },
  134. .probe = lpc32xx_pwm_probe,
  135. };
  136. module_platform_driver(lpc32xx_pwm_driver);
  137. MODULE_ALIAS("platform:lpc32xx-pwm");
  138. MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
  139. MODULE_DESCRIPTION("LPC32XX PWM Driver");
  140. MODULE_LICENSE("GPL v2");