qcom_smd-regulator.c 56 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015, Sony Mobile Communications AB.
  4. * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/of.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/regulator/driver.h>
  10. #include <linux/regulator/of_regulator.h>
  11. #include <linux/soc/qcom/smd-rpm.h>
  12. static struct qcom_smd_rpm *smd_vreg_rpm;
  13. struct qcom_rpm_reg {
  14. struct device *dev;
  15. u32 type;
  16. u32 id;
  17. struct regulator_desc desc;
  18. int is_enabled;
  19. int uV;
  20. u32 load;
  21. unsigned int enabled_updated:1;
  22. unsigned int uv_updated:1;
  23. unsigned int load_updated:1;
  24. };
  25. struct rpm_regulator_req {
  26. __le32 key;
  27. __le32 nbytes;
  28. __le32 value;
  29. };
  30. #define RPM_KEY_SWEN 0x6e657773 /* "swen" */
  31. #define RPM_KEY_UV 0x00007675 /* "uv" */
  32. #define RPM_KEY_MA 0x0000616d /* "ma" */
  33. static int rpm_reg_write_active(struct qcom_rpm_reg *vreg)
  34. {
  35. struct rpm_regulator_req req[3];
  36. int reqlen = 0;
  37. int ret;
  38. if (vreg->enabled_updated) {
  39. req[reqlen].key = cpu_to_le32(RPM_KEY_SWEN);
  40. req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
  41. req[reqlen].value = cpu_to_le32(vreg->is_enabled);
  42. reqlen++;
  43. }
  44. if (vreg->uv_updated && vreg->is_enabled) {
  45. req[reqlen].key = cpu_to_le32(RPM_KEY_UV);
  46. req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
  47. req[reqlen].value = cpu_to_le32(vreg->uV);
  48. reqlen++;
  49. }
  50. if (vreg->load_updated && vreg->is_enabled) {
  51. req[reqlen].key = cpu_to_le32(RPM_KEY_MA);
  52. req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
  53. req[reqlen].value = cpu_to_le32(vreg->load / 1000);
  54. reqlen++;
  55. }
  56. if (!reqlen)
  57. return 0;
  58. ret = qcom_rpm_smd_write(smd_vreg_rpm, QCOM_SMD_RPM_ACTIVE_STATE,
  59. vreg->type, vreg->id,
  60. req, sizeof(req[0]) * reqlen);
  61. if (!ret) {
  62. vreg->enabled_updated = 0;
  63. vreg->uv_updated = 0;
  64. vreg->load_updated = 0;
  65. }
  66. return ret;
  67. }
  68. static int rpm_reg_enable(struct regulator_dev *rdev)
  69. {
  70. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  71. int ret;
  72. vreg->is_enabled = 1;
  73. vreg->enabled_updated = 1;
  74. ret = rpm_reg_write_active(vreg);
  75. if (ret)
  76. vreg->is_enabled = 0;
  77. return ret;
  78. }
  79. static int rpm_reg_is_enabled(struct regulator_dev *rdev)
  80. {
  81. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  82. return vreg->is_enabled;
  83. }
  84. static int rpm_reg_disable(struct regulator_dev *rdev)
  85. {
  86. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  87. int ret;
  88. vreg->is_enabled = 0;
  89. vreg->enabled_updated = 1;
  90. ret = rpm_reg_write_active(vreg);
  91. if (ret)
  92. vreg->is_enabled = 1;
  93. return ret;
  94. }
  95. static int rpm_reg_get_voltage(struct regulator_dev *rdev)
  96. {
  97. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  98. return vreg->uV;
  99. }
  100. static int rpm_reg_set_voltage(struct regulator_dev *rdev,
  101. int min_uV,
  102. int max_uV,
  103. unsigned *selector)
  104. {
  105. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  106. int ret;
  107. int old_uV = vreg->uV;
  108. vreg->uV = min_uV;
  109. vreg->uv_updated = 1;
  110. ret = rpm_reg_write_active(vreg);
  111. if (ret)
  112. vreg->uV = old_uV;
  113. return ret;
  114. }
  115. static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA)
  116. {
  117. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  118. u32 old_load = vreg->load;
  119. int ret;
  120. vreg->load = load_uA;
  121. vreg->load_updated = 1;
  122. ret = rpm_reg_write_active(vreg);
  123. if (ret)
  124. vreg->load = old_load;
  125. return ret;
  126. }
  127. static const struct regulator_ops rpm_smps_ldo_ops = {
  128. .enable = rpm_reg_enable,
  129. .disable = rpm_reg_disable,
  130. .is_enabled = rpm_reg_is_enabled,
  131. .list_voltage = regulator_list_voltage_linear_range,
  132. .get_voltage = rpm_reg_get_voltage,
  133. .set_voltage = rpm_reg_set_voltage,
  134. .set_load = rpm_reg_set_load,
  135. };
  136. static const struct regulator_ops rpm_smps_ldo_ops_fixed = {
  137. .enable = rpm_reg_enable,
  138. .disable = rpm_reg_disable,
  139. .is_enabled = rpm_reg_is_enabled,
  140. .get_voltage = rpm_reg_get_voltage,
  141. .set_voltage = rpm_reg_set_voltage,
  142. .set_load = rpm_reg_set_load,
  143. };
  144. static const struct regulator_ops rpm_switch_ops = {
  145. .enable = rpm_reg_enable,
  146. .disable = rpm_reg_disable,
  147. .is_enabled = rpm_reg_is_enabled,
  148. };
  149. static const struct regulator_ops rpm_bob_ops = {
  150. .enable = rpm_reg_enable,
  151. .disable = rpm_reg_disable,
  152. .is_enabled = rpm_reg_is_enabled,
  153. .get_voltage = rpm_reg_get_voltage,
  154. .set_voltage = rpm_reg_set_voltage,
  155. };
  156. static const struct regulator_ops rpm_mp5496_ops = {
  157. .enable = rpm_reg_enable,
  158. .disable = rpm_reg_disable,
  159. .is_enabled = rpm_reg_is_enabled,
  160. .list_voltage = regulator_list_voltage_linear_range,
  161. .get_voltage = rpm_reg_get_voltage,
  162. .set_voltage = rpm_reg_set_voltage,
  163. };
  164. static const struct regulator_desc pma8084_hfsmps = {
  165. .linear_ranges = (struct linear_range[]) {
  166. REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
  167. REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
  168. },
  169. .n_linear_ranges = 2,
  170. .n_voltages = 159,
  171. .ops = &rpm_smps_ldo_ops,
  172. };
  173. static const struct regulator_desc pma8084_ftsmps = {
  174. .linear_ranges = (struct linear_range[]) {
  175. REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
  176. REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
  177. },
  178. .n_linear_ranges = 2,
  179. .n_voltages = 262,
  180. .ops = &rpm_smps_ldo_ops,
  181. };
  182. static const struct regulator_desc pma8084_pldo = {
  183. .linear_ranges = (struct linear_range[]) {
  184. REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
  185. REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
  186. REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
  187. },
  188. .n_linear_ranges = 3,
  189. .n_voltages = 164,
  190. .ops = &rpm_smps_ldo_ops,
  191. };
  192. static const struct regulator_desc pma8084_nldo = {
  193. .linear_ranges = (struct linear_range[]) {
  194. REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
  195. },
  196. .n_linear_ranges = 1,
  197. .n_voltages = 64,
  198. .ops = &rpm_smps_ldo_ops,
  199. };
  200. static const struct regulator_desc pma8084_switch = {
  201. .ops = &rpm_switch_ops,
  202. };
  203. static const struct regulator_desc pm8226_hfsmps = {
  204. .linear_ranges = (struct linear_range[]) {
  205. REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
  206. REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000),
  207. },
  208. .n_linear_ranges = 2,
  209. .n_voltages = 159,
  210. .ops = &rpm_smps_ldo_ops,
  211. };
  212. static const struct regulator_desc pm8226_ftsmps = {
  213. .linear_ranges = (struct linear_range[]) {
  214. REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
  215. REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
  216. },
  217. .n_linear_ranges = 2,
  218. .n_voltages = 262,
  219. .ops = &rpm_smps_ldo_ops,
  220. };
  221. static const struct regulator_desc pm8226_pldo = {
  222. .linear_ranges = (struct linear_range[]) {
  223. REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
  224. REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
  225. REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
  226. },
  227. .n_linear_ranges = 3,
  228. .n_voltages = 164,
  229. .ops = &rpm_smps_ldo_ops,
  230. };
  231. static const struct regulator_desc pm8226_nldo = {
  232. .linear_ranges = (struct linear_range[]) {
  233. REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
  234. },
  235. .n_linear_ranges = 1,
  236. .n_voltages = 64,
  237. .ops = &rpm_smps_ldo_ops,
  238. };
  239. static const struct regulator_desc pm8226_switch = {
  240. .ops = &rpm_switch_ops,
  241. };
  242. static const struct regulator_desc pm8x41_hfsmps = {
  243. .linear_ranges = (struct linear_range[]) {
  244. REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
  245. REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000),
  246. },
  247. .n_linear_ranges = 2,
  248. .n_voltages = 159,
  249. .ops = &rpm_smps_ldo_ops,
  250. };
  251. static const struct regulator_desc pm8841_ftsmps = {
  252. .linear_ranges = (struct linear_range[]) {
  253. REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
  254. REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
  255. },
  256. .n_linear_ranges = 2,
  257. .n_voltages = 262,
  258. .ops = &rpm_smps_ldo_ops,
  259. };
  260. static const struct regulator_desc pm8941_boost = {
  261. .linear_ranges = (struct linear_range[]) {
  262. REGULATOR_LINEAR_RANGE(4000000, 0, 30, 50000),
  263. },
  264. .n_linear_ranges = 1,
  265. .n_voltages = 31,
  266. .ops = &rpm_smps_ldo_ops,
  267. };
  268. static const struct regulator_desc pm8941_pldo = {
  269. .linear_ranges = (struct linear_range[]) {
  270. REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
  271. REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
  272. REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
  273. },
  274. .n_linear_ranges = 3,
  275. .n_voltages = 164,
  276. .ops = &rpm_smps_ldo_ops,
  277. };
  278. static const struct regulator_desc pm8941_nldo = {
  279. .linear_ranges = (struct linear_range[]) {
  280. REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
  281. },
  282. .n_linear_ranges = 1,
  283. .n_voltages = 64,
  284. .ops = &rpm_smps_ldo_ops,
  285. };
  286. static const struct regulator_desc pm8941_lnldo = {
  287. .fixed_uV = 1740000,
  288. .n_voltages = 1,
  289. .ops = &rpm_smps_ldo_ops_fixed,
  290. };
  291. static const struct regulator_desc pm8941_switch = {
  292. .ops = &rpm_switch_ops,
  293. };
  294. static const struct regulator_desc pm8916_pldo = {
  295. .linear_ranges = (struct linear_range[]) {
  296. REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500),
  297. },
  298. .n_linear_ranges = 1,
  299. .n_voltages = 128,
  300. .ops = &rpm_smps_ldo_ops,
  301. };
  302. static const struct regulator_desc pm8916_nldo = {
  303. .linear_ranges = (struct linear_range[]) {
  304. REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
  305. },
  306. .n_linear_ranges = 1,
  307. .n_voltages = 94,
  308. .ops = &rpm_smps_ldo_ops,
  309. };
  310. static const struct regulator_desc pm8916_buck_lvo_smps = {
  311. .linear_ranges = (struct linear_range[]) {
  312. REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
  313. REGULATOR_LINEAR_RANGE(750000, 96, 127, 25000),
  314. },
  315. .n_linear_ranges = 2,
  316. .n_voltages = 128,
  317. .ops = &rpm_smps_ldo_ops,
  318. };
  319. static const struct regulator_desc pm8916_buck_hvo_smps = {
  320. .linear_ranges = (struct linear_range[]) {
  321. REGULATOR_LINEAR_RANGE(1550000, 0, 31, 25000),
  322. },
  323. .n_linear_ranges = 1,
  324. .n_voltages = 32,
  325. .ops = &rpm_smps_ldo_ops,
  326. };
  327. static const struct regulator_desc pm8950_hfsmps = {
  328. .linear_ranges = (struct linear_range[]) {
  329. REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
  330. REGULATOR_LINEAR_RANGE(1550000, 96, 127, 25000),
  331. },
  332. .n_linear_ranges = 2,
  333. .n_voltages = 128,
  334. .ops = &rpm_smps_ldo_ops,
  335. };
  336. static const struct regulator_desc pm8950_ftsmps2p5 = {
  337. .linear_ranges = (struct linear_range[]) {
  338. REGULATOR_LINEAR_RANGE(80000, 0, 255, 5000),
  339. REGULATOR_LINEAR_RANGE(160000, 256, 460, 10000),
  340. },
  341. .n_linear_ranges = 2,
  342. .n_voltages = 461,
  343. .ops = &rpm_smps_ldo_ops,
  344. };
  345. static const struct regulator_desc pm8950_ult_nldo = {
  346. .linear_ranges = (struct linear_range[]) {
  347. REGULATOR_LINEAR_RANGE(375000, 0, 202, 12500),
  348. },
  349. .n_linear_ranges = 1,
  350. .n_voltages = 203,
  351. .ops = &rpm_smps_ldo_ops,
  352. };
  353. static const struct regulator_desc pm8950_ult_pldo = {
  354. .linear_ranges = (struct linear_range[]) {
  355. REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500),
  356. },
  357. .n_linear_ranges = 1,
  358. .n_voltages = 128,
  359. .ops = &rpm_smps_ldo_ops,
  360. };
  361. static const struct regulator_desc pm8950_pldo_lv = {
  362. .linear_ranges = (struct linear_range[]) {
  363. REGULATOR_LINEAR_RANGE(1500000, 0, 16, 25000),
  364. },
  365. .n_linear_ranges = 1,
  366. .n_voltages = 17,
  367. .ops = &rpm_smps_ldo_ops,
  368. };
  369. static const struct regulator_desc pm8950_pldo = {
  370. .linear_ranges = (struct linear_range[]) {
  371. REGULATOR_LINEAR_RANGE(975000, 0, 164, 12500),
  372. },
  373. .n_linear_ranges = 1,
  374. .n_voltages = 165,
  375. .ops = &rpm_smps_ldo_ops,
  376. };
  377. static const struct regulator_desc pm8953_lnldo = {
  378. .linear_ranges = (struct linear_range[]) {
  379. REGULATOR_LINEAR_RANGE(690000, 0, 7, 60000),
  380. REGULATOR_LINEAR_RANGE(1380000, 8, 15, 120000),
  381. },
  382. .n_linear_ranges = 2,
  383. .n_voltages = 16,
  384. .ops = &rpm_smps_ldo_ops,
  385. };
  386. static const struct regulator_desc pm8953_ult_nldo = {
  387. .linear_ranges = (struct linear_range[]) {
  388. REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
  389. },
  390. .n_linear_ranges = 1,
  391. .n_voltages = 94,
  392. .ops = &rpm_smps_ldo_ops,
  393. };
  394. static const struct regulator_desc pm8994_hfsmps = {
  395. .linear_ranges = (struct linear_range[]) {
  396. REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
  397. REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
  398. },
  399. .n_linear_ranges = 2,
  400. .n_voltages = 159,
  401. .ops = &rpm_smps_ldo_ops,
  402. };
  403. static const struct regulator_desc pm8994_ftsmps = {
  404. .linear_ranges = (struct linear_range[]) {
  405. REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000),
  406. REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000),
  407. },
  408. .n_linear_ranges = 2,
  409. .n_voltages = 350,
  410. .ops = &rpm_smps_ldo_ops,
  411. };
  412. static const struct regulator_desc pm8994_nldo = {
  413. .linear_ranges = (struct linear_range[]) {
  414. REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
  415. },
  416. .n_linear_ranges = 1,
  417. .n_voltages = 64,
  418. .ops = &rpm_smps_ldo_ops,
  419. };
  420. static const struct regulator_desc pm8994_pldo = {
  421. .linear_ranges = (struct linear_range[]) {
  422. REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
  423. REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
  424. REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
  425. },
  426. .n_linear_ranges = 3,
  427. .n_voltages = 164,
  428. .ops = &rpm_smps_ldo_ops,
  429. };
  430. static const struct regulator_desc pm8994_switch = {
  431. .ops = &rpm_switch_ops,
  432. };
  433. static const struct regulator_desc pm8994_lnldo = {
  434. .fixed_uV = 1740000,
  435. .n_voltages = 1,
  436. .ops = &rpm_smps_ldo_ops_fixed,
  437. };
  438. static const struct regulator_desc pmi8994_ftsmps = {
  439. .linear_ranges = (struct linear_range[]) {
  440. REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000),
  441. REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000),
  442. },
  443. .n_linear_ranges = 2,
  444. .n_voltages = 350,
  445. .ops = &rpm_smps_ldo_ops,
  446. };
  447. static const struct regulator_desc pmi8994_hfsmps = {
  448. .linear_ranges = (struct linear_range[]) {
  449. REGULATOR_LINEAR_RANGE(350000, 0, 80, 12500),
  450. REGULATOR_LINEAR_RANGE(700000, 81, 141, 25000),
  451. },
  452. .n_linear_ranges = 2,
  453. .n_voltages = 142,
  454. .ops = &rpm_smps_ldo_ops,
  455. };
  456. static const struct regulator_desc pmi8994_bby = {
  457. .linear_ranges = (struct linear_range[]) {
  458. REGULATOR_LINEAR_RANGE(3000000, 0, 44, 50000),
  459. },
  460. .n_linear_ranges = 1,
  461. .n_voltages = 45,
  462. .ops = &rpm_bob_ops,
  463. };
  464. static const struct regulator_desc pm8998_ftsmps = {
  465. .linear_ranges = (struct linear_range[]) {
  466. REGULATOR_LINEAR_RANGE(320000, 0, 258, 4000),
  467. },
  468. .n_linear_ranges = 1,
  469. .n_voltages = 259,
  470. .ops = &rpm_smps_ldo_ops,
  471. };
  472. static const struct regulator_desc pm8998_hfsmps = {
  473. .linear_ranges = (struct linear_range[]) {
  474. REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
  475. },
  476. .n_linear_ranges = 1,
  477. .n_voltages = 216,
  478. .ops = &rpm_smps_ldo_ops,
  479. };
  480. static const struct regulator_desc pm8998_nldo = {
  481. .linear_ranges = (struct linear_range[]) {
  482. REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
  483. },
  484. .n_linear_ranges = 1,
  485. .n_voltages = 128,
  486. .ops = &rpm_smps_ldo_ops,
  487. };
  488. static const struct regulator_desc pm8998_pldo = {
  489. .linear_ranges = (struct linear_range[]) {
  490. REGULATOR_LINEAR_RANGE(1664000, 0, 255, 8000),
  491. },
  492. .n_linear_ranges = 1,
  493. .n_voltages = 256,
  494. .ops = &rpm_smps_ldo_ops,
  495. };
  496. static const struct regulator_desc pm8998_pldo_lv = {
  497. .linear_ranges = (struct linear_range[]) {
  498. REGULATOR_LINEAR_RANGE(1256000, 0, 127, 8000),
  499. },
  500. .n_linear_ranges = 1,
  501. .n_voltages = 128,
  502. .ops = &rpm_smps_ldo_ops,
  503. };
  504. static const struct regulator_desc pm8998_switch = {
  505. .ops = &rpm_switch_ops,
  506. };
  507. static const struct regulator_desc pmi8998_bob = {
  508. .linear_ranges = (struct linear_range[]) {
  509. REGULATOR_LINEAR_RANGE(1824000, 0, 83, 32000),
  510. },
  511. .n_linear_ranges = 1,
  512. .n_voltages = 84,
  513. .ops = &rpm_bob_ops,
  514. };
  515. static const struct regulator_desc pm660_ftsmps = {
  516. .linear_ranges = (struct linear_range[]) {
  517. REGULATOR_LINEAR_RANGE(355000, 0, 199, 5000),
  518. },
  519. .n_linear_ranges = 1,
  520. .n_voltages = 200,
  521. .ops = &rpm_smps_ldo_ops,
  522. };
  523. static const struct regulator_desc pm660_hfsmps = {
  524. .linear_ranges = (struct linear_range[]) {
  525. REGULATOR_LINEAR_RANGE(320000, 0, 216, 8000),
  526. },
  527. .n_linear_ranges = 1,
  528. .n_voltages = 217,
  529. .ops = &rpm_smps_ldo_ops,
  530. };
  531. static const struct regulator_desc pm660_ht_nldo = {
  532. .linear_ranges = (struct linear_range[]) {
  533. REGULATOR_LINEAR_RANGE(312000, 0, 124, 8000),
  534. },
  535. .n_linear_ranges = 1,
  536. .n_voltages = 125,
  537. .ops = &rpm_smps_ldo_ops,
  538. };
  539. static const struct regulator_desc pm660_ht_lvpldo = {
  540. .linear_ranges = (struct linear_range[]) {
  541. REGULATOR_LINEAR_RANGE(1504000, 0, 62, 8000),
  542. },
  543. .n_linear_ranges = 1,
  544. .n_voltages = 63,
  545. .ops = &rpm_smps_ldo_ops,
  546. };
  547. static const struct regulator_desc pm660_nldo660 = {
  548. .linear_ranges = (struct linear_range[]) {
  549. REGULATOR_LINEAR_RANGE(320000, 0, 123, 8000),
  550. },
  551. .n_linear_ranges = 1,
  552. .n_voltages = 124,
  553. .ops = &rpm_smps_ldo_ops,
  554. };
  555. static const struct regulator_desc pm660_pldo660 = {
  556. .linear_ranges = (struct linear_range[]) {
  557. REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000),
  558. },
  559. .n_linear_ranges = 1,
  560. .n_voltages = 256,
  561. .ops = &rpm_smps_ldo_ops,
  562. };
  563. static const struct regulator_desc pm660l_bob = {
  564. .linear_ranges = (struct linear_range[]) {
  565. REGULATOR_LINEAR_RANGE(1800000, 0, 84, 32000),
  566. },
  567. .n_linear_ranges = 1,
  568. .n_voltages = 85,
  569. .ops = &rpm_bob_ops,
  570. };
  571. static const struct regulator_desc pm6125_ftsmps = {
  572. .linear_ranges = (struct linear_range[]) {
  573. REGULATOR_LINEAR_RANGE(300000, 0, 268, 4000),
  574. },
  575. .n_linear_ranges = 1,
  576. .n_voltages = 269,
  577. .ops = &rpm_smps_ldo_ops,
  578. };
  579. static const struct regulator_desc pmic5_ftsmps520 = {
  580. .linear_ranges = (struct linear_range[]) {
  581. REGULATOR_LINEAR_RANGE(300000, 0, 263, 4000),
  582. },
  583. .n_linear_ranges = 1,
  584. .n_voltages = 264,
  585. .ops = &rpm_smps_ldo_ops,
  586. };
  587. static const struct regulator_desc pmic5_hfsmps515 = {
  588. .linear_ranges = (struct linear_range[]) {
  589. REGULATOR_LINEAR_RANGE(320000, 0, 235, 16000),
  590. },
  591. .n_linear_ranges = 1,
  592. .n_voltages = 236,
  593. .ops = &rpm_smps_ldo_ops,
  594. };
  595. static const struct regulator_desc pms405_hfsmps3 = {
  596. .linear_ranges = (struct linear_range[]) {
  597. REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
  598. },
  599. .n_linear_ranges = 1,
  600. .n_voltages = 216,
  601. .ops = &rpm_smps_ldo_ops,
  602. };
  603. static const struct regulator_desc pms405_nldo300 = {
  604. .linear_ranges = (struct linear_range[]) {
  605. REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
  606. },
  607. .n_linear_ranges = 1,
  608. .n_voltages = 128,
  609. .ops = &rpm_smps_ldo_ops,
  610. };
  611. static const struct regulator_desc pms405_nldo1200 = {
  612. .linear_ranges = (struct linear_range[]) {
  613. REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
  614. },
  615. .n_linear_ranges = 1,
  616. .n_voltages = 128,
  617. .ops = &rpm_smps_ldo_ops,
  618. };
  619. static const struct regulator_desc pms405_pldo50 = {
  620. .linear_ranges = (struct linear_range[]) {
  621. REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
  622. },
  623. .n_linear_ranges = 1,
  624. .n_voltages = 129,
  625. .ops = &rpm_smps_ldo_ops,
  626. };
  627. static const struct regulator_desc pms405_pldo150 = {
  628. .linear_ranges = (struct linear_range[]) {
  629. REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
  630. },
  631. .n_linear_ranges = 1,
  632. .n_voltages = 129,
  633. .ops = &rpm_smps_ldo_ops,
  634. };
  635. static const struct regulator_desc pms405_pldo600 = {
  636. .linear_ranges = (struct linear_range[]) {
  637. REGULATOR_LINEAR_RANGE(1256000, 0, 98, 8000),
  638. },
  639. .n_linear_ranges = 1,
  640. .n_voltages = 99,
  641. .ops = &rpm_smps_ldo_ops,
  642. };
  643. static const struct regulator_desc mp5496_smps = {
  644. .linear_ranges = (struct linear_range[]) {
  645. REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500),
  646. },
  647. .n_linear_ranges = 1,
  648. .n_voltages = 128,
  649. .ops = &rpm_mp5496_ops,
  650. };
  651. static const struct regulator_desc mp5496_ldoa2 = {
  652. .linear_ranges = (struct linear_range[]) {
  653. REGULATOR_LINEAR_RANGE(800000, 0, 127, 25000),
  654. },
  655. .n_linear_ranges = 1,
  656. .n_voltages = 128,
  657. .ops = &rpm_mp5496_ops,
  658. };
  659. static const struct regulator_desc pm2250_lvftsmps = {
  660. .linear_ranges = (struct linear_range[]) {
  661. REGULATOR_LINEAR_RANGE(320000, 0, 269, 4000),
  662. },
  663. .n_linear_ranges = 1,
  664. .n_voltages = 270,
  665. .ops = &rpm_smps_ldo_ops,
  666. };
  667. static const struct regulator_desc pm2250_ftsmps = {
  668. .linear_ranges = (struct linear_range[]) {
  669. REGULATOR_LINEAR_RANGE(640000, 0, 269, 8000),
  670. },
  671. .n_linear_ranges = 1,
  672. .n_voltages = 270,
  673. .ops = &rpm_smps_ldo_ops,
  674. };
  675. struct rpm_regulator_data {
  676. const char *name;
  677. u32 type;
  678. u32 id;
  679. const struct regulator_desc *desc;
  680. const char *supply;
  681. };
  682. static const struct rpm_regulator_data rpm_mp5496_regulators[] = {
  683. { "s1", QCOM_SMD_RPM_SMPA, 1, &mp5496_smps, "s1" },
  684. { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smps, "s2" },
  685. { "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2" },
  686. { "l5", QCOM_SMD_RPM_LDOA, 5, &mp5496_ldoa2, "l5" },
  687. {}
  688. };
  689. static const struct rpm_regulator_data rpm_pm2250_regulators[] = {
  690. { "s1", QCOM_SMD_RPM_SMPA, 1, &pm2250_lvftsmps, "vdd_s1" },
  691. { "s2", QCOM_SMD_RPM_SMPA, 2, &pm2250_lvftsmps, "vdd_s2" },
  692. { "s3", QCOM_SMD_RPM_SMPA, 3, &pm2250_lvftsmps, "vdd_s3" },
  693. { "s4", QCOM_SMD_RPM_SMPA, 4, &pm2250_ftsmps, "vdd_s4" },
  694. { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
  695. { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
  696. { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
  697. { "l4", QCOM_SMD_RPM_LDOA, 4, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
  698. { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
  699. { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
  700. { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
  701. { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
  702. { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
  703. { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
  704. { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
  705. { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
  706. { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
  707. { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
  708. { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
  709. { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
  710. { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
  711. { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
  712. { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
  713. { "l20", QCOM_SMD_RPM_LDOA, 20, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
  714. { "l21", QCOM_SMD_RPM_LDOA, 21, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
  715. { "l22", QCOM_SMD_RPM_LDOA, 22, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
  716. {}
  717. };
  718. static const struct rpm_regulator_data rpm_pm6125_regulators[] = {
  719. { "s1", QCOM_SMD_RPM_SMPA, 1, &pm6125_ftsmps, "vdd_s1" },
  720. { "s2", QCOM_SMD_RPM_SMPA, 2, &pm6125_ftsmps, "vdd_s2" },
  721. { "s3", QCOM_SMD_RPM_SMPA, 3, &pm6125_ftsmps, "vdd_s3" },
  722. { "s4", QCOM_SMD_RPM_SMPA, 4, &pm6125_ftsmps, "vdd_s4" },
  723. { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" },
  724. { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_hfsmps, "vdd_s6" },
  725. { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_hfsmps, "vdd_s7" },
  726. { "s8", QCOM_SMD_RPM_SMPA, 8, &pm6125_ftsmps, "vdd_s8" },
  727. { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
  728. { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_nldo660, "vdd_l2_l3_l4" },
  729. { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l2_l3_l4" },
  730. { "l4", QCOM_SMD_RPM_LDOA, 4, &pm660_nldo660, "vdd_l2_l3_l4" },
  731. { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
  732. { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_nldo660, "vdd_l6_l8" },
  733. { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
  734. { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_nldo660, "vdd_l6_l8" },
  735. { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_ht_lvpldo, "vdd_l9_l11" },
  736. { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_ht_lvpldo, "vdd_l10_l13_l14" },
  737. { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_ht_lvpldo, "vdd_l9_l11" },
  738. { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l12_l16" },
  739. { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l10_l13_l14" },
  740. { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l10_l13_l14" },
  741. { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
  742. { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_ht_lvpldo, "vdd_l12_l16" },
  743. { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
  744. { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
  745. { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
  746. { "l20", QCOM_SMD_RPM_LDOA, 20, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
  747. { "l21", QCOM_SMD_RPM_LDOA, 21, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
  748. { "l22", QCOM_SMD_RPM_LDOA, 22, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
  749. { "l23", QCOM_SMD_RPM_LDOA, 23, &pm660_pldo660, "vdd_l23_l24" },
  750. { "l24", QCOM_SMD_RPM_LDOA, 24, &pm660_pldo660, "vdd_l23_l24" },
  751. { }
  752. };
  753. static const struct rpm_regulator_data rpm_pm660_regulators[] = {
  754. { "s1", QCOM_SMD_RPM_SMPA, 1, &pm660_ftsmps, "vdd_s1" },
  755. { "s2", QCOM_SMD_RPM_SMPA, 2, &pm660_ftsmps, "vdd_s2" },
  756. { "s3", QCOM_SMD_RPM_SMPA, 3, &pm660_ftsmps, "vdd_s3" },
  757. { "s4", QCOM_SMD_RPM_SMPA, 4, &pm660_hfsmps, "vdd_s4" },
  758. { "s5", QCOM_SMD_RPM_SMPA, 5, &pm660_hfsmps, "vdd_s5" },
  759. { "s6", QCOM_SMD_RPM_SMPA, 6, &pm660_hfsmps, "vdd_s6" },
  760. { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l6_l7" },
  761. { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_ht_nldo, "vdd_l2_l3" },
  762. { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l2_l3" },
  763. /* l4 is unaccessible on PM660 */
  764. { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_ht_nldo, "vdd_l5" },
  765. { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_ht_nldo, "vdd_l1_l6_l7" },
  766. { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_ht_nldo, "vdd_l1_l6_l7" },
  767. { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
  768. { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
  769. { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
  770. { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
  771. { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
  772. { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
  773. { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
  774. { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
  775. { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
  776. { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
  777. { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
  778. { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
  779. { }
  780. };
  781. static const struct rpm_regulator_data rpm_pm660l_regulators[] = {
  782. { "s1", QCOM_SMD_RPM_SMPB, 1, &pm660_ftsmps, "vdd_s1" },
  783. { "s2", QCOM_SMD_RPM_SMPB, 2, &pm660_ftsmps, "vdd_s2" },
  784. { "s3", QCOM_SMD_RPM_RWCX, 0, &pm660_ftsmps, "vdd_s3_s4" },
  785. { "s5", QCOM_SMD_RPM_RWMX, 0, &pm660_ftsmps, "vdd_s5" },
  786. { "l1", QCOM_SMD_RPM_LDOB, 1, &pm660_nldo660, "vdd_l1_l9_l10" },
  787. { "l2", QCOM_SMD_RPM_LDOB, 2, &pm660_pldo660, "vdd_l2" },
  788. { "l3", QCOM_SMD_RPM_LDOB, 3, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
  789. { "l4", QCOM_SMD_RPM_LDOB, 4, &pm660_pldo660, "vdd_l4_l6" },
  790. { "l5", QCOM_SMD_RPM_LDOB, 5, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
  791. { "l6", QCOM_SMD_RPM_LDOB, 6, &pm660_pldo660, "vdd_l4_l6" },
  792. { "l7", QCOM_SMD_RPM_LDOB, 7, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
  793. { "l8", QCOM_SMD_RPM_LDOB, 8, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
  794. { "l9", QCOM_SMD_RPM_RWLC, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" },
  795. { "l10", QCOM_SMD_RPM_RWLM, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" },
  796. { "bob", QCOM_SMD_RPM_BOBB, 1, &pm660l_bob, "vdd_bob", },
  797. { }
  798. };
  799. static const struct rpm_regulator_data rpm_pm8226_regulators[] = {
  800. { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8226_hfsmps, "vdd_s1" },
  801. { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8226_ftsmps, "vdd_s2" },
  802. { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8226_hfsmps, "vdd_s3" },
  803. { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8226_hfsmps, "vdd_s4" },
  804. { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8226_hfsmps, "vdd_s5" },
  805. { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
  806. { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
  807. { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8226_nldo, "vdd_l3_l24_l26" },
  808. { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
  809. { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
  810. { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
  811. { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
  812. { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
  813. { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
  814. { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8226_pldo, "vdd_l10_l11_l13" },
  815. { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8226_pldo, "vdd_l10_l11_l13" },
  816. { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8226_pldo, "vdd_l12_l14" },
  817. { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8226_pldo, "vdd_l10_l11_l13" },
  818. { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8226_pldo, "vdd_l12_l14" },
  819. { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
  820. { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
  821. { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
  822. { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
  823. { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
  824. { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
  825. { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
  826. { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
  827. { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
  828. { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8226_nldo, "vdd_l3_l24_l26" },
  829. { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8226_pldo, "vdd_l25" },
  830. { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8226_nldo, "vdd_l3_l24_l26" },
  831. { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
  832. { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
  833. { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8226_switch, "vdd_lvs1" },
  834. {}
  835. };
  836. static const struct rpm_regulator_data rpm_pm8841_regulators[] = {
  837. { "s1", QCOM_SMD_RPM_SMPB, 1, &pm8x41_hfsmps, "vdd_s1" },
  838. { "s2", QCOM_SMD_RPM_SMPB, 2, &pm8841_ftsmps, "vdd_s2" },
  839. { "s3", QCOM_SMD_RPM_SMPB, 3, &pm8x41_hfsmps, "vdd_s3" },
  840. { "s4", QCOM_SMD_RPM_SMPB, 4, &pm8841_ftsmps, "vdd_s4" },
  841. { "s5", QCOM_SMD_RPM_SMPB, 5, &pm8841_ftsmps, "vdd_s5" },
  842. { "s6", QCOM_SMD_RPM_SMPB, 6, &pm8841_ftsmps, "vdd_s6" },
  843. { "s7", QCOM_SMD_RPM_SMPB, 7, &pm8841_ftsmps, "vdd_s7" },
  844. { "s8", QCOM_SMD_RPM_SMPB, 8, &pm8841_ftsmps, "vdd_s8" },
  845. {}
  846. };
  847. static const struct rpm_regulator_data rpm_pm8909_regulators[] = {
  848. { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" },
  849. { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_hvo_smps, "vdd_s2" },
  850. { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1" },
  851. { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l2_l5" },
  852. { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l3_l6_l10" },
  853. { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l7" },
  854. { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_pldo, "vdd_l2_l5" },
  855. { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8226_pldo, "vdd_l3_l6_l10" },
  856. { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8226_pldo, "vdd_l4_l7" },
  857. { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l11_l15_l18" },
  858. { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
  859. { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_nldo, "vdd_l3_l6_l10" },
  860. { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8226_pldo, "vdd_l8_l11_l15_l18" },
  861. { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
  862. { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l13" },
  863. { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
  864. { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l11_l15_l18" },
  865. { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
  866. { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l11_l15_l18" },
  867. {}
  868. };
  869. static const struct rpm_regulator_data rpm_pm8916_regulators[] = {
  870. { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" },
  871. { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_lvo_smps, "vdd_s2" },
  872. { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8916_buck_lvo_smps, "vdd_s3" },
  873. { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8916_buck_hvo_smps, "vdd_s4" },
  874. { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1_l2_l3" },
  875. { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l1_l2_l3" },
  876. { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l1_l2_l3" },
  877. { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l5_l6" },
  878. { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8916_pldo, "vdd_l4_l5_l6" },
  879. { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8916_pldo, "vdd_l4_l5_l6" },
  880. { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8916_pldo, "vdd_l7" },
  881. { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
  882. { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
  883. { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
  884. { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
  885. { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
  886. { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
  887. { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
  888. { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
  889. { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
  890. { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
  891. { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
  892. {}
  893. };
  894. static const struct rpm_regulator_data rpm_pm8937_regulators[] = {
  895. { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8994_hfsmps, "vdd_s1" },
  896. { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8994_hfsmps, "vdd_s2" },
  897. { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8994_hfsmps, "vdd_s3" },
  898. { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8994_hfsmps, "vdd_s4" },
  899. /* S5 - S6 are managed by SPMI */
  900. { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8953_ult_nldo, "vdd_l1_l19" },
  901. { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8953_ult_nldo, "vdd_l2_l23" },
  902. { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8953_ult_nldo, "vdd_l3" },
  903. { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16" },
  904. { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16" },
  905. { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16" },
  906. { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16" },
  907. { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
  908. { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
  909. { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18"},
  910. { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
  911. { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
  912. { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
  913. { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
  914. { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
  915. { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16" },
  916. { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
  917. { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
  918. { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8953_ult_nldo, "vdd_l1_l19" },
  919. { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8953_lnldo, "vdd_l20_l21" },
  920. { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8953_lnldo, "vdd_l20_l21" },
  921. { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
  922. { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8994_nldo, "vdd_l2_l23" },
  923. {}
  924. };
  925. static const struct rpm_regulator_data rpm_pm8941_regulators[] = {
  926. { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8x41_hfsmps, "vdd_s1" },
  927. { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8x41_hfsmps, "vdd_s2" },
  928. { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8x41_hfsmps, "vdd_s3" },
  929. { "s4", QCOM_SMD_RPM_BOOST, 1, &pm8941_boost },
  930. { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8941_nldo, "vdd_l1_l3" },
  931. { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8941_nldo, "vdd_l2_lvs1_2_3" },
  932. { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8941_nldo, "vdd_l1_l3" },
  933. { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8941_nldo, "vdd_l4_l11" },
  934. { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8941_lnldo, "vdd_l5_l7" },
  935. { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
  936. { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8941_lnldo, "vdd_l5_l7" },
  937. { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
  938. { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
  939. { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
  940. { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8941_nldo, "vdd_l4_l11" },
  941. { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
  942. { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
  943. { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
  944. { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
  945. { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
  946. { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
  947. { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
  948. { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
  949. { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
  950. { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8941_pldo, "vdd_l21" },
  951. { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
  952. { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
  953. { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
  954. { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8941_switch, "vdd_l2_lvs1_2_3" },
  955. { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8941_switch, "vdd_l2_lvs1_2_3" },
  956. { "lvs3", QCOM_SMD_RPM_VSA, 3, &pm8941_switch, "vdd_l2_lvs1_2_3" },
  957. { "5vs1", QCOM_SMD_RPM_VSA, 4, &pm8941_switch, "vin_5vs" },
  958. { "5vs2", QCOM_SMD_RPM_VSA, 5, &pm8941_switch, "vin_5vs" },
  959. {}
  960. };
  961. static const struct rpm_regulator_data rpm_pm8950_regulators[] = {
  962. { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8950_hfsmps, "vdd_s1" },
  963. { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8950_hfsmps, "vdd_s2" },
  964. { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8950_hfsmps, "vdd_s3" },
  965. { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8950_hfsmps, "vdd_s4" },
  966. /* S5 is managed via SPMI. */
  967. { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8950_hfsmps, "vdd_s6" },
  968. { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8950_ult_nldo, "vdd_l1_l19" },
  969. { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8950_ult_nldo, "vdd_l2_l23" },
  970. { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8950_ult_nldo, "vdd_l3" },
  971. /* L4 seems not to exist. */
  972. { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
  973. { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
  974. { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
  975. { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
  976. { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
  977. { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_nldo, "vdd_l9_l10_l13_l14_l15_l18"},
  978. { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
  979. { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
  980. { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
  981. { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
  982. { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
  983. { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l5_l6_l7_l16" },
  984. { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
  985. /* L18 seems not to exist. */
  986. { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8950_pldo, "vdd_l1_l19" },
  987. /* L20 & L21 seem not to exist. */
  988. { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_pldo, "vdd_l8_l11_l12_l17_l22" },
  989. { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8950_pldo, "vdd_l2_l23" },
  990. {}
  991. };
  992. static const struct rpm_regulator_data rpm_pm8953_regulators[] = {
  993. { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_hfsmps, "vdd_s1" },
  994. { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_hfsmps, "vdd_s2" },
  995. { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" },
  996. { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" },
  997. { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8950_ftsmps2p5, "vdd_s5" },
  998. { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8950_ftsmps2p5, "vdd_s6" },
  999. { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_hfsmps, "vdd_s7" },
  1000. { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8953_ult_nldo, "vdd_l1" },
  1001. { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8953_ult_nldo, "vdd_l2_l3" },
  1002. { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8953_ult_nldo, "vdd_l2_l3" },
  1003. { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
  1004. { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
  1005. { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
  1006. { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
  1007. { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
  1008. { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
  1009. { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
  1010. { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
  1011. { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
  1012. { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
  1013. { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
  1014. { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
  1015. { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
  1016. { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
  1017. { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
  1018. { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8953_ult_nldo, "vdd_l4_l5_l6_l7_l16_l19" },
  1019. { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8953_lnldo, "vdd_l20" },
  1020. { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8953_lnldo, "vdd_l21" },
  1021. { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
  1022. { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8953_ult_nldo, "vdd_l23" },
  1023. {}
  1024. };
  1025. static const struct rpm_regulator_data rpm_pm8994_regulators[] = {
  1026. { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8994_ftsmps, "vdd_s1" },
  1027. { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8994_ftsmps, "vdd_s2" },
  1028. { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8994_hfsmps, "vdd_s3" },
  1029. { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8994_hfsmps, "vdd_s4" },
  1030. { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8994_hfsmps, "vdd_s5" },
  1031. { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8994_ftsmps, "vdd_s6" },
  1032. { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8994_hfsmps, "vdd_s7" },
  1033. { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8994_ftsmps, "vdd_s8" },
  1034. { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8994_ftsmps, "vdd_s9" },
  1035. { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8994_ftsmps, "vdd_s10" },
  1036. { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8994_ftsmps, "vdd_s11" },
  1037. { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8994_ftsmps, "vdd_s12" },
  1038. { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8994_nldo, "vdd_l1" },
  1039. { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8994_nldo, "vdd_l2_l26_l28" },
  1040. { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8994_nldo, "vdd_l3_l11" },
  1041. { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8994_nldo, "vdd_l4_l27_l31" },
  1042. { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8994_lnldo, "vdd_l5_l7" },
  1043. { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8994_pldo, "vdd_l6_l12_l32" },
  1044. { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8994_lnldo, "vdd_l5_l7" },
  1045. { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8994_pldo, "vdd_l8_l16_l30" },
  1046. { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
  1047. { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
  1048. { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8994_nldo, "vdd_l3_l11" },
  1049. { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8994_pldo, "vdd_l6_l12_l32" },
  1050. { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
  1051. { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8994_pldo, "vdd_l14_l15" },
  1052. { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8994_pldo, "vdd_l14_l15" },
  1053. { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8994_pldo, "vdd_l8_l16_l30" },
  1054. { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8994_pldo, "vdd_l17_l29" },
  1055. { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
  1056. { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
  1057. { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8994_pldo, "vdd_l20_l21" },
  1058. { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8994_pldo, "vdd_l20_l21" },
  1059. { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
  1060. { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
  1061. { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
  1062. { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8994_pldo, "vdd_l25" },
  1063. { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8994_nldo, "vdd_l2_l26_l28" },
  1064. { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8994_nldo, "vdd_l4_l27_l31" },
  1065. { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8994_nldo, "vdd_l2_l26_l28" },
  1066. { "l29", QCOM_SMD_RPM_LDOA, 29, &pm8994_pldo, "vdd_l17_l29" },
  1067. { "l30", QCOM_SMD_RPM_LDOA, 30, &pm8994_pldo, "vdd_l8_l16_l30" },
  1068. { "l31", QCOM_SMD_RPM_LDOA, 31, &pm8994_nldo, "vdd_l4_l27_l31" },
  1069. { "l32", QCOM_SMD_RPM_LDOA, 32, &pm8994_pldo, "vdd_l6_l12_l32" },
  1070. { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8994_switch, "vdd_lvs1_2" },
  1071. { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8994_switch, "vdd_lvs1_2" },
  1072. {}
  1073. };
  1074. static const struct rpm_regulator_data rpm_pm8998_regulators[] = {
  1075. { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_ftsmps, "vdd_s1" },
  1076. { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_ftsmps, "vdd_s2" },
  1077. { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" },
  1078. { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" },
  1079. { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" },
  1080. { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_ftsmps, "vdd_s6" },
  1081. { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_ftsmps, "vdd_s7" },
  1082. { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8998_ftsmps, "vdd_s8" },
  1083. { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8998_ftsmps, "vdd_s9" },
  1084. { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8998_ftsmps, "vdd_s10" },
  1085. { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8998_ftsmps, "vdd_s11" },
  1086. { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8998_ftsmps, "vdd_s12" },
  1087. { "s13", QCOM_SMD_RPM_SMPA, 13, &pm8998_ftsmps, "vdd_s13" },
  1088. { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8998_nldo, "vdd_l1_l27" },
  1089. { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8998_nldo, "vdd_l2_l8_l17" },
  1090. { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8998_nldo, "vdd_l3_l11" },
  1091. { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8998_nldo, "vdd_l4_l5" },
  1092. { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8998_nldo, "vdd_l4_l5" },
  1093. { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8998_pldo, "vdd_l6" },
  1094. { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
  1095. { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8998_nldo, "vdd_l2_l8_l17" },
  1096. { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8998_pldo, "vdd_l9" },
  1097. { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8998_pldo, "vdd_l10_l23_l25" },
  1098. { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8998_nldo, "vdd_l3_l11" },
  1099. { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
  1100. { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8998_pldo, "vdd_l13_l19_l21" },
  1101. { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
  1102. { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
  1103. { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8998_pldo, "vdd_l16_l28" },
  1104. { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8998_nldo, "vdd_l2_l8_l17" },
  1105. { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8998_pldo, "vdd_l18_l22" },
  1106. { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8998_pldo, "vdd_l13_l19_l21" },
  1107. { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8998_pldo, "vdd_l20_l24" },
  1108. { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8998_pldo, "vdd_l13_l19_l21" },
  1109. { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8998_pldo, "vdd_l18_l22" },
  1110. { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8998_pldo, "vdd_l10_l23_l25" },
  1111. { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8998_pldo, "vdd_l20_l24" },
  1112. { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8998_pldo, "vdd_l10_l23_l25" },
  1113. { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8998_nldo, "vdd_l26" },
  1114. { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8998_nldo, "vdd_l1_l27" },
  1115. { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8998_pldo, "vdd_l16_l28" },
  1116. { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8998_switch, "vdd_lvs1_lvs2" },
  1117. { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8998_switch, "vdd_lvs1_lvs2" },
  1118. {}
  1119. };
  1120. static const struct rpm_regulator_data rpm_pma8084_regulators[] = {
  1121. { "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" },
  1122. { "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" },
  1123. { "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" },
  1124. { "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" },
  1125. { "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" },
  1126. { "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" },
  1127. { "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" },
  1128. { "s8", QCOM_SMD_RPM_SMPA, 8, &pma8084_ftsmps, "vdd_s8" },
  1129. { "s9", QCOM_SMD_RPM_SMPA, 9, &pma8084_ftsmps, "vdd_s9" },
  1130. { "s10", QCOM_SMD_RPM_SMPA, 10, &pma8084_ftsmps, "vdd_s10" },
  1131. { "s11", QCOM_SMD_RPM_SMPA, 11, &pma8084_ftsmps, "vdd_s11" },
  1132. { "s12", QCOM_SMD_RPM_SMPA, 12, &pma8084_ftsmps, "vdd_s12" },
  1133. { "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" },
  1134. { "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
  1135. { "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
  1136. { "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
  1137. { "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" },
  1138. { "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
  1139. { "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" },
  1140. { "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" },
  1141. { "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
  1142. { "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
  1143. { "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" },
  1144. { "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
  1145. { "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
  1146. { "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
  1147. { "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
  1148. { "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" },
  1149. { "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" },
  1150. { "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" },
  1151. { "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" },
  1152. { "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
  1153. { "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" },
  1154. { "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" },
  1155. { "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
  1156. { "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
  1157. { "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" },
  1158. { "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
  1159. { "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
  1160. { "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch },
  1161. { "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch },
  1162. { "lvs3", QCOM_SMD_RPM_VSA, 3, &pma8084_switch },
  1163. { "lvs4", QCOM_SMD_RPM_VSA, 4, &pma8084_switch },
  1164. { "5vs1", QCOM_SMD_RPM_VSA, 5, &pma8084_switch },
  1165. {}
  1166. };
  1167. static const struct rpm_regulator_data rpm_pmi8994_regulators[] = {
  1168. { "s1", QCOM_SMD_RPM_SMPB, 1, &pmi8994_ftsmps, "vdd_s1" },
  1169. { "s2", QCOM_SMD_RPM_SMPB, 2, &pmi8994_hfsmps, "vdd_s2" },
  1170. { "s3", QCOM_SMD_RPM_SMPB, 3, &pmi8994_hfsmps, "vdd_s3" },
  1171. { "boost-bypass", QCOM_SMD_RPM_BBYB, 1, &pmi8994_bby, "vdd_bst_byp" },
  1172. {}
  1173. };
  1174. static const struct rpm_regulator_data rpm_pmi8998_regulators[] = {
  1175. { "bob", QCOM_SMD_RPM_BOBB, 1, &pmi8998_bob, "vdd_bob" },
  1176. {}
  1177. };
  1178. static const struct rpm_regulator_data rpm_pmr735a_regulators[] = {
  1179. { "s1", QCOM_SMD_RPM_SMPE, 1, &pmic5_ftsmps520, "vdd_s1"},
  1180. { "s2", QCOM_SMD_RPM_SMPE, 2, &pmic5_ftsmps520, "vdd_s2"},
  1181. { "s3", QCOM_SMD_RPM_SMPE, 3, &pmic5_hfsmps515, "vdd_s3"},
  1182. { "l1", QCOM_SMD_RPM_LDOE, 1, &pm660_nldo660, "vdd_l1_l2"},
  1183. { "l2", QCOM_SMD_RPM_LDOE, 2, &pm660_nldo660, "vdd_l1_l2"},
  1184. { "l3", QCOM_SMD_RPM_LDOE, 3, &pm660_nldo660, "vdd_l3"},
  1185. { "l4", QCOM_SMD_RPM_LDOE, 4, &pm660_ht_lvpldo, "vdd_l4"},
  1186. { "l5", QCOM_SMD_RPM_LDOE, 5, &pm660_nldo660, "vdd_l5_l6"},
  1187. { "l6", QCOM_SMD_RPM_LDOE, 6, &pm660_nldo660, "vdd_l5_l6"},
  1188. { "l7", QCOM_SMD_RPM_LDOE, 7, &pm660_pldo660, "vdd_l7_bob"},
  1189. {}
  1190. };
  1191. static const struct rpm_regulator_data rpm_pms405_regulators[] = {
  1192. { "s1", QCOM_SMD_RPM_SMPA, 1, &pms405_hfsmps3, "vdd_s1" },
  1193. { "s2", QCOM_SMD_RPM_SMPA, 2, &pms405_hfsmps3, "vdd_s2" },
  1194. { "s3", QCOM_SMD_RPM_SMPA, 3, &pms405_hfsmps3, "vdd_s3" },
  1195. { "s4", QCOM_SMD_RPM_SMPA, 4, &pms405_hfsmps3, "vdd_s4" },
  1196. { "s5", QCOM_SMD_RPM_SMPA, 5, &pms405_hfsmps3, "vdd_s5" },
  1197. { "l1", QCOM_SMD_RPM_LDOA, 1, &pms405_nldo1200, "vdd_l1_l2" },
  1198. { "l2", QCOM_SMD_RPM_LDOA, 2, &pms405_nldo1200, "vdd_l1_l2" },
  1199. { "l3", QCOM_SMD_RPM_LDOA, 3, &pms405_nldo1200, "vdd_l3_l8" },
  1200. { "l4", QCOM_SMD_RPM_LDOA, 4, &pms405_nldo300, "vdd_l4" },
  1201. { "l5", QCOM_SMD_RPM_LDOA, 5, &pms405_pldo600, "vdd_l5_l6" },
  1202. { "l6", QCOM_SMD_RPM_LDOA, 6, &pms405_pldo600, "vdd_l5_l6" },
  1203. { "l7", QCOM_SMD_RPM_LDOA, 7, &pms405_pldo150, "vdd_l7" },
  1204. { "l8", QCOM_SMD_RPM_LDOA, 8, &pms405_nldo1200, "vdd_l3_l8" },
  1205. { "l9", QCOM_SMD_RPM_LDOA, 9, &pms405_nldo1200, "vdd_l9" },
  1206. { "l10", QCOM_SMD_RPM_LDOA, 10, &pms405_pldo50, "vdd_l10_l11_l12_l13" },
  1207. { "l11", QCOM_SMD_RPM_LDOA, 11, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
  1208. { "l12", QCOM_SMD_RPM_LDOA, 12, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
  1209. { "l13", QCOM_SMD_RPM_LDOA, 13, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
  1210. {}
  1211. };
  1212. static const struct of_device_id rpm_of_match[] = {
  1213. { .compatible = "qcom,rpm-mp5496-regulators", .data = &rpm_mp5496_regulators },
  1214. { .compatible = "qcom,rpm-pm2250-regulators", .data = &rpm_pm2250_regulators },
  1215. { .compatible = "qcom,rpm-pm6125-regulators", .data = &rpm_pm6125_regulators },
  1216. { .compatible = "qcom,rpm-pm660-regulators", .data = &rpm_pm660_regulators },
  1217. { .compatible = "qcom,rpm-pm660l-regulators", .data = &rpm_pm660l_regulators },
  1218. { .compatible = "qcom,rpm-pm8226-regulators", .data = &rpm_pm8226_regulators },
  1219. { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators },
  1220. { .compatible = "qcom,rpm-pm8909-regulators", .data = &rpm_pm8909_regulators },
  1221. { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators },
  1222. { .compatible = "qcom,rpm-pm8937-regulators", .data = &rpm_pm8937_regulators },
  1223. { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators },
  1224. { .compatible = "qcom,rpm-pm8950-regulators", .data = &rpm_pm8950_regulators },
  1225. { .compatible = "qcom,rpm-pm8953-regulators", .data = &rpm_pm8953_regulators },
  1226. { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators },
  1227. { .compatible = "qcom,rpm-pm8998-regulators", .data = &rpm_pm8998_regulators },
  1228. { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators },
  1229. { .compatible = "qcom,rpm-pmi8994-regulators", .data = &rpm_pmi8994_regulators },
  1230. { .compatible = "qcom,rpm-pmi8998-regulators", .data = &rpm_pmi8998_regulators },
  1231. { .compatible = "qcom,rpm-pmr735a-regulators", .data = &rpm_pmr735a_regulators },
  1232. { .compatible = "qcom,rpm-pms405-regulators", .data = &rpm_pms405_regulators },
  1233. {}
  1234. };
  1235. MODULE_DEVICE_TABLE(of, rpm_of_match);
  1236. /**
  1237. * rpm_regulator_init_vreg() - initialize all attributes of a qcom_smd-regulator
  1238. * @vreg: Pointer to the individual qcom_smd-regulator resource
  1239. * @dev: Pointer to the top level qcom_smd-regulator PMIC device
  1240. * @node: Pointer to the individual qcom_smd-regulator resource
  1241. * device node
  1242. * @pmic_rpm_data: Pointer to a null-terminated array of qcom_smd-regulator
  1243. * resources defined for the top level PMIC device
  1244. *
  1245. * Return: 0 on success, or a negative error number on failure
  1246. */
  1247. static int rpm_regulator_init_vreg(struct qcom_rpm_reg *vreg, struct device *dev,
  1248. struct device_node *node,
  1249. const struct rpm_regulator_data *pmic_rpm_data)
  1250. {
  1251. struct regulator_config config = {};
  1252. const struct rpm_regulator_data *rpm_data;
  1253. struct regulator_dev *rdev;
  1254. int ret;
  1255. for (rpm_data = pmic_rpm_data; rpm_data->name; rpm_data++)
  1256. if (of_node_name_eq(node, rpm_data->name))
  1257. break;
  1258. if (!rpm_data->name) {
  1259. dev_err(dev, "Unknown regulator %pOFn\n", node);
  1260. return -EINVAL;
  1261. }
  1262. vreg->dev = dev;
  1263. vreg->type = rpm_data->type;
  1264. vreg->id = rpm_data->id;
  1265. memcpy(&vreg->desc, rpm_data->desc, sizeof(vreg->desc));
  1266. vreg->desc.name = rpm_data->name;
  1267. vreg->desc.supply_name = rpm_data->supply;
  1268. vreg->desc.owner = THIS_MODULE;
  1269. vreg->desc.type = REGULATOR_VOLTAGE;
  1270. vreg->desc.of_match = rpm_data->name;
  1271. config.dev = dev;
  1272. config.of_node = node;
  1273. config.driver_data = vreg;
  1274. rdev = devm_regulator_register(dev, &vreg->desc, &config);
  1275. if (IS_ERR(rdev)) {
  1276. ret = PTR_ERR(rdev);
  1277. dev_err(dev, "%pOFn: devm_regulator_register() failed, ret=%d\n", node, ret);
  1278. return ret;
  1279. }
  1280. return 0;
  1281. }
  1282. static int rpm_reg_probe(struct platform_device *pdev)
  1283. {
  1284. struct device *dev = &pdev->dev;
  1285. const struct rpm_regulator_data *vreg_data;
  1286. struct qcom_rpm_reg *vreg;
  1287. struct qcom_smd_rpm *rpm;
  1288. int ret;
  1289. rpm = dev_get_drvdata(pdev->dev.parent);
  1290. if (!rpm) {
  1291. dev_err(&pdev->dev, "Unable to retrieve handle to rpm\n");
  1292. return -ENODEV;
  1293. }
  1294. if (smd_vreg_rpm && rpm != smd_vreg_rpm)
  1295. return dev_err_probe(dev, -EINVAL, "RPM mismatch\n");
  1296. smd_vreg_rpm = rpm;
  1297. vreg_data = of_device_get_match_data(dev);
  1298. if (!vreg_data)
  1299. return -ENODEV;
  1300. for_each_available_child_of_node_scoped(dev->of_node, node) {
  1301. vreg = devm_kzalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL);
  1302. if (!vreg)
  1303. return -ENOMEM;
  1304. ret = rpm_regulator_init_vreg(vreg, dev, node, vreg_data);
  1305. if (ret < 0)
  1306. return ret;
  1307. }
  1308. return 0;
  1309. }
  1310. static struct platform_driver rpm_reg_driver = {
  1311. .probe = rpm_reg_probe,
  1312. .driver = {
  1313. .name = "qcom_rpm_smd_regulator",
  1314. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  1315. .of_match_table = rpm_of_match,
  1316. },
  1317. };
  1318. static int __init rpm_reg_init(void)
  1319. {
  1320. return platform_driver_register(&rpm_reg_driver);
  1321. }
  1322. subsys_initcall(rpm_reg_init);
  1323. static void __exit rpm_reg_exit(void)
  1324. {
  1325. platform_driver_unregister(&rpm_reg_driver);
  1326. }
  1327. module_exit(rpm_reg_exit)
  1328. MODULE_DESCRIPTION("Qualcomm RPM regulator driver");
  1329. MODULE_LICENSE("GPL v2");