stm32-pwr.c 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185
  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) STMicroelectronics 2019
  3. // Authors: Gabriel Fernandez <gabriel.fernandez@st.com>
  4. // Pascal Paillet <p.paillet@st.com>.
  5. #include <linux/io.h>
  6. #include <linux/iopoll.h>
  7. #include <linux/module.h>
  8. #include <linux/of.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/regulator/driver.h>
  11. #include <linux/regulator/of_regulator.h>
  12. /*
  13. * Registers description
  14. */
  15. #define REG_PWR_CR3 0x0C
  16. #define USB_3_3_EN BIT(24)
  17. #define USB_3_3_RDY BIT(26)
  18. #define REG_1_8_EN BIT(28)
  19. #define REG_1_8_RDY BIT(29)
  20. #define REG_1_1_EN BIT(30)
  21. #define REG_1_1_RDY BIT(31)
  22. /* list of supported regulators */
  23. enum {
  24. PWR_REG11,
  25. PWR_REG18,
  26. PWR_USB33,
  27. STM32PWR_REG_NUM_REGS
  28. };
  29. static u32 ready_mask_table[STM32PWR_REG_NUM_REGS] = {
  30. [PWR_REG11] = REG_1_1_RDY,
  31. [PWR_REG18] = REG_1_8_RDY,
  32. [PWR_USB33] = USB_3_3_RDY,
  33. };
  34. struct stm32_pwr_reg {
  35. void __iomem *base;
  36. u32 ready_mask;
  37. };
  38. static int stm32_pwr_reg_is_ready(struct regulator_dev *rdev)
  39. {
  40. struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
  41. u32 val;
  42. val = readl_relaxed(priv->base + REG_PWR_CR3);
  43. return (val & priv->ready_mask);
  44. }
  45. static int stm32_pwr_reg_is_enabled(struct regulator_dev *rdev)
  46. {
  47. struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
  48. u32 val;
  49. val = readl_relaxed(priv->base + REG_PWR_CR3);
  50. return (val & rdev->desc->enable_mask);
  51. }
  52. static int stm32_pwr_reg_enable(struct regulator_dev *rdev)
  53. {
  54. struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
  55. int ret;
  56. u32 val;
  57. val = readl_relaxed(priv->base + REG_PWR_CR3);
  58. val |= rdev->desc->enable_mask;
  59. writel_relaxed(val, priv->base + REG_PWR_CR3);
  60. /* use an arbitrary timeout of 20ms */
  61. ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, val,
  62. 100, 20 * 1000);
  63. if (ret)
  64. dev_err(&rdev->dev, "regulator enable timed out!\n");
  65. return ret;
  66. }
  67. static int stm32_pwr_reg_disable(struct regulator_dev *rdev)
  68. {
  69. struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
  70. int ret;
  71. u32 val;
  72. val = readl_relaxed(priv->base + REG_PWR_CR3);
  73. val &= ~rdev->desc->enable_mask;
  74. writel_relaxed(val, priv->base + REG_PWR_CR3);
  75. /* use an arbitrary timeout of 20ms */
  76. ret = readx_poll_timeout(stm32_pwr_reg_is_enabled, rdev, val, !val,
  77. 100, 20 * 1000);
  78. if (ret)
  79. dev_err(&rdev->dev, "regulator disable timed out!\n");
  80. return ret;
  81. }
  82. static const struct regulator_ops stm32_pwr_reg_ops = {
  83. .enable = stm32_pwr_reg_enable,
  84. .disable = stm32_pwr_reg_disable,
  85. .is_enabled = stm32_pwr_reg_is_enabled,
  86. };
  87. #define PWR_REG(_id, _name, _volt, _en, _supply) \
  88. [_id] = { \
  89. .id = _id, \
  90. .name = _name, \
  91. .of_match = of_match_ptr(_name), \
  92. .n_voltages = 1, \
  93. .type = REGULATOR_VOLTAGE, \
  94. .fixed_uV = _volt, \
  95. .ops = &stm32_pwr_reg_ops, \
  96. .enable_mask = _en, \
  97. .owner = THIS_MODULE, \
  98. .supply_name = _supply, \
  99. } \
  100. static const struct regulator_desc stm32_pwr_desc[] = {
  101. PWR_REG(PWR_REG11, "reg11", 1100000, REG_1_1_EN, "vdd"),
  102. PWR_REG(PWR_REG18, "reg18", 1800000, REG_1_8_EN, "vdd"),
  103. PWR_REG(PWR_USB33, "usb33", 3300000, USB_3_3_EN, "vdd_3v3_usbfs"),
  104. };
  105. static int stm32_pwr_regulator_probe(struct platform_device *pdev)
  106. {
  107. struct stm32_pwr_reg *priv;
  108. void __iomem *base;
  109. struct regulator_dev *rdev;
  110. struct regulator_config config = { };
  111. int i, ret = 0;
  112. base = devm_platform_ioremap_resource(pdev, 0);
  113. if (IS_ERR(base)) {
  114. dev_err(&pdev->dev, "Unable to map IO memory\n");
  115. return PTR_ERR(base);
  116. }
  117. config.dev = &pdev->dev;
  118. for (i = 0; i < STM32PWR_REG_NUM_REGS; i++) {
  119. priv = devm_kzalloc(&pdev->dev, sizeof(struct stm32_pwr_reg),
  120. GFP_KERNEL);
  121. if (!priv)
  122. return -ENOMEM;
  123. priv->base = base;
  124. priv->ready_mask = ready_mask_table[i];
  125. config.driver_data = priv;
  126. rdev = devm_regulator_register(&pdev->dev,
  127. &stm32_pwr_desc[i],
  128. &config);
  129. if (IS_ERR(rdev)) {
  130. ret = PTR_ERR(rdev);
  131. dev_err(&pdev->dev,
  132. "Failed to register regulator: %d\n", ret);
  133. break;
  134. }
  135. }
  136. return ret;
  137. }
  138. static const struct of_device_id __maybe_unused stm32_pwr_of_match[] = {
  139. { .compatible = "st,stm32mp1,pwr-reg", },
  140. { .compatible = "st,stm32mp13-pwr-reg", },
  141. {},
  142. };
  143. MODULE_DEVICE_TABLE(of, stm32_pwr_of_match);
  144. static struct platform_driver stm32_pwr_driver = {
  145. .probe = stm32_pwr_regulator_probe,
  146. .driver = {
  147. .name = "stm32-pwr-regulator",
  148. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  149. .of_match_table = of_match_ptr(stm32_pwr_of_match),
  150. },
  151. };
  152. module_platform_driver(stm32_pwr_driver);
  153. MODULE_DESCRIPTION("STM32MP1 PWR voltage regulator driver");
  154. MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");