Kconfig 11 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. config ARCH_HAS_RESET_CONTROLLER
  3. bool
  4. menuconfig RESET_CONTROLLER
  5. bool "Reset Controller Support"
  6. default y if ARCH_HAS_RESET_CONTROLLER
  7. help
  8. Generic Reset Controller support.
  9. This framework is designed to abstract reset handling of devices
  10. via GPIOs or SoC-internal reset controller modules.
  11. If unsure, say no.
  12. if RESET_CONTROLLER
  13. config RESET_A10SR
  14. tristate "Altera Arria10 System Resource Reset"
  15. depends on MFD_ALTERA_A10SR || COMPILE_TEST
  16. help
  17. This option enables support for the external reset functions for
  18. peripheral PHYs on the Altera Arria10 System Resource Chip.
  19. config RESET_ATH79
  20. bool "AR71xx Reset Driver" if COMPILE_TEST
  21. default ATH79
  22. help
  23. This enables the ATH79 reset controller driver that supports the
  24. AR71xx SoC reset controller.
  25. config RESET_AXS10X
  26. bool "AXS10x Reset Driver" if COMPILE_TEST
  27. default ARC_PLAT_AXS10X
  28. help
  29. This enables the reset controller driver for AXS10x.
  30. config RESET_BCM6345
  31. bool "BCM6345 Reset Controller"
  32. depends on BMIPS_GENERIC || COMPILE_TEST
  33. default BMIPS_GENERIC
  34. help
  35. This enables the reset controller driver for BCM6345 SoCs.
  36. config RESET_BERLIN
  37. tristate "Berlin Reset Driver"
  38. depends on ARCH_BERLIN || COMPILE_TEST
  39. default m if ARCH_BERLIN
  40. help
  41. This enables the reset controller driver for Marvell Berlin SoCs.
  42. config RESET_BRCMSTB
  43. tristate "Broadcom STB reset controller"
  44. depends on ARCH_BRCMSTB || COMPILE_TEST
  45. default ARCH_BRCMSTB
  46. help
  47. This enables the reset controller driver for Broadcom STB SoCs using
  48. a SUN_TOP_CTRL_SW_INIT style controller.
  49. config RESET_BRCMSTB_RESCAL
  50. tristate "Broadcom STB RESCAL reset controller"
  51. depends on HAS_IOMEM
  52. depends on ARCH_BRCMSTB || COMPILE_TEST
  53. default ARCH_BRCMSTB
  54. help
  55. This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
  56. BCM7216.
  57. config RESET_EYEQ
  58. bool "Mobileye EyeQ reset controller"
  59. depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
  60. select AUXILIARY_BUS
  61. default MACH_EYEQ5 || MACH_EYEQ6H
  62. help
  63. This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L
  64. and EyeQ6H SoCs.
  65. It has one or more domains, with a varying number of resets in each.
  66. Registers are located in a shared register region called OLB. EyeQ6H
  67. has multiple reset instances.
  68. config RESET_GPIO
  69. tristate "GPIO reset controller"
  70. depends on GPIOLIB
  71. help
  72. This enables a generic reset controller for resets attached via
  73. GPIOs. Typically for OF platforms this driver expects "reset-gpios"
  74. property.
  75. If compiled as module, it will be called reset-gpio.
  76. config RESET_HSDK
  77. bool "Synopsys HSDK Reset Driver"
  78. depends on HAS_IOMEM
  79. depends on ARC_SOC_HSDK || COMPILE_TEST
  80. help
  81. This enables the reset controller driver for HSDK board.
  82. config RESET_IMX7
  83. tristate "i.MX7/8 Reset Driver"
  84. depends on HAS_IOMEM
  85. depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
  86. default y if SOC_IMX7D
  87. select MFD_SYSCON
  88. help
  89. This enables the reset controller driver for i.MX7 SoCs.
  90. config RESET_IMX8MP_AUDIOMIX
  91. tristate "i.MX8MP AudioMix Reset Driver"
  92. depends on ARCH_MXC || COMPILE_TEST
  93. select AUXILIARY_BUS
  94. default CLK_IMX8MP
  95. help
  96. This enables the reset controller driver for i.MX8MP AudioMix
  97. config RESET_INTEL_GW
  98. bool "Intel Reset Controller Driver"
  99. depends on X86 || COMPILE_TEST
  100. depends on OF && HAS_IOMEM
  101. select REGMAP_MMIO
  102. help
  103. This enables the reset controller driver for Intel Gateway SoCs.
  104. Say Y to control the reset signals provided by reset controller.
  105. Otherwise, say N.
  106. config RESET_K210
  107. bool "Reset controller driver for Canaan Kendryte K210 SoC"
  108. depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF
  109. select MFD_SYSCON
  110. default SOC_CANAAN_K210
  111. help
  112. Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
  113. Say Y if you want to control reset signals provided by this
  114. controller.
  115. config RESET_LANTIQ
  116. bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
  117. default SOC_TYPE_XWAY
  118. help
  119. This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
  120. config RESET_LPC18XX
  121. bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
  122. default ARCH_LPC18XX
  123. help
  124. This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
  125. config RESET_MCHP_SPARX5
  126. bool "Microchip Sparx5 reset driver"
  127. depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST
  128. default y if SPARX5_SWITCH
  129. select MFD_SYSCON
  130. help
  131. This driver supports switch core reset for the Microchip Sparx5 SoC.
  132. config RESET_MESON
  133. tristate "Meson Reset Driver"
  134. depends on ARCH_MESON || COMPILE_TEST
  135. default ARCH_MESON
  136. help
  137. This enables the reset driver for Amlogic Meson SoCs.
  138. config RESET_MESON_AUDIO_ARB
  139. tristate "Meson Audio Memory Arbiter Reset Driver"
  140. depends on ARCH_MESON || COMPILE_TEST
  141. help
  142. This enables the reset driver for Audio Memory Arbiter of
  143. Amlogic's A113 based SoCs
  144. config RESET_NPCM
  145. bool "NPCM BMC Reset Driver" if COMPILE_TEST
  146. default ARCH_NPCM
  147. help
  148. This enables the reset controller driver for Nuvoton NPCM
  149. BMC SoCs.
  150. config RESET_NUVOTON_MA35D1
  151. bool "Nuvoton MA35D1 Reset Driver"
  152. depends on ARCH_MA35 || COMPILE_TEST
  153. default ARCH_MA35
  154. help
  155. This enables the reset controller driver for Nuvoton MA35D1 SoC.
  156. config RESET_PISTACHIO
  157. bool "Pistachio Reset Driver"
  158. depends on MIPS || COMPILE_TEST
  159. help
  160. This enables the reset driver for ImgTec Pistachio SoCs.
  161. config RESET_POLARFIRE_SOC
  162. bool "Microchip PolarFire SoC (MPFS) Reset Driver"
  163. depends on MCHP_CLK_MPFS
  164. select AUXILIARY_BUS
  165. default MCHP_CLK_MPFS
  166. help
  167. This driver supports peripheral reset for the Microchip PolarFire SoC
  168. config RESET_QCOM_AOSS
  169. tristate "Qcom AOSS Reset Driver"
  170. depends on ARCH_QCOM || COMPILE_TEST
  171. help
  172. This enables the AOSS (always on subsystem) reset driver
  173. for Qualcomm SDM845 SoCs. Say Y if you want to control
  174. reset signals provided by AOSS for Modem, Venus, ADSP,
  175. GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
  176. config RESET_QCOM_PDC
  177. tristate "Qualcomm PDC Reset Driver"
  178. depends on ARCH_QCOM || COMPILE_TEST
  179. help
  180. This enables the PDC (Power Domain Controller) reset driver
  181. for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
  182. to control reset signals provided by PDC for Modem, Compute,
  183. Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
  184. config RESET_RASPBERRYPI
  185. tristate "Raspberry Pi 4 Firmware Reset Driver"
  186. depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
  187. default USB_XHCI_PCI
  188. help
  189. Raspberry Pi 4's co-processor controls some of the board's HW
  190. initialization process, but it's up to Linux to trigger it when
  191. relevant. This driver provides a reset controller capable of
  192. interfacing with RPi4's co-processor and model these firmware
  193. initialization routines as reset lines.
  194. config RESET_RZG2L_USBPHY_CTRL
  195. tristate "Renesas RZ/G2L USBPHY control driver"
  196. depends on ARCH_RZG2L || COMPILE_TEST
  197. help
  198. Support for USBPHY Control found on RZ/G2L family. It mainly
  199. controls reset and power down of the USB/PHY.
  200. config RESET_SCMI
  201. tristate "Reset driver controlled via ARM SCMI interface"
  202. depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
  203. default ARM_SCMI_PROTOCOL
  204. help
  205. This driver provides support for reset signal/domains that are
  206. controlled by firmware that implements the SCMI interface.
  207. This driver uses SCMI Message Protocol to interact with the
  208. firmware controlling all the reset signals.
  209. config RESET_SIMPLE
  210. bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
  211. default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
  212. depends on HAS_IOMEM
  213. help
  214. This enables a simple reset controller driver for reset lines that
  215. that can be asserted and deasserted by toggling bits in a contiguous,
  216. exclusive register space.
  217. Currently this driver supports:
  218. - Altera SoCFPGAs
  219. - ASPEED BMC SoCs
  220. - Bitmain BM1880 SoC
  221. - Realtek SoCs
  222. - RCC reset controller in STM32 MCUs
  223. - Allwinner SoCs
  224. - SiFive FU740 SoCs
  225. - Sophgo SoCs
  226. config RESET_SOCFPGA
  227. bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
  228. default ARM && ARCH_INTEL_SOCFPGA
  229. select RESET_SIMPLE
  230. help
  231. This enables the reset driver for the SoCFPGA ARMv7 platforms. This
  232. driver gets initialized early during platform init calls.
  233. config RESET_SUNPLUS
  234. bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
  235. default ARCH_SUNPLUS
  236. help
  237. This enables the reset driver support for Sunplus SoCs.
  238. The reset lines that can be asserted and deasserted by toggling bits
  239. in a contiguous, exclusive register space. The register is HIWORD_MASKED,
  240. which means each register holds 16 reset lines.
  241. config RESET_SUNXI
  242. bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
  243. default ARCH_SUNXI
  244. select RESET_SIMPLE
  245. help
  246. This enables the reset driver for Allwinner SoCs.
  247. config RESET_TI_SCI
  248. tristate "TI System Control Interface (TI-SCI) reset driver"
  249. depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)
  250. help
  251. This enables the reset driver support over TI System Control Interface
  252. available on some new TI's SoCs. If you wish to use reset resources
  253. managed by the TI System Controller, say Y here. Otherwise, say N.
  254. config RESET_TI_SYSCON
  255. tristate "TI SYSCON Reset Driver"
  256. depends on HAS_IOMEM
  257. select MFD_SYSCON
  258. help
  259. This enables the reset driver support for TI devices with
  260. memory-mapped reset registers as part of a syscon device node. If
  261. you wish to use the reset framework for such memory-mapped devices,
  262. say Y here. Otherwise, say N.
  263. config RESET_TI_TPS380X
  264. tristate "TI TPS380x Reset Driver"
  265. select GPIOLIB
  266. help
  267. This enables the reset driver support for TI TPS380x devices. If
  268. you wish to use the reset framework for such devices, say Y here.
  269. Otherwise, say N.
  270. config RESET_TN48M_CPLD
  271. tristate "Delta Networks TN48M switch CPLD reset controller"
  272. depends on MFD_TN48M_CPLD || COMPILE_TEST
  273. default MFD_TN48M_CPLD
  274. help
  275. This enables the reset controller driver for the Delta TN48M CPLD.
  276. It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
  277. switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
  278. Microchip PD69200 PoE PSE controller.
  279. This driver can also be built as a module. If so, the module will be
  280. called reset-tn48m.
  281. config RESET_UNIPHIER
  282. tristate "Reset controller driver for UniPhier SoCs"
  283. depends on ARCH_UNIPHIER || COMPILE_TEST
  284. depends on OF && MFD_SYSCON
  285. default ARCH_UNIPHIER
  286. help
  287. Support for reset controllers on UniPhier SoCs.
  288. Say Y if you want to control reset signals provided by System Control
  289. block, Media I/O block, Peripheral Block.
  290. config RESET_UNIPHIER_GLUE
  291. tristate "Reset driver in glue layer for UniPhier SoCs"
  292. depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
  293. default ARCH_UNIPHIER
  294. select RESET_SIMPLE
  295. help
  296. Support for peripheral core reset included in its own glue layer
  297. on UniPhier SoCs. Say Y if you want to control reset signals
  298. provided by the glue layer.
  299. config RESET_ZYNQ
  300. bool "ZYNQ Reset Driver" if COMPILE_TEST
  301. default ARCH_ZYNQ
  302. help
  303. This enables the reset controller driver for Xilinx Zynq SoCs.
  304. config RESET_ZYNQMP
  305. bool "ZYNQMP Reset Driver" if COMPILE_TEST
  306. default ARCH_ZYNQMP
  307. help
  308. This enables the reset controller driver for Xilinx ZynqMP SoCs.
  309. source "drivers/reset/starfive/Kconfig"
  310. source "drivers/reset/sti/Kconfig"
  311. source "drivers/reset/hisilicon/Kconfig"
  312. source "drivers/reset/tegra/Kconfig"
  313. endif