rtc-abx80x.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * A driver for the I2C members of the Abracon AB x8xx RTC family,
  4. * and compatible: AB 1805 and AB 0805
  5. *
  6. * Copyright 2014-2015 Macq S.A.
  7. *
  8. * Author: Philippe De Muyter <phdm@macqel.be>
  9. * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
  10. *
  11. */
  12. #include <linux/bcd.h>
  13. #include <linux/bitfield.h>
  14. #include <linux/i2c.h>
  15. #include <linux/kstrtox.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/rtc.h>
  19. #include <linux/watchdog.h>
  20. #define ABX8XX_REG_HTH 0x00
  21. #define ABX8XX_REG_SC 0x01
  22. #define ABX8XX_REG_MN 0x02
  23. #define ABX8XX_REG_HR 0x03
  24. #define ABX8XX_REG_DA 0x04
  25. #define ABX8XX_REG_MO 0x05
  26. #define ABX8XX_REG_YR 0x06
  27. #define ABX8XX_REG_WD 0x07
  28. #define ABX8XX_REG_AHTH 0x08
  29. #define ABX8XX_REG_ASC 0x09
  30. #define ABX8XX_REG_AMN 0x0a
  31. #define ABX8XX_REG_AHR 0x0b
  32. #define ABX8XX_REG_ADA 0x0c
  33. #define ABX8XX_REG_AMO 0x0d
  34. #define ABX8XX_REG_AWD 0x0e
  35. #define ABX8XX_REG_STATUS 0x0f
  36. #define ABX8XX_STATUS_AF BIT(2)
  37. #define ABX8XX_STATUS_BLF BIT(4)
  38. #define ABX8XX_STATUS_WDT BIT(5)
  39. #define ABX8XX_REG_CTRL1 0x10
  40. #define ABX8XX_CTRL_WRITE BIT(0)
  41. #define ABX8XX_CTRL_ARST BIT(2)
  42. #define ABX8XX_CTRL_12_24 BIT(6)
  43. #define ABX8XX_REG_CTRL2 0x11
  44. #define ABX8XX_CTRL2_RSVD BIT(5)
  45. #define ABX8XX_REG_IRQ 0x12
  46. #define ABX8XX_IRQ_AIE BIT(2)
  47. #define ABX8XX_IRQ_IM_1_4 (0x3 << 5)
  48. #define ABX8XX_REG_CD_TIMER_CTL 0x18
  49. #define ABX8XX_REG_OSC 0x1c
  50. #define ABX8XX_OSC_FOS BIT(3)
  51. #define ABX8XX_OSC_BOS BIT(4)
  52. #define ABX8XX_OSC_ACAL_512 BIT(5)
  53. #define ABX8XX_OSC_ACAL_1024 BIT(6)
  54. #define ABX8XX_OSC_OSEL BIT(7)
  55. #define ABX8XX_REG_OSS 0x1d
  56. #define ABX8XX_OSS_OF BIT(1)
  57. #define ABX8XX_OSS_OMODE BIT(4)
  58. #define ABX8XX_REG_WDT 0x1b
  59. #define ABX8XX_WDT_WDS BIT(7)
  60. #define ABX8XX_WDT_BMB_MASK 0x7c
  61. #define ABX8XX_WDT_BMB_SHIFT 2
  62. #define ABX8XX_WDT_MAX_TIME (ABX8XX_WDT_BMB_MASK >> ABX8XX_WDT_BMB_SHIFT)
  63. #define ABX8XX_WDT_WRB_MASK 0x03
  64. #define ABX8XX_WDT_WRB_1HZ 0x02
  65. #define ABX8XX_REG_CFG_KEY 0x1f
  66. #define ABX8XX_CFG_KEY_OSC 0xa1
  67. #define ABX8XX_CFG_KEY_MISC 0x9d
  68. #define ABX8XX_REG_ID0 0x28
  69. #define ABX8XX_REG_OUT_CTRL 0x30
  70. #define ABX8XX_OUT_CTRL_EXDS BIT(4)
  71. #define ABX8XX_REG_TRICKLE 0x20
  72. #define ABX8XX_TRICKLE_CHARGE_ENABLE 0xa0
  73. #define ABX8XX_TRICKLE_STANDARD_DIODE 0x8
  74. #define ABX8XX_TRICKLE_SCHOTTKY_DIODE 0x4
  75. #define ABX8XX_REG_EXTRAM 0x3f
  76. #define ABX8XX_EXTRAM_XADS GENMASK(1, 0)
  77. #define ABX8XX_SRAM_BASE 0x40
  78. #define ABX8XX_SRAM_WIN_SIZE 0x40
  79. #define ABX8XX_RAM_SIZE 256
  80. #define NVMEM_ADDR_LOWER GENMASK(5, 0)
  81. #define NVMEM_ADDR_UPPER GENMASK(7, 6)
  82. static u8 trickle_resistors[] = {0, 3, 6, 11};
  83. enum abx80x_chip {AB0801, AB0803, AB0804, AB0805,
  84. AB1801, AB1803, AB1804, AB1805, RV1805, ABX80X};
  85. struct abx80x_cap {
  86. u16 pn;
  87. bool has_tc;
  88. bool has_wdog;
  89. };
  90. static struct abx80x_cap abx80x_caps[] = {
  91. [AB0801] = {.pn = 0x0801},
  92. [AB0803] = {.pn = 0x0803},
  93. [AB0804] = {.pn = 0x0804, .has_tc = true, .has_wdog = true},
  94. [AB0805] = {.pn = 0x0805, .has_tc = true, .has_wdog = true},
  95. [AB1801] = {.pn = 0x1801},
  96. [AB1803] = {.pn = 0x1803},
  97. [AB1804] = {.pn = 0x1804, .has_tc = true, .has_wdog = true},
  98. [AB1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
  99. [RV1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
  100. [ABX80X] = {.pn = 0}
  101. };
  102. struct abx80x_priv {
  103. struct rtc_device *rtc;
  104. struct i2c_client *client;
  105. struct watchdog_device wdog;
  106. };
  107. static int abx80x_write_config_key(struct i2c_client *client, u8 key)
  108. {
  109. if (i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY, key) < 0) {
  110. dev_err(&client->dev, "Unable to write configuration key\n");
  111. return -EIO;
  112. }
  113. return 0;
  114. }
  115. static int abx80x_is_rc_mode(struct i2c_client *client)
  116. {
  117. int flags = 0;
  118. flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS);
  119. if (flags < 0) {
  120. dev_err(&client->dev,
  121. "Failed to read autocalibration attribute\n");
  122. return flags;
  123. }
  124. return (flags & ABX8XX_OSS_OMODE) ? 1 : 0;
  125. }
  126. static int abx80x_enable_trickle_charger(struct i2c_client *client,
  127. u8 trickle_cfg)
  128. {
  129. int err;
  130. /*
  131. * Write the configuration key register to enable access to the Trickle
  132. * register
  133. */
  134. if (abx80x_write_config_key(client, ABX8XX_CFG_KEY_MISC) < 0)
  135. return -EIO;
  136. err = i2c_smbus_write_byte_data(client, ABX8XX_REG_TRICKLE,
  137. ABX8XX_TRICKLE_CHARGE_ENABLE |
  138. trickle_cfg);
  139. if (err < 0) {
  140. dev_err(&client->dev, "Unable to write trickle register\n");
  141. return -EIO;
  142. }
  143. return 0;
  144. }
  145. static int abx80x_rtc_read_time(struct device *dev, struct rtc_time *tm)
  146. {
  147. struct i2c_client *client = to_i2c_client(dev);
  148. unsigned char buf[8];
  149. int err, flags, rc_mode = 0;
  150. /* Read the Oscillator Failure only in XT mode */
  151. rc_mode = abx80x_is_rc_mode(client);
  152. if (rc_mode < 0)
  153. return rc_mode;
  154. if (!rc_mode) {
  155. flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS);
  156. if (flags < 0)
  157. return flags;
  158. if (flags & ABX8XX_OSS_OF) {
  159. dev_err(dev, "Oscillator failure, data is invalid.\n");
  160. return -EINVAL;
  161. }
  162. }
  163. err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_HTH,
  164. sizeof(buf), buf);
  165. if (err < 0) {
  166. dev_err(&client->dev, "Unable to read date\n");
  167. return -EIO;
  168. }
  169. tm->tm_sec = bcd2bin(buf[ABX8XX_REG_SC] & 0x7F);
  170. tm->tm_min = bcd2bin(buf[ABX8XX_REG_MN] & 0x7F);
  171. tm->tm_hour = bcd2bin(buf[ABX8XX_REG_HR] & 0x3F);
  172. tm->tm_wday = buf[ABX8XX_REG_WD] & 0x7;
  173. tm->tm_mday = bcd2bin(buf[ABX8XX_REG_DA] & 0x3F);
  174. tm->tm_mon = bcd2bin(buf[ABX8XX_REG_MO] & 0x1F) - 1;
  175. tm->tm_year = bcd2bin(buf[ABX8XX_REG_YR]) + 100;
  176. return 0;
  177. }
  178. static int abx80x_rtc_set_time(struct device *dev, struct rtc_time *tm)
  179. {
  180. struct i2c_client *client = to_i2c_client(dev);
  181. unsigned char buf[8];
  182. int err, flags;
  183. if (tm->tm_year < 100)
  184. return -EINVAL;
  185. buf[ABX8XX_REG_HTH] = 0;
  186. buf[ABX8XX_REG_SC] = bin2bcd(tm->tm_sec);
  187. buf[ABX8XX_REG_MN] = bin2bcd(tm->tm_min);
  188. buf[ABX8XX_REG_HR] = bin2bcd(tm->tm_hour);
  189. buf[ABX8XX_REG_DA] = bin2bcd(tm->tm_mday);
  190. buf[ABX8XX_REG_MO] = bin2bcd(tm->tm_mon + 1);
  191. buf[ABX8XX_REG_YR] = bin2bcd(tm->tm_year - 100);
  192. buf[ABX8XX_REG_WD] = tm->tm_wday;
  193. err = i2c_smbus_write_i2c_block_data(client, ABX8XX_REG_HTH,
  194. sizeof(buf), buf);
  195. if (err < 0) {
  196. dev_err(&client->dev, "Unable to write to date registers\n");
  197. return -EIO;
  198. }
  199. /* Clear the OF bit of Oscillator Status Register */
  200. flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS);
  201. if (flags < 0)
  202. return flags;
  203. err = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSS,
  204. flags & ~ABX8XX_OSS_OF);
  205. if (err < 0) {
  206. dev_err(&client->dev, "Unable to write oscillator status register\n");
  207. return err;
  208. }
  209. return 0;
  210. }
  211. static irqreturn_t abx80x_handle_irq(int irq, void *dev_id)
  212. {
  213. struct i2c_client *client = dev_id;
  214. struct abx80x_priv *priv = i2c_get_clientdata(client);
  215. struct rtc_device *rtc = priv->rtc;
  216. int status;
  217. status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS);
  218. if (status < 0)
  219. return IRQ_NONE;
  220. if (status & ABX8XX_STATUS_AF)
  221. rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);
  222. /*
  223. * It is unclear if we'll get an interrupt before the external
  224. * reset kicks in.
  225. */
  226. if (status & ABX8XX_STATUS_WDT)
  227. dev_alert(&client->dev, "watchdog timeout interrupt.\n");
  228. i2c_smbus_write_byte_data(client, ABX8XX_REG_STATUS, 0);
  229. return IRQ_HANDLED;
  230. }
  231. static int abx80x_read_alarm(struct device *dev, struct rtc_wkalrm *t)
  232. {
  233. struct i2c_client *client = to_i2c_client(dev);
  234. unsigned char buf[7];
  235. int irq_mask, err;
  236. if (client->irq <= 0)
  237. return -EINVAL;
  238. err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_ASC,
  239. sizeof(buf), buf);
  240. if (err)
  241. return err;
  242. irq_mask = i2c_smbus_read_byte_data(client, ABX8XX_REG_IRQ);
  243. if (irq_mask < 0)
  244. return irq_mask;
  245. t->time.tm_sec = bcd2bin(buf[0] & 0x7F);
  246. t->time.tm_min = bcd2bin(buf[1] & 0x7F);
  247. t->time.tm_hour = bcd2bin(buf[2] & 0x3F);
  248. t->time.tm_mday = bcd2bin(buf[3] & 0x3F);
  249. t->time.tm_mon = bcd2bin(buf[4] & 0x1F) - 1;
  250. t->time.tm_wday = buf[5] & 0x7;
  251. t->enabled = !!(irq_mask & ABX8XX_IRQ_AIE);
  252. t->pending = (buf[6] & ABX8XX_STATUS_AF) && t->enabled;
  253. return err;
  254. }
  255. static int abx80x_set_alarm(struct device *dev, struct rtc_wkalrm *t)
  256. {
  257. struct i2c_client *client = to_i2c_client(dev);
  258. u8 alarm[6];
  259. int err;
  260. if (client->irq <= 0)
  261. return -EINVAL;
  262. alarm[0] = 0x0;
  263. alarm[1] = bin2bcd(t->time.tm_sec);
  264. alarm[2] = bin2bcd(t->time.tm_min);
  265. alarm[3] = bin2bcd(t->time.tm_hour);
  266. alarm[4] = bin2bcd(t->time.tm_mday);
  267. alarm[5] = bin2bcd(t->time.tm_mon + 1);
  268. err = i2c_smbus_write_i2c_block_data(client, ABX8XX_REG_AHTH,
  269. sizeof(alarm), alarm);
  270. if (err < 0) {
  271. dev_err(&client->dev, "Unable to write alarm registers\n");
  272. return -EIO;
  273. }
  274. if (t->enabled) {
  275. err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ,
  276. (ABX8XX_IRQ_IM_1_4 |
  277. ABX8XX_IRQ_AIE));
  278. if (err)
  279. return err;
  280. }
  281. return 0;
  282. }
  283. static int abx80x_rtc_set_autocalibration(struct device *dev,
  284. int autocalibration)
  285. {
  286. struct i2c_client *client = to_i2c_client(dev);
  287. int retval, flags = 0;
  288. if ((autocalibration != 0) && (autocalibration != 1024) &&
  289. (autocalibration != 512)) {
  290. dev_err(dev, "autocalibration value outside permitted range\n");
  291. return -EINVAL;
  292. }
  293. flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC);
  294. if (flags < 0)
  295. return flags;
  296. if (autocalibration == 0) {
  297. flags &= ~(ABX8XX_OSC_ACAL_512 | ABX8XX_OSC_ACAL_1024);
  298. } else if (autocalibration == 1024) {
  299. /* 1024 autocalibration is 0x10 */
  300. flags |= ABX8XX_OSC_ACAL_1024;
  301. flags &= ~(ABX8XX_OSC_ACAL_512);
  302. } else {
  303. /* 512 autocalibration is 0x11 */
  304. flags |= (ABX8XX_OSC_ACAL_1024 | ABX8XX_OSC_ACAL_512);
  305. }
  306. /* Unlock write access to Oscillator Control Register */
  307. if (abx80x_write_config_key(client, ABX8XX_CFG_KEY_OSC) < 0)
  308. return -EIO;
  309. retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSC, flags);
  310. return retval;
  311. }
  312. static int abx80x_rtc_get_autocalibration(struct device *dev)
  313. {
  314. struct i2c_client *client = to_i2c_client(dev);
  315. int flags = 0, autocalibration;
  316. flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC);
  317. if (flags < 0)
  318. return flags;
  319. if (flags & ABX8XX_OSC_ACAL_512)
  320. autocalibration = 512;
  321. else if (flags & ABX8XX_OSC_ACAL_1024)
  322. autocalibration = 1024;
  323. else
  324. autocalibration = 0;
  325. return autocalibration;
  326. }
  327. static ssize_t autocalibration_store(struct device *dev,
  328. struct device_attribute *attr,
  329. const char *buf, size_t count)
  330. {
  331. int retval;
  332. unsigned long autocalibration = 0;
  333. retval = kstrtoul(buf, 10, &autocalibration);
  334. if (retval < 0) {
  335. dev_err(dev, "Failed to store RTC autocalibration attribute\n");
  336. return -EINVAL;
  337. }
  338. retval = abx80x_rtc_set_autocalibration(dev->parent, autocalibration);
  339. return retval ? retval : count;
  340. }
  341. static ssize_t autocalibration_show(struct device *dev,
  342. struct device_attribute *attr, char *buf)
  343. {
  344. int autocalibration = 0;
  345. autocalibration = abx80x_rtc_get_autocalibration(dev->parent);
  346. if (autocalibration < 0) {
  347. dev_err(dev, "Failed to read RTC autocalibration\n");
  348. sprintf(buf, "0\n");
  349. return autocalibration;
  350. }
  351. return sprintf(buf, "%d\n", autocalibration);
  352. }
  353. static DEVICE_ATTR_RW(autocalibration);
  354. static ssize_t oscillator_store(struct device *dev,
  355. struct device_attribute *attr,
  356. const char *buf, size_t count)
  357. {
  358. struct i2c_client *client = to_i2c_client(dev->parent);
  359. int retval, flags, rc_mode = 0;
  360. if (strncmp(buf, "rc", 2) == 0) {
  361. rc_mode = 1;
  362. } else if (strncmp(buf, "xtal", 4) == 0) {
  363. rc_mode = 0;
  364. } else {
  365. dev_err(dev, "Oscillator selection value outside permitted ones\n");
  366. return -EINVAL;
  367. }
  368. flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC);
  369. if (flags < 0)
  370. return flags;
  371. if (rc_mode == 0)
  372. flags &= ~(ABX8XX_OSC_OSEL);
  373. else
  374. flags |= (ABX8XX_OSC_OSEL);
  375. /* Unlock write access on Oscillator Control register */
  376. if (abx80x_write_config_key(client, ABX8XX_CFG_KEY_OSC) < 0)
  377. return -EIO;
  378. retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSC, flags);
  379. if (retval < 0) {
  380. dev_err(dev, "Failed to write Oscillator Control register\n");
  381. return retval;
  382. }
  383. return retval ? retval : count;
  384. }
  385. static ssize_t oscillator_show(struct device *dev,
  386. struct device_attribute *attr, char *buf)
  387. {
  388. int rc_mode = 0;
  389. struct i2c_client *client = to_i2c_client(dev->parent);
  390. rc_mode = abx80x_is_rc_mode(client);
  391. if (rc_mode < 0) {
  392. dev_err(dev, "Failed to read RTC oscillator selection\n");
  393. sprintf(buf, "\n");
  394. return rc_mode;
  395. }
  396. if (rc_mode)
  397. return sprintf(buf, "rc\n");
  398. else
  399. return sprintf(buf, "xtal\n");
  400. }
  401. static DEVICE_ATTR_RW(oscillator);
  402. static struct attribute *rtc_calib_attrs[] = {
  403. &dev_attr_autocalibration.attr,
  404. &dev_attr_oscillator.attr,
  405. NULL,
  406. };
  407. static const struct attribute_group rtc_calib_attr_group = {
  408. .attrs = rtc_calib_attrs,
  409. };
  410. static int abx80x_alarm_irq_enable(struct device *dev, unsigned int enabled)
  411. {
  412. struct i2c_client *client = to_i2c_client(dev);
  413. int err;
  414. if (enabled)
  415. err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ,
  416. (ABX8XX_IRQ_IM_1_4 |
  417. ABX8XX_IRQ_AIE));
  418. else
  419. err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ,
  420. ABX8XX_IRQ_IM_1_4);
  421. return err;
  422. }
  423. static int abx80x_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
  424. {
  425. struct i2c_client *client = to_i2c_client(dev);
  426. int status, tmp;
  427. switch (cmd) {
  428. case RTC_VL_READ:
  429. status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS);
  430. if (status < 0)
  431. return status;
  432. tmp = status & ABX8XX_STATUS_BLF ? RTC_VL_BACKUP_LOW : 0;
  433. return put_user(tmp, (unsigned int __user *)arg);
  434. case RTC_VL_CLR:
  435. status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS);
  436. if (status < 0)
  437. return status;
  438. status &= ~ABX8XX_STATUS_BLF;
  439. tmp = i2c_smbus_write_byte_data(client, ABX8XX_REG_STATUS, 0);
  440. if (tmp < 0)
  441. return tmp;
  442. return 0;
  443. default:
  444. return -ENOIOCTLCMD;
  445. }
  446. }
  447. static const struct rtc_class_ops abx80x_rtc_ops = {
  448. .read_time = abx80x_rtc_read_time,
  449. .set_time = abx80x_rtc_set_time,
  450. .read_alarm = abx80x_read_alarm,
  451. .set_alarm = abx80x_set_alarm,
  452. .alarm_irq_enable = abx80x_alarm_irq_enable,
  453. .ioctl = abx80x_ioctl,
  454. };
  455. static int abx80x_dt_trickle_cfg(struct i2c_client *client)
  456. {
  457. struct device_node *np = client->dev.of_node;
  458. const char *diode;
  459. int trickle_cfg = 0;
  460. int i, ret;
  461. u32 tmp;
  462. ret = of_property_read_string(np, "abracon,tc-diode", &diode);
  463. if (ret)
  464. return ret;
  465. if (!strcmp(diode, "standard")) {
  466. trickle_cfg |= ABX8XX_TRICKLE_STANDARD_DIODE;
  467. } else if (!strcmp(diode, "schottky")) {
  468. trickle_cfg |= ABX8XX_TRICKLE_SCHOTTKY_DIODE;
  469. } else {
  470. dev_dbg(&client->dev, "Invalid tc-diode value: %s\n", diode);
  471. return -EINVAL;
  472. }
  473. ret = of_property_read_u32(np, "abracon,tc-resistor", &tmp);
  474. if (ret)
  475. return ret;
  476. for (i = 0; i < sizeof(trickle_resistors); i++)
  477. if (trickle_resistors[i] == tmp)
  478. break;
  479. if (i == sizeof(trickle_resistors)) {
  480. dev_dbg(&client->dev, "Invalid tc-resistor value: %u\n", tmp);
  481. return -EINVAL;
  482. }
  483. return (trickle_cfg | i);
  484. }
  485. #ifdef CONFIG_WATCHDOG
  486. static inline u8 timeout_bits(unsigned int timeout)
  487. {
  488. return ((timeout << ABX8XX_WDT_BMB_SHIFT) & ABX8XX_WDT_BMB_MASK) |
  489. ABX8XX_WDT_WRB_1HZ;
  490. }
  491. static int __abx80x_wdog_set_timeout(struct watchdog_device *wdog,
  492. unsigned int timeout)
  493. {
  494. struct abx80x_priv *priv = watchdog_get_drvdata(wdog);
  495. u8 val = ABX8XX_WDT_WDS | timeout_bits(timeout);
  496. /*
  497. * Writing any timeout to the WDT register resets the watchdog timer.
  498. * Writing 0 disables it.
  499. */
  500. return i2c_smbus_write_byte_data(priv->client, ABX8XX_REG_WDT, val);
  501. }
  502. static int abx80x_wdog_set_timeout(struct watchdog_device *wdog,
  503. unsigned int new_timeout)
  504. {
  505. int err = 0;
  506. if (watchdog_hw_running(wdog))
  507. err = __abx80x_wdog_set_timeout(wdog, new_timeout);
  508. if (err == 0)
  509. wdog->timeout = new_timeout;
  510. return err;
  511. }
  512. static int abx80x_wdog_ping(struct watchdog_device *wdog)
  513. {
  514. return __abx80x_wdog_set_timeout(wdog, wdog->timeout);
  515. }
  516. static int abx80x_wdog_start(struct watchdog_device *wdog)
  517. {
  518. return __abx80x_wdog_set_timeout(wdog, wdog->timeout);
  519. }
  520. static int abx80x_wdog_stop(struct watchdog_device *wdog)
  521. {
  522. return __abx80x_wdog_set_timeout(wdog, 0);
  523. }
  524. static const struct watchdog_info abx80x_wdog_info = {
  525. .identity = "abx80x watchdog",
  526. .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
  527. };
  528. static const struct watchdog_ops abx80x_wdog_ops = {
  529. .owner = THIS_MODULE,
  530. .start = abx80x_wdog_start,
  531. .stop = abx80x_wdog_stop,
  532. .ping = abx80x_wdog_ping,
  533. .set_timeout = abx80x_wdog_set_timeout,
  534. };
  535. static int abx80x_setup_watchdog(struct abx80x_priv *priv)
  536. {
  537. priv->wdog.parent = &priv->client->dev;
  538. priv->wdog.ops = &abx80x_wdog_ops;
  539. priv->wdog.info = &abx80x_wdog_info;
  540. priv->wdog.min_timeout = 1;
  541. priv->wdog.max_timeout = ABX8XX_WDT_MAX_TIME;
  542. priv->wdog.timeout = ABX8XX_WDT_MAX_TIME;
  543. watchdog_set_drvdata(&priv->wdog, priv);
  544. return devm_watchdog_register_device(&priv->client->dev, &priv->wdog);
  545. }
  546. #else
  547. static int abx80x_setup_watchdog(struct abx80x_priv *priv)
  548. {
  549. return 0;
  550. }
  551. #endif
  552. static int abx80x_nvmem_xfer(struct abx80x_priv *priv, unsigned int offset,
  553. void *val, size_t bytes, bool write)
  554. {
  555. int ret;
  556. while (bytes) {
  557. u8 extram, reg, len, lower, upper;
  558. lower = FIELD_GET(NVMEM_ADDR_LOWER, offset);
  559. upper = FIELD_GET(NVMEM_ADDR_UPPER, offset);
  560. extram = FIELD_PREP(ABX8XX_EXTRAM_XADS, upper);
  561. reg = ABX8XX_SRAM_BASE + lower;
  562. len = min(lower + bytes, (size_t)ABX8XX_SRAM_WIN_SIZE) - lower;
  563. len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX);
  564. ret = i2c_smbus_write_byte_data(priv->client, ABX8XX_REG_EXTRAM,
  565. extram);
  566. if (ret)
  567. return ret;
  568. if (write) {
  569. ret = i2c_smbus_write_i2c_block_data(priv->client, reg,
  570. len, val);
  571. if (ret)
  572. return ret;
  573. } else {
  574. ret = i2c_smbus_read_i2c_block_data(priv->client, reg,
  575. len, val);
  576. if (ret <= 0)
  577. return ret ? ret : -EIO;
  578. len = ret;
  579. }
  580. offset += len;
  581. val += len;
  582. bytes -= len;
  583. }
  584. return 0;
  585. }
  586. static int abx80x_nvmem_read(void *priv, unsigned int offset, void *val,
  587. size_t bytes)
  588. {
  589. return abx80x_nvmem_xfer(priv, offset, val, bytes, false);
  590. }
  591. static int abx80x_nvmem_write(void *priv, unsigned int offset, void *val,
  592. size_t bytes)
  593. {
  594. return abx80x_nvmem_xfer(priv, offset, val, bytes, true);
  595. }
  596. static int abx80x_setup_nvmem(struct abx80x_priv *priv)
  597. {
  598. struct nvmem_config config = {
  599. .type = NVMEM_TYPE_BATTERY_BACKED,
  600. .reg_read = abx80x_nvmem_read,
  601. .reg_write = abx80x_nvmem_write,
  602. .size = ABX8XX_RAM_SIZE,
  603. .priv = priv,
  604. };
  605. return devm_rtc_nvmem_register(priv->rtc, &config);
  606. }
  607. static const struct i2c_device_id abx80x_id[] = {
  608. { "abx80x", ABX80X },
  609. { "ab0801", AB0801 },
  610. { "ab0803", AB0803 },
  611. { "ab0804", AB0804 },
  612. { "ab0805", AB0805 },
  613. { "ab1801", AB1801 },
  614. { "ab1803", AB1803 },
  615. { "ab1804", AB1804 },
  616. { "ab1805", AB1805 },
  617. { "rv1805", RV1805 },
  618. { }
  619. };
  620. MODULE_DEVICE_TABLE(i2c, abx80x_id);
  621. static int abx80x_probe(struct i2c_client *client)
  622. {
  623. struct device_node *np = client->dev.of_node;
  624. struct abx80x_priv *priv;
  625. int i, data, err, trickle_cfg = -EINVAL;
  626. char buf[7];
  627. const struct i2c_device_id *id = i2c_match_id(abx80x_id, client);
  628. unsigned int part = id->driver_data;
  629. unsigned int partnumber;
  630. unsigned int majrev, minrev;
  631. unsigned int lot;
  632. unsigned int wafer;
  633. unsigned int uid;
  634. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
  635. return -ENODEV;
  636. err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_ID0,
  637. sizeof(buf), buf);
  638. if (err < 0) {
  639. dev_err(&client->dev, "Unable to read partnumber\n");
  640. return -EIO;
  641. }
  642. partnumber = (buf[0] << 8) | buf[1];
  643. majrev = buf[2] >> 3;
  644. minrev = buf[2] & 0x7;
  645. lot = ((buf[4] & 0x80) << 2) | ((buf[6] & 0x80) << 1) | buf[3];
  646. uid = ((buf[4] & 0x7f) << 8) | buf[5];
  647. wafer = (buf[6] & 0x7c) >> 2;
  648. dev_info(&client->dev, "model %04x, revision %u.%u, lot %x, wafer %x, uid %x\n",
  649. partnumber, majrev, minrev, lot, wafer, uid);
  650. data = i2c_smbus_read_byte_data(client, ABX8XX_REG_CTRL1);
  651. if (data < 0) {
  652. dev_err(&client->dev, "Unable to read control register\n");
  653. return -EIO;
  654. }
  655. err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CTRL1,
  656. ((data & ~(ABX8XX_CTRL_12_24 |
  657. ABX8XX_CTRL_ARST)) |
  658. ABX8XX_CTRL_WRITE));
  659. if (err < 0) {
  660. dev_err(&client->dev, "Unable to write control register\n");
  661. return -EIO;
  662. }
  663. /* Configure RV1805 specifics */
  664. if (part == RV1805) {
  665. /*
  666. * Avoid accidentally entering test mode. This can happen
  667. * on the RV1805 in case the reserved bit 5 in control2
  668. * register is set. RV-1805-C3 datasheet indicates that
  669. * the bit should be cleared in section 11h - Control2.
  670. */
  671. data = i2c_smbus_read_byte_data(client, ABX8XX_REG_CTRL2);
  672. if (data < 0) {
  673. dev_err(&client->dev,
  674. "Unable to read control2 register\n");
  675. return -EIO;
  676. }
  677. err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CTRL2,
  678. data & ~ABX8XX_CTRL2_RSVD);
  679. if (err < 0) {
  680. dev_err(&client->dev,
  681. "Unable to write control2 register\n");
  682. return -EIO;
  683. }
  684. /*
  685. * Avoid extra power leakage. The RV1805 uses smaller
  686. * 10pin package and the EXTI input is not present.
  687. * Disable it to avoid leakage.
  688. */
  689. data = i2c_smbus_read_byte_data(client, ABX8XX_REG_OUT_CTRL);
  690. if (data < 0) {
  691. dev_err(&client->dev,
  692. "Unable to read output control register\n");
  693. return -EIO;
  694. }
  695. /*
  696. * Write the configuration key register to enable access to
  697. * the config2 register
  698. */
  699. if (abx80x_write_config_key(client, ABX8XX_CFG_KEY_MISC) < 0)
  700. return -EIO;
  701. err = i2c_smbus_write_byte_data(client, ABX8XX_REG_OUT_CTRL,
  702. data | ABX8XX_OUT_CTRL_EXDS);
  703. if (err < 0) {
  704. dev_err(&client->dev,
  705. "Unable to write output control register\n");
  706. return -EIO;
  707. }
  708. }
  709. /* part autodetection */
  710. if (part == ABX80X) {
  711. for (i = 0; abx80x_caps[i].pn; i++)
  712. if (partnumber == abx80x_caps[i].pn)
  713. break;
  714. if (abx80x_caps[i].pn == 0) {
  715. dev_err(&client->dev, "Unknown part: %04x\n",
  716. partnumber);
  717. return -EINVAL;
  718. }
  719. part = i;
  720. }
  721. if (partnumber != abx80x_caps[part].pn) {
  722. dev_err(&client->dev, "partnumber mismatch %04x != %04x\n",
  723. partnumber, abx80x_caps[part].pn);
  724. return -EINVAL;
  725. }
  726. if (np && abx80x_caps[part].has_tc)
  727. trickle_cfg = abx80x_dt_trickle_cfg(client);
  728. if (trickle_cfg > 0) {
  729. dev_info(&client->dev, "Enabling trickle charger: %02x\n",
  730. trickle_cfg);
  731. abx80x_enable_trickle_charger(client, trickle_cfg);
  732. }
  733. err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CD_TIMER_CTL,
  734. BIT(2));
  735. if (err)
  736. return err;
  737. priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
  738. if (priv == NULL)
  739. return -ENOMEM;
  740. priv->rtc = devm_rtc_allocate_device(&client->dev);
  741. if (IS_ERR(priv->rtc))
  742. return PTR_ERR(priv->rtc);
  743. priv->rtc->ops = &abx80x_rtc_ops;
  744. priv->client = client;
  745. i2c_set_clientdata(client, priv);
  746. if (abx80x_caps[part].has_wdog) {
  747. err = abx80x_setup_watchdog(priv);
  748. if (err)
  749. return err;
  750. }
  751. err = abx80x_setup_nvmem(priv);
  752. if (err)
  753. return err;
  754. if (client->irq > 0) {
  755. dev_info(&client->dev, "IRQ %d supplied\n", client->irq);
  756. err = devm_request_threaded_irq(&client->dev, client->irq, NULL,
  757. abx80x_handle_irq,
  758. IRQF_SHARED | IRQF_ONESHOT,
  759. "abx8xx",
  760. client);
  761. if (err) {
  762. dev_err(&client->dev, "unable to request IRQ, alarms disabled\n");
  763. client->irq = 0;
  764. }
  765. }
  766. err = rtc_add_group(priv->rtc, &rtc_calib_attr_group);
  767. if (err) {
  768. dev_err(&client->dev, "Failed to create sysfs group: %d\n",
  769. err);
  770. return err;
  771. }
  772. return devm_rtc_register_device(priv->rtc);
  773. }
  774. #ifdef CONFIG_OF
  775. static const struct of_device_id abx80x_of_match[] = {
  776. {
  777. .compatible = "abracon,abx80x",
  778. .data = (void *)ABX80X
  779. },
  780. {
  781. .compatible = "abracon,ab0801",
  782. .data = (void *)AB0801
  783. },
  784. {
  785. .compatible = "abracon,ab0803",
  786. .data = (void *)AB0803
  787. },
  788. {
  789. .compatible = "abracon,ab0804",
  790. .data = (void *)AB0804
  791. },
  792. {
  793. .compatible = "abracon,ab0805",
  794. .data = (void *)AB0805
  795. },
  796. {
  797. .compatible = "abracon,ab1801",
  798. .data = (void *)AB1801
  799. },
  800. {
  801. .compatible = "abracon,ab1803",
  802. .data = (void *)AB1803
  803. },
  804. {
  805. .compatible = "abracon,ab1804",
  806. .data = (void *)AB1804
  807. },
  808. {
  809. .compatible = "abracon,ab1805",
  810. .data = (void *)AB1805
  811. },
  812. {
  813. .compatible = "microcrystal,rv1805",
  814. .data = (void *)RV1805
  815. },
  816. { }
  817. };
  818. MODULE_DEVICE_TABLE(of, abx80x_of_match);
  819. #endif
  820. static struct i2c_driver abx80x_driver = {
  821. .driver = {
  822. .name = "rtc-abx80x",
  823. .of_match_table = of_match_ptr(abx80x_of_match),
  824. },
  825. .probe = abx80x_probe,
  826. .id_table = abx80x_id,
  827. };
  828. module_i2c_driver(abx80x_driver);
  829. MODULE_AUTHOR("Philippe De Muyter <phdm@macqel.be>");
  830. MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
  831. MODULE_DESCRIPTION("Abracon ABX80X RTC driver");
  832. MODULE_LICENSE("GPL v2");