atp870u.c 59 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 1997 Wu Ching Chen
  4. * 2.1.x update (C) 1998 Krzysztof G. Baranowski
  5. * 2.5.x update (C) 2002 Red Hat
  6. * 2.6.x update (C) 2004 Red Hat
  7. *
  8. * Marcelo Tosatti <marcelo@conectiva.com.br> : SMP fixes
  9. *
  10. * Wu Ching Chen : NULL pointer fixes 2000/06/02
  11. * support atp876 chip
  12. * enable 32 bit fifo transfer
  13. * support cdrom & remove device run ultra speed
  14. * fix disconnect bug 2000/12/21
  15. * support atp880 chip lvd u160 2001/05/15
  16. * fix prd table bug 2001/09/12 (7.1)
  17. *
  18. * atp885 support add by ACARD Hao Ping Lian 2005/01/05
  19. */
  20. #include <linux/module.h>
  21. #include <linux/init.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/kernel.h>
  24. #include <linux/types.h>
  25. #include <linux/string.h>
  26. #include <linux/ioport.h>
  27. #include <linux/delay.h>
  28. #include <linux/proc_fs.h>
  29. #include <linux/spinlock.h>
  30. #include <linux/pci.h>
  31. #include <linux/blkdev.h>
  32. #include <linux/dma-mapping.h>
  33. #include <linux/slab.h>
  34. #include <asm/io.h>
  35. #include <scsi/scsi.h>
  36. #include <scsi/scsi_cmnd.h>
  37. #include <scsi/scsi_device.h>
  38. #include <scsi/scsi_host.h>
  39. #include "atp870u.h"
  40. static const struct scsi_host_template atp870u_template;
  41. static void send_s870(struct atp_unit *dev,unsigned char c);
  42. static void atp_is(struct atp_unit *dev, unsigned char c, bool wide_chip,
  43. unsigned char lvdmode);
  44. static inline void atp_writeb_base(struct atp_unit *atp, u8 reg, u8 val)
  45. {
  46. outb(val, atp->baseport + reg);
  47. }
  48. static inline void atp_writew_base(struct atp_unit *atp, u8 reg, u16 val)
  49. {
  50. outw(val, atp->baseport + reg);
  51. }
  52. static inline void atp_writeb_io(struct atp_unit *atp, u8 channel, u8 reg, u8 val)
  53. {
  54. outb(val, atp->ioport[channel] + reg);
  55. }
  56. static inline void atp_writew_io(struct atp_unit *atp, u8 channel, u8 reg, u16 val)
  57. {
  58. outw(val, atp->ioport[channel] + reg);
  59. }
  60. static inline void atp_writeb_pci(struct atp_unit *atp, u8 channel, u8 reg, u8 val)
  61. {
  62. outb(val, atp->pciport[channel] + reg);
  63. }
  64. static inline void atp_writel_pci(struct atp_unit *atp, u8 channel, u8 reg, u32 val)
  65. {
  66. outl(val, atp->pciport[channel] + reg);
  67. }
  68. static inline u8 atp_readb_base(struct atp_unit *atp, u8 reg)
  69. {
  70. return inb(atp->baseport + reg);
  71. }
  72. static inline u16 atp_readw_base(struct atp_unit *atp, u8 reg)
  73. {
  74. return inw(atp->baseport + reg);
  75. }
  76. static inline u32 atp_readl_base(struct atp_unit *atp, u8 reg)
  77. {
  78. return inl(atp->baseport + reg);
  79. }
  80. static inline u8 atp_readb_io(struct atp_unit *atp, u8 channel, u8 reg)
  81. {
  82. return inb(atp->ioport[channel] + reg);
  83. }
  84. static inline u16 atp_readw_io(struct atp_unit *atp, u8 channel, u8 reg)
  85. {
  86. return inw(atp->ioport[channel] + reg);
  87. }
  88. static inline u8 atp_readb_pci(struct atp_unit *atp, u8 channel, u8 reg)
  89. {
  90. return inb(atp->pciport[channel] + reg);
  91. }
  92. static inline bool is880(struct atp_unit *atp)
  93. {
  94. return atp->pdev->device == ATP880_DEVID1 ||
  95. atp->pdev->device == ATP880_DEVID2;
  96. }
  97. static inline bool is885(struct atp_unit *atp)
  98. {
  99. return atp->pdev->device == ATP885_DEVID;
  100. }
  101. static irqreturn_t atp870u_intr_handle(int irq, void *dev_id)
  102. {
  103. unsigned long flags;
  104. unsigned short int id;
  105. unsigned char i, j, c, target_id, lun,cmdp;
  106. unsigned char *prd;
  107. struct scsi_cmnd *workreq;
  108. unsigned long adrcnt, k;
  109. #ifdef ED_DBGP
  110. unsigned long l;
  111. #endif
  112. struct Scsi_Host *host = dev_id;
  113. struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
  114. for (c = 0; c < 2; c++) {
  115. j = atp_readb_io(dev, c, 0x1f);
  116. if ((j & 0x80) != 0)
  117. break;
  118. dev->in_int[c] = 0;
  119. }
  120. if ((j & 0x80) == 0)
  121. return IRQ_NONE;
  122. #ifdef ED_DBGP
  123. printk("atp870u_intr_handle enter\n");
  124. #endif
  125. dev->in_int[c] = 1;
  126. cmdp = atp_readb_io(dev, c, 0x10);
  127. if (dev->working[c] != 0) {
  128. if (is885(dev)) {
  129. if ((atp_readb_io(dev, c, 0x16) & 0x80) == 0)
  130. atp_writeb_io(dev, c, 0x16,
  131. (atp_readb_io(dev, c, 0x16) | 0x80));
  132. }
  133. if ((atp_readb_pci(dev, c, 0x00) & 0x08) != 0)
  134. {
  135. for (k=0; k < 1000; k++) {
  136. if ((atp_readb_pci(dev, c, 2) & 0x08) == 0)
  137. break;
  138. if ((atp_readb_pci(dev, c, 2) & 0x01) == 0)
  139. break;
  140. }
  141. }
  142. atp_writeb_pci(dev, c, 0, 0x00);
  143. i = atp_readb_io(dev, c, 0x17);
  144. if (is885(dev))
  145. atp_writeb_pci(dev, c, 2, 0x06);
  146. target_id = atp_readb_io(dev, c, 0x15);
  147. /*
  148. * Remap wide devices onto id numbers
  149. */
  150. if ((target_id & 0x40) != 0) {
  151. target_id = (target_id & 0x07) | 0x08;
  152. } else {
  153. target_id &= 0x07;
  154. }
  155. if ((j & 0x40) != 0) {
  156. if (dev->last_cmd[c] == 0xff) {
  157. dev->last_cmd[c] = target_id;
  158. }
  159. dev->last_cmd[c] |= 0x40;
  160. }
  161. if (is885(dev))
  162. dev->r1f[c][target_id] |= j;
  163. #ifdef ED_DBGP
  164. printk("atp870u_intr_handle status = %x\n",i);
  165. #endif
  166. if (i == 0x85) {
  167. if ((dev->last_cmd[c] & 0xf0) != 0x40) {
  168. dev->last_cmd[c] = 0xff;
  169. }
  170. if (is885(dev)) {
  171. adrcnt = 0;
  172. ((unsigned char *) &adrcnt)[2] =
  173. atp_readb_io(dev, c, 0x12);
  174. ((unsigned char *) &adrcnt)[1] =
  175. atp_readb_io(dev, c, 0x13);
  176. ((unsigned char *) &adrcnt)[0] =
  177. atp_readb_io(dev, c, 0x14);
  178. if (dev->id[c][target_id].last_len != adrcnt) {
  179. k = dev->id[c][target_id].last_len;
  180. k -= adrcnt;
  181. dev->id[c][target_id].tran_len = k;
  182. dev->id[c][target_id].last_len = adrcnt;
  183. }
  184. #ifdef ED_DBGP
  185. printk("dev->id[c][target_id].last_len = %d "
  186. "dev->id[c][target_id].tran_len = %d\n",
  187. dev->id[c][target_id].last_len,
  188. dev->id[c][target_id].tran_len);
  189. #endif
  190. }
  191. /*
  192. * Flip wide
  193. */
  194. if (dev->wide_id[c] != 0) {
  195. atp_writeb_io(dev, c, 0x1b, 0x01);
  196. while ((atp_readb_io(dev, c, 0x1b) & 0x01) != 0x01)
  197. atp_writeb_io(dev, c, 0x1b, 0x01);
  198. }
  199. /*
  200. * Issue more commands
  201. */
  202. spin_lock_irqsave(dev->host->host_lock, flags);
  203. if (((dev->quhd[c] != dev->quend[c]) ||
  204. (dev->last_cmd[c] != 0xff)) &&
  205. (dev->in_snd[c] == 0)) {
  206. #ifdef ED_DBGP
  207. printk("Call sent_s870\n");
  208. #endif
  209. send_s870(dev,c);
  210. }
  211. spin_unlock_irqrestore(dev->host->host_lock, flags);
  212. /*
  213. * Done
  214. */
  215. dev->in_int[c] = 0;
  216. #ifdef ED_DBGP
  217. printk("Status 0x85 return\n");
  218. #endif
  219. return IRQ_HANDLED;
  220. }
  221. if (i == 0x40) {
  222. dev->last_cmd[c] |= 0x40;
  223. dev->in_int[c] = 0;
  224. return IRQ_HANDLED;
  225. }
  226. if (i == 0x21) {
  227. if ((dev->last_cmd[c] & 0xf0) != 0x40) {
  228. dev->last_cmd[c] = 0xff;
  229. }
  230. adrcnt = 0;
  231. ((unsigned char *) &adrcnt)[2] =
  232. atp_readb_io(dev, c, 0x12);
  233. ((unsigned char *) &adrcnt)[1] =
  234. atp_readb_io(dev, c, 0x13);
  235. ((unsigned char *) &adrcnt)[0] =
  236. atp_readb_io(dev, c, 0x14);
  237. k = dev->id[c][target_id].last_len;
  238. k -= adrcnt;
  239. dev->id[c][target_id].tran_len = k;
  240. dev->id[c][target_id].last_len = adrcnt;
  241. atp_writeb_io(dev, c, 0x10, 0x41);
  242. atp_writeb_io(dev, c, 0x18, 0x08);
  243. dev->in_int[c] = 0;
  244. return IRQ_HANDLED;
  245. }
  246. if (is885(dev)) {
  247. if ((i == 0x4c) || (i == 0x4d) || (i == 0x8c) || (i == 0x8d)) {
  248. if ((i == 0x4c) || (i == 0x8c))
  249. i=0x48;
  250. else
  251. i=0x49;
  252. }
  253. }
  254. if ((i == 0x80) || (i == 0x8f)) {
  255. #ifdef ED_DBGP
  256. printk(KERN_DEBUG "Device reselect\n");
  257. #endif
  258. lun = 0;
  259. if (cmdp == 0x44 || i == 0x80)
  260. lun = atp_readb_io(dev, c, 0x1d) & 0x07;
  261. else {
  262. if ((dev->last_cmd[c] & 0xf0) != 0x40) {
  263. dev->last_cmd[c] = 0xff;
  264. }
  265. if (cmdp == 0x41) {
  266. #ifdef ED_DBGP
  267. printk("cmdp = 0x41\n");
  268. #endif
  269. adrcnt = 0;
  270. ((unsigned char *) &adrcnt)[2] =
  271. atp_readb_io(dev, c, 0x12);
  272. ((unsigned char *) &adrcnt)[1] =
  273. atp_readb_io(dev, c, 0x13);
  274. ((unsigned char *) &adrcnt)[0] =
  275. atp_readb_io(dev, c, 0x14);
  276. k = dev->id[c][target_id].last_len;
  277. k -= adrcnt;
  278. dev->id[c][target_id].tran_len = k;
  279. dev->id[c][target_id].last_len = adrcnt;
  280. atp_writeb_io(dev, c, 0x18, 0x08);
  281. dev->in_int[c] = 0;
  282. return IRQ_HANDLED;
  283. } else {
  284. #ifdef ED_DBGP
  285. printk("cmdp != 0x41\n");
  286. #endif
  287. atp_writeb_io(dev, c, 0x10, 0x46);
  288. dev->id[c][target_id].dirct = 0x00;
  289. atp_writeb_io(dev, c, 0x12, 0x00);
  290. atp_writeb_io(dev, c, 0x13, 0x00);
  291. atp_writeb_io(dev, c, 0x14, 0x00);
  292. atp_writeb_io(dev, c, 0x18, 0x08);
  293. dev->in_int[c] = 0;
  294. return IRQ_HANDLED;
  295. }
  296. }
  297. if (dev->last_cmd[c] != 0xff) {
  298. dev->last_cmd[c] |= 0x40;
  299. }
  300. if (is885(dev)) {
  301. j = atp_readb_base(dev, 0x29) & 0xfe;
  302. atp_writeb_base(dev, 0x29, j);
  303. } else
  304. atp_writeb_io(dev, c, 0x10, 0x45);
  305. target_id = atp_readb_io(dev, c, 0x16);
  306. /*
  307. * Remap wide identifiers
  308. */
  309. if ((target_id & 0x10) != 0) {
  310. target_id = (target_id & 0x07) | 0x08;
  311. } else {
  312. target_id &= 0x07;
  313. }
  314. if (is885(dev))
  315. atp_writeb_io(dev, c, 0x10, 0x45);
  316. workreq = dev->id[c][target_id].curr_req;
  317. #ifdef ED_DBGP
  318. scmd_printk(KERN_DEBUG, workreq, "CDB");
  319. for (l = 0; l < workreq->cmd_len; l++)
  320. printk(KERN_DEBUG " %x",workreq->cmnd[l]);
  321. printk("\n");
  322. #endif
  323. atp_writeb_io(dev, c, 0x0f, lun);
  324. atp_writeb_io(dev, c, 0x11, dev->id[c][target_id].devsp);
  325. adrcnt = dev->id[c][target_id].tran_len;
  326. k = dev->id[c][target_id].last_len;
  327. atp_writeb_io(dev, c, 0x12, ((unsigned char *) &k)[2]);
  328. atp_writeb_io(dev, c, 0x13, ((unsigned char *) &k)[1]);
  329. atp_writeb_io(dev, c, 0x14, ((unsigned char *) &k)[0]);
  330. #ifdef ED_DBGP
  331. printk("k %x, k[0] 0x%x k[1] 0x%x k[2] 0x%x\n", k,
  332. atp_readb_io(dev, c, 0x14),
  333. atp_readb_io(dev, c, 0x13),
  334. atp_readb_io(dev, c, 0x12));
  335. #endif
  336. /* Remap wide */
  337. j = target_id;
  338. if (target_id > 7) {
  339. j = (j & 0x07) | 0x40;
  340. }
  341. /* Add direction */
  342. j |= dev->id[c][target_id].dirct;
  343. atp_writeb_io(dev, c, 0x15, j);
  344. atp_writeb_io(dev, c, 0x16, 0x80);
  345. /* enable 32 bit fifo transfer */
  346. if (is885(dev)) {
  347. i = atp_readb_pci(dev, c, 1) & 0xf3;
  348. //j=workreq->cmnd[0];
  349. if ((workreq->cmnd[0] == READ_6) ||
  350. (workreq->cmnd[0] == READ_10) ||
  351. (workreq->cmnd[0] == WRITE_6) ||
  352. (workreq->cmnd[0] == WRITE_10)) {
  353. i |= 0x0c;
  354. }
  355. atp_writeb_pci(dev, c, 1, i);
  356. } else if (is880(dev)) {
  357. if ((workreq->cmnd[0] == READ_6) ||
  358. (workreq->cmnd[0] == READ_10) ||
  359. (workreq->cmnd[0] == WRITE_6) ||
  360. (workreq->cmnd[0] == WRITE_10))
  361. atp_writeb_base(dev, 0x3b,
  362. (atp_readb_base(dev, 0x3b) & 0x3f) | 0xc0);
  363. else
  364. atp_writeb_base(dev, 0x3b,
  365. atp_readb_base(dev, 0x3b) & 0x3f);
  366. } else {
  367. if ((workreq->cmnd[0] == READ_6) ||
  368. (workreq->cmnd[0] == READ_10) ||
  369. (workreq->cmnd[0] == WRITE_6) ||
  370. (workreq->cmnd[0] == WRITE_10))
  371. atp_writeb_base(dev, 0x3a,
  372. (atp_readb_base(dev, 0x3a) & 0xf3) | 0x08);
  373. else
  374. atp_writeb_base(dev, 0x3a,
  375. atp_readb_base(dev, 0x3a) & 0xf3);
  376. }
  377. j = 0;
  378. id = 1;
  379. id = id << target_id;
  380. /*
  381. * Is this a wide device
  382. */
  383. if ((id & dev->wide_id[c]) != 0) {
  384. j |= 0x01;
  385. }
  386. atp_writeb_io(dev, c, 0x1b, j);
  387. while ((atp_readb_io(dev, c, 0x1b) & 0x01) != j)
  388. atp_writeb_io(dev, c, 0x1b, j);
  389. if (dev->id[c][target_id].last_len == 0) {
  390. atp_writeb_io(dev, c, 0x18, 0x08);
  391. dev->in_int[c] = 0;
  392. #ifdef ED_DBGP
  393. printk("dev->id[c][target_id].last_len = 0\n");
  394. #endif
  395. return IRQ_HANDLED;
  396. }
  397. #ifdef ED_DBGP
  398. printk("target_id = %d adrcnt = %d\n",target_id,adrcnt);
  399. #endif
  400. prd = dev->id[c][target_id].prd_pos;
  401. while (adrcnt != 0) {
  402. id = ((unsigned short int *)prd)[2];
  403. if (id == 0) {
  404. k = 0x10000;
  405. } else {
  406. k = id;
  407. }
  408. if (k > adrcnt) {
  409. ((unsigned short int *)prd)[2] =
  410. (unsigned short int)(k - adrcnt);
  411. ((unsigned long *)prd)[0] += adrcnt;
  412. adrcnt = 0;
  413. dev->id[c][target_id].prd_pos = prd;
  414. } else {
  415. adrcnt -= k;
  416. dev->id[c][target_id].prdaddr += 0x08;
  417. prd += 0x08;
  418. if (adrcnt == 0) {
  419. dev->id[c][target_id].prd_pos = prd;
  420. }
  421. }
  422. }
  423. atp_writel_pci(dev, c, 0x04, dev->id[c][target_id].prdaddr);
  424. #ifdef ED_DBGP
  425. printk("dev->id[%d][%d].prdaddr 0x%8x\n",
  426. c, target_id, dev->id[c][target_id].prdaddr);
  427. #endif
  428. if (!is885(dev)) {
  429. atp_writeb_pci(dev, c, 2, 0x06);
  430. atp_writeb_pci(dev, c, 2, 0x00);
  431. }
  432. /*
  433. * Check transfer direction
  434. */
  435. if (dev->id[c][target_id].dirct != 0) {
  436. atp_writeb_io(dev, c, 0x18, 0x08);
  437. atp_writeb_pci(dev, c, 0, 0x01);
  438. dev->in_int[c] = 0;
  439. #ifdef ED_DBGP
  440. printk("status 0x80 return dirct != 0\n");
  441. #endif
  442. return IRQ_HANDLED;
  443. }
  444. atp_writeb_io(dev, c, 0x18, 0x08);
  445. atp_writeb_pci(dev, c, 0, 0x09);
  446. dev->in_int[c] = 0;
  447. #ifdef ED_DBGP
  448. printk("status 0x80 return dirct = 0\n");
  449. #endif
  450. return IRQ_HANDLED;
  451. }
  452. /*
  453. * Current scsi request on this target
  454. */
  455. workreq = dev->id[c][target_id].curr_req;
  456. if (i == 0x42 || i == 0x16) {
  457. if ((dev->last_cmd[c] & 0xf0) != 0x40) {
  458. dev->last_cmd[c] = 0xff;
  459. }
  460. if (i == 0x16) {
  461. workreq->result = atp_readb_io(dev, c, 0x0f);
  462. if (((dev->r1f[c][target_id] & 0x10) != 0) && is885(dev)) {
  463. printk(KERN_WARNING "AEC67162 CRC ERROR !\n");
  464. workreq->result = SAM_STAT_CHECK_CONDITION;
  465. }
  466. } else
  467. workreq->result = SAM_STAT_CHECK_CONDITION;
  468. if (is885(dev)) {
  469. j = atp_readb_base(dev, 0x29) | 0x01;
  470. atp_writeb_base(dev, 0x29, j);
  471. }
  472. /*
  473. * Complete the command
  474. */
  475. scsi_dma_unmap(workreq);
  476. spin_lock_irqsave(dev->host->host_lock, flags);
  477. scsi_done(workreq);
  478. #ifdef ED_DBGP
  479. printk("workreq->scsi_done\n");
  480. #endif
  481. /*
  482. * Clear it off the queue
  483. */
  484. dev->id[c][target_id].curr_req = NULL;
  485. dev->working[c]--;
  486. spin_unlock_irqrestore(dev->host->host_lock, flags);
  487. /*
  488. * Take it back wide
  489. */
  490. if (dev->wide_id[c] != 0) {
  491. atp_writeb_io(dev, c, 0x1b, 0x01);
  492. while ((atp_readb_io(dev, c, 0x1b) & 0x01) != 0x01)
  493. atp_writeb_io(dev, c, 0x1b, 0x01);
  494. }
  495. /*
  496. * If there is stuff to send and nothing going then send it
  497. */
  498. spin_lock_irqsave(dev->host->host_lock, flags);
  499. if (((dev->last_cmd[c] != 0xff) ||
  500. (dev->quhd[c] != dev->quend[c])) &&
  501. (dev->in_snd[c] == 0)) {
  502. #ifdef ED_DBGP
  503. printk("Call sent_s870(scsi_done)\n");
  504. #endif
  505. send_s870(dev,c);
  506. }
  507. spin_unlock_irqrestore(dev->host->host_lock, flags);
  508. dev->in_int[c] = 0;
  509. return IRQ_HANDLED;
  510. }
  511. if ((dev->last_cmd[c] & 0xf0) != 0x40) {
  512. dev->last_cmd[c] = 0xff;
  513. }
  514. if (i == 0x4f) {
  515. i = 0x89;
  516. }
  517. i &= 0x0f;
  518. if (i == 0x09) {
  519. atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr);
  520. atp_writeb_pci(dev, c, 2, 0x06);
  521. atp_writeb_pci(dev, c, 2, 0x00);
  522. atp_writeb_io(dev, c, 0x10, 0x41);
  523. if (is885(dev)) {
  524. k = dev->id[c][target_id].last_len;
  525. atp_writeb_io(dev, c, 0x12,
  526. ((unsigned char *) (&k))[2]);
  527. atp_writeb_io(dev, c, 0x13,
  528. ((unsigned char *) (&k))[1]);
  529. atp_writeb_io(dev, c, 0x14,
  530. ((unsigned char *) (&k))[0]);
  531. dev->id[c][target_id].dirct = 0x00;
  532. } else {
  533. dev->id[c][target_id].dirct = 0x00;
  534. }
  535. atp_writeb_io(dev, c, 0x18, 0x08);
  536. atp_writeb_pci(dev, c, 0, 0x09);
  537. dev->in_int[c] = 0;
  538. return IRQ_HANDLED;
  539. }
  540. if (i == 0x08) {
  541. atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr);
  542. atp_writeb_pci(dev, c, 2, 0x06);
  543. atp_writeb_pci(dev, c, 2, 0x00);
  544. atp_writeb_io(dev, c, 0x10, 0x41);
  545. if (is885(dev)) {
  546. k = dev->id[c][target_id].last_len;
  547. atp_writeb_io(dev, c, 0x12,
  548. ((unsigned char *) (&k))[2]);
  549. atp_writeb_io(dev, c, 0x13,
  550. ((unsigned char *) (&k))[1]);
  551. atp_writeb_io(dev, c, 0x14,
  552. ((unsigned char *) (&k))[0]);
  553. }
  554. atp_writeb_io(dev, c, 0x15,
  555. atp_readb_io(dev, c, 0x15) | 0x20);
  556. dev->id[c][target_id].dirct = 0x20;
  557. atp_writeb_io(dev, c, 0x18, 0x08);
  558. atp_writeb_pci(dev, c, 0, 0x01);
  559. dev->in_int[c] = 0;
  560. return IRQ_HANDLED;
  561. }
  562. if (i == 0x0a)
  563. atp_writeb_io(dev, c, 0x10, 0x30);
  564. else
  565. atp_writeb_io(dev, c, 0x10, 0x46);
  566. dev->id[c][target_id].dirct = 0x00;
  567. atp_writeb_io(dev, c, 0x12, 0x00);
  568. atp_writeb_io(dev, c, 0x13, 0x00);
  569. atp_writeb_io(dev, c, 0x14, 0x00);
  570. atp_writeb_io(dev, c, 0x18, 0x08);
  571. }
  572. dev->in_int[c] = 0;
  573. return IRQ_HANDLED;
  574. }
  575. /**
  576. * atp870u_queuecommand_lck - Queue SCSI command
  577. * @req_p: request block
  578. *
  579. * Queue a command to the ATP queue. Called with the host lock held.
  580. */
  581. static int atp870u_queuecommand_lck(struct scsi_cmnd *req_p)
  582. {
  583. void (*done)(struct scsi_cmnd *) = scsi_done;
  584. unsigned char c;
  585. unsigned int m;
  586. struct atp_unit *dev;
  587. struct Scsi_Host *host;
  588. c = scmd_channel(req_p);
  589. req_p->sense_buffer[0]=0;
  590. scsi_set_resid(req_p, 0);
  591. if (scmd_channel(req_p) > 1) {
  592. req_p->result = DID_BAD_TARGET << 16;
  593. done(req_p);
  594. #ifdef ED_DBGP
  595. printk("atp870u_queuecommand : req_p->device->channel > 1\n");
  596. #endif
  597. return 0;
  598. }
  599. host = req_p->device->host;
  600. dev = (struct atp_unit *)&host->hostdata;
  601. m = 1;
  602. m = m << scmd_id(req_p);
  603. /*
  604. * Fake a timeout for missing targets
  605. */
  606. if ((m & dev->active_id[c]) == 0) {
  607. req_p->result = DID_BAD_TARGET << 16;
  608. done(req_p);
  609. return 0;
  610. }
  611. /*
  612. * Count new command
  613. */
  614. dev->quend[c]++;
  615. if (dev->quend[c] >= qcnt) {
  616. dev->quend[c] = 0;
  617. }
  618. /*
  619. * Check queue state
  620. */
  621. if (dev->quhd[c] == dev->quend[c]) {
  622. if (dev->quend[c] == 0) {
  623. dev->quend[c] = qcnt;
  624. }
  625. #ifdef ED_DBGP
  626. printk("atp870u_queuecommand : dev->quhd[c] == dev->quend[c]\n");
  627. #endif
  628. dev->quend[c]--;
  629. req_p->result = DID_BUS_BUSY << 16;
  630. done(req_p);
  631. return 0;
  632. }
  633. dev->quereq[c][dev->quend[c]] = req_p;
  634. #ifdef ED_DBGP
  635. printk("dev->ioport[c] = %x atp_readb_io(dev, c, 0x1c) = %x "
  636. "dev->in_int[%d] = %d dev->in_snd[%d] = %d\n",
  637. dev->ioport[c], atp_readb_io(dev, c, 0x1c), c,
  638. dev->in_int[c],c,dev->in_snd[c]);
  639. #endif
  640. if ((atp_readb_io(dev, c, 0x1c) == 0) &&
  641. (dev->in_int[c] == 0) &&
  642. (dev->in_snd[c] == 0)) {
  643. #ifdef ED_DBGP
  644. printk("Call sent_s870(atp870u_queuecommand)\n");
  645. #endif
  646. send_s870(dev,c);
  647. }
  648. #ifdef ED_DBGP
  649. printk("atp870u_queuecommand : exit\n");
  650. #endif
  651. return 0;
  652. }
  653. static DEF_SCSI_QCMD(atp870u_queuecommand)
  654. /*
  655. * send_s870 - send a command to the controller
  656. *
  657. * On entry there is work queued to be done. We move some of that work to the
  658. * controller itself.
  659. *
  660. * Caller holds the host lock.
  661. */
  662. static void send_s870(struct atp_unit *dev, unsigned char c)
  663. {
  664. struct scsi_cmnd *workreq = NULL;
  665. unsigned int i;//,k;
  666. unsigned char j, target_id;
  667. unsigned char *prd;
  668. unsigned short int w;
  669. unsigned long l, bttl = 0;
  670. unsigned long sg_count;
  671. if (dev->in_snd[c] != 0) {
  672. #ifdef ED_DBGP
  673. printk("cmnd in_snd\n");
  674. #endif
  675. return;
  676. }
  677. #ifdef ED_DBGP
  678. printk("Sent_s870 enter\n");
  679. #endif
  680. dev->in_snd[c] = 1;
  681. if ((dev->last_cmd[c] != 0xff) && ((dev->last_cmd[c] & 0x40) != 0)) {
  682. dev->last_cmd[c] &= 0x0f;
  683. workreq = dev->id[c][dev->last_cmd[c]].curr_req;
  684. if (!workreq) {
  685. dev->last_cmd[c] = 0xff;
  686. if (dev->quhd[c] == dev->quend[c]) {
  687. dev->in_snd[c] = 0;
  688. return;
  689. }
  690. }
  691. }
  692. if (!workreq) {
  693. if ((dev->last_cmd[c] != 0xff) && (dev->working[c] != 0)) {
  694. dev->in_snd[c] = 0;
  695. return;
  696. }
  697. dev->working[c]++;
  698. j = dev->quhd[c];
  699. dev->quhd[c]++;
  700. if (dev->quhd[c] >= qcnt)
  701. dev->quhd[c] = 0;
  702. workreq = dev->quereq[c][dev->quhd[c]];
  703. if (dev->id[c][scmd_id(workreq)].curr_req != NULL) {
  704. dev->quhd[c] = j;
  705. dev->working[c]--;
  706. dev->in_snd[c] = 0;
  707. return;
  708. }
  709. dev->id[c][scmd_id(workreq)].curr_req = workreq;
  710. dev->last_cmd[c] = scmd_id(workreq);
  711. }
  712. if ((atp_readb_io(dev, c, 0x1f) & 0xb0) != 0 ||
  713. atp_readb_io(dev, c, 0x1c) != 0) {
  714. #ifdef ED_DBGP
  715. printk("Abort to Send\n");
  716. #endif
  717. dev->last_cmd[c] |= 0x40;
  718. dev->in_snd[c] = 0;
  719. return;
  720. }
  721. #ifdef ED_DBGP
  722. printk("OK to Send\n");
  723. scmd_printk(KERN_DEBUG, workreq, "CDB");
  724. for(i=0;i<workreq->cmd_len;i++) {
  725. printk(" %x",workreq->cmnd[i]);
  726. }
  727. printk("\n");
  728. #endif
  729. l = scsi_bufflen(workreq);
  730. if (is885(dev)) {
  731. j = atp_readb_base(dev, 0x29) & 0xfe;
  732. atp_writeb_base(dev, 0x29, j);
  733. dev->r1f[c][scmd_id(workreq)] = 0;
  734. }
  735. if (workreq->cmnd[0] == READ_CAPACITY) {
  736. if (l > 8)
  737. l = 8;
  738. }
  739. if (workreq->cmnd[0] == TEST_UNIT_READY) {
  740. l = 0;
  741. }
  742. j = 0;
  743. target_id = scmd_id(workreq);
  744. /*
  745. * Wide ?
  746. */
  747. w = 1;
  748. w = w << target_id;
  749. if ((w & dev->wide_id[c]) != 0) {
  750. j |= 0x01;
  751. }
  752. atp_writeb_io(dev, c, 0x1b, j);
  753. while ((atp_readb_io(dev, c, 0x1b) & 0x01) != j) {
  754. atp_writeb_pci(dev, c, 0x1b, j);
  755. #ifdef ED_DBGP
  756. printk("send_s870 while loop 1\n");
  757. #endif
  758. }
  759. /*
  760. * Write the command
  761. */
  762. atp_writeb_io(dev, c, 0x00, workreq->cmd_len);
  763. atp_writeb_io(dev, c, 0x01, 0x2c);
  764. if (is885(dev))
  765. atp_writeb_io(dev, c, 0x02, 0x7f);
  766. else
  767. atp_writeb_io(dev, c, 0x02, 0xcf);
  768. for (i = 0; i < workreq->cmd_len; i++)
  769. atp_writeb_io(dev, c, 0x03 + i, workreq->cmnd[i]);
  770. atp_writeb_io(dev, c, 0x0f, workreq->device->lun);
  771. /*
  772. * Write the target
  773. */
  774. atp_writeb_io(dev, c, 0x11, dev->id[c][target_id].devsp);
  775. #ifdef ED_DBGP
  776. printk("dev->id[%d][%d].devsp = %2x\n",c,target_id,
  777. dev->id[c][target_id].devsp);
  778. #endif
  779. sg_count = scsi_dma_map(workreq);
  780. /*
  781. * Write transfer size
  782. */
  783. atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&l))[2]);
  784. atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&l))[1]);
  785. atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&l))[0]);
  786. j = target_id;
  787. dev->id[c][j].last_len = l;
  788. dev->id[c][j].tran_len = 0;
  789. #ifdef ED_DBGP
  790. printk("dev->id[%2d][%2d].last_len = %d\n",c,j,dev->id[c][j].last_len);
  791. #endif
  792. /*
  793. * Flip the wide bits
  794. */
  795. if ((j & 0x08) != 0) {
  796. j = (j & 0x07) | 0x40;
  797. }
  798. /*
  799. * Check transfer direction
  800. */
  801. if (workreq->sc_data_direction == DMA_TO_DEVICE)
  802. atp_writeb_io(dev, c, 0x15, j | 0x20);
  803. else
  804. atp_writeb_io(dev, c, 0x15, j);
  805. atp_writeb_io(dev, c, 0x16, atp_readb_io(dev, c, 0x16) | 0x80);
  806. atp_writeb_io(dev, c, 0x16, 0x80);
  807. dev->id[c][target_id].dirct = 0;
  808. if (l == 0) {
  809. if (atp_readb_io(dev, c, 0x1c) == 0) {
  810. #ifdef ED_DBGP
  811. printk("change SCSI_CMD_REG 0x08\n");
  812. #endif
  813. atp_writeb_io(dev, c, 0x18, 0x08);
  814. } else
  815. dev->last_cmd[c] |= 0x40;
  816. dev->in_snd[c] = 0;
  817. return;
  818. }
  819. prd = dev->id[c][target_id].prd_table;
  820. dev->id[c][target_id].prd_pos = prd;
  821. /*
  822. * Now write the request list. Either as scatter/gather or as
  823. * a linear chain.
  824. */
  825. if (l) {
  826. struct scatterlist *sgpnt;
  827. i = 0;
  828. scsi_for_each_sg(workreq, sgpnt, sg_count, j) {
  829. bttl = sg_dma_address(sgpnt);
  830. l=sg_dma_len(sgpnt);
  831. #ifdef ED_DBGP
  832. printk("1. bttl %x, l %x\n",bttl, l);
  833. #endif
  834. while (l > 0x10000) {
  835. (((u16 *) (prd))[i + 3]) = 0x0000;
  836. (((u16 *) (prd))[i + 2]) = 0x0000;
  837. (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
  838. l -= 0x10000;
  839. bttl += 0x10000;
  840. i += 0x04;
  841. }
  842. (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
  843. (((u16 *) (prd))[i + 2]) = cpu_to_le16(l);
  844. (((u16 *) (prd))[i + 3]) = 0;
  845. i += 0x04;
  846. }
  847. (((u16 *) (prd))[i - 1]) = cpu_to_le16(0x8000);
  848. #ifdef ED_DBGP
  849. printk("prd %4x %4x %4x %4x\n",
  850. (((unsigned short int *)prd)[0]),
  851. (((unsigned short int *)prd)[1]),
  852. (((unsigned short int *)prd)[2]),
  853. (((unsigned short int *)prd)[3]));
  854. printk("2. bttl %x, l %x\n",bttl, l);
  855. #endif
  856. }
  857. #ifdef ED_DBGP
  858. printk("send_s870: prdaddr_2 0x%8x target_id %d\n",
  859. dev->id[c][target_id].prdaddr,target_id);
  860. #endif
  861. dev->id[c][target_id].prdaddr = dev->id[c][target_id].prd_bus;
  862. atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr);
  863. atp_writeb_pci(dev, c, 2, 0x06);
  864. atp_writeb_pci(dev, c, 2, 0x00);
  865. if (is885(dev)) {
  866. j = atp_readb_pci(dev, c, 1) & 0xf3;
  867. if ((workreq->cmnd[0] == READ_6) ||
  868. (workreq->cmnd[0] == READ_10) ||
  869. (workreq->cmnd[0] == WRITE_6) ||
  870. (workreq->cmnd[0] == WRITE_10)) {
  871. j |= 0x0c;
  872. }
  873. atp_writeb_pci(dev, c, 1, j);
  874. } else if (is880(dev)) {
  875. if ((workreq->cmnd[0] == READ_6) ||
  876. (workreq->cmnd[0] == READ_10) ||
  877. (workreq->cmnd[0] == WRITE_6) ||
  878. (workreq->cmnd[0] == WRITE_10))
  879. atp_writeb_base(dev, 0x3b,
  880. (atp_readb_base(dev, 0x3b) & 0x3f) | 0xc0);
  881. else
  882. atp_writeb_base(dev, 0x3b,
  883. atp_readb_base(dev, 0x3b) & 0x3f);
  884. } else {
  885. if ((workreq->cmnd[0] == READ_6) ||
  886. (workreq->cmnd[0] == READ_10) ||
  887. (workreq->cmnd[0] == WRITE_6) ||
  888. (workreq->cmnd[0] == WRITE_10))
  889. atp_writeb_base(dev, 0x3a,
  890. (atp_readb_base(dev, 0x3a) & 0xf3) | 0x08);
  891. else
  892. atp_writeb_base(dev, 0x3a,
  893. atp_readb_base(dev, 0x3a) & 0xf3);
  894. }
  895. if(workreq->sc_data_direction == DMA_TO_DEVICE) {
  896. dev->id[c][target_id].dirct = 0x20;
  897. if (atp_readb_io(dev, c, 0x1c) == 0) {
  898. atp_writeb_io(dev, c, 0x18, 0x08);
  899. atp_writeb_pci(dev, c, 0, 0x01);
  900. #ifdef ED_DBGP
  901. printk( "start DMA(to target)\n");
  902. #endif
  903. } else {
  904. dev->last_cmd[c] |= 0x40;
  905. }
  906. dev->in_snd[c] = 0;
  907. return;
  908. }
  909. if (atp_readb_io(dev, c, 0x1c) == 0) {
  910. atp_writeb_io(dev, c, 0x18, 0x08);
  911. atp_writeb_pci(dev, c, 0, 0x09);
  912. #ifdef ED_DBGP
  913. printk( "start DMA(to host)\n");
  914. #endif
  915. } else {
  916. dev->last_cmd[c] |= 0x40;
  917. }
  918. dev->in_snd[c] = 0;
  919. return;
  920. }
  921. static unsigned char fun_scam(struct atp_unit *dev, unsigned short int *val)
  922. {
  923. unsigned short int i, k;
  924. unsigned char j;
  925. atp_writew_io(dev, 0, 0x1c, *val);
  926. for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
  927. k = atp_readw_io(dev, 0, 0x1c);
  928. j = (unsigned char) (k >> 8);
  929. if ((k & 0x8000) != 0) /* DB7 all release? */
  930. i = 0;
  931. }
  932. *val |= 0x4000; /* assert DB6 */
  933. atp_writew_io(dev, 0, 0x1c, *val);
  934. *val &= 0xdfff; /* assert DB5 */
  935. atp_writew_io(dev, 0, 0x1c, *val);
  936. for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
  937. if ((atp_readw_io(dev, 0, 0x1c) & 0x2000) != 0) /* DB5 all release? */
  938. i = 0;
  939. }
  940. *val |= 0x8000; /* no DB4-0, assert DB7 */
  941. *val &= 0xe0ff;
  942. atp_writew_io(dev, 0, 0x1c, *val);
  943. *val &= 0xbfff; /* release DB6 */
  944. atp_writew_io(dev, 0, 0x1c, *val);
  945. for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
  946. if ((atp_readw_io(dev, 0, 0x1c) & 0x4000) != 0) /* DB6 all release? */
  947. i = 0;
  948. }
  949. return j;
  950. }
  951. static void tscam(struct Scsi_Host *host, bool wide_chip, u8 scam_on)
  952. {
  953. unsigned char i, j, k;
  954. unsigned long n;
  955. unsigned short int m, assignid_map, val;
  956. unsigned char mbuf[33], quintet[2];
  957. struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
  958. static unsigned char g2q_tab[8] = {
  959. 0x38, 0x31, 0x32, 0x2b, 0x34, 0x2d, 0x2e, 0x27
  960. };
  961. /* I can't believe we need this before we've even done anything. Remove it
  962. * and see if anyone bitches.
  963. for (i = 0; i < 0x10; i++) {
  964. udelay(0xffff);
  965. }
  966. */
  967. atp_writeb_io(dev, 0, 1, 0x08);
  968. atp_writeb_io(dev, 0, 2, 0x7f);
  969. atp_writeb_io(dev, 0, 0x11, 0x20);
  970. if ((scam_on & 0x40) == 0) {
  971. return;
  972. }
  973. m = 1;
  974. m <<= dev->host_id[0];
  975. j = 16;
  976. if (!wide_chip) {
  977. m |= 0xff00;
  978. j = 8;
  979. }
  980. assignid_map = m;
  981. atp_writeb_io(dev, 0, 0x02, 0x02); /* 2*2=4ms,3EH 2/32*3E=3.9ms */
  982. atp_writeb_io(dev, 0, 0x03, 0);
  983. atp_writeb_io(dev, 0, 0x04, 0);
  984. atp_writeb_io(dev, 0, 0x05, 0);
  985. atp_writeb_io(dev, 0, 0x06, 0);
  986. atp_writeb_io(dev, 0, 0x07, 0);
  987. atp_writeb_io(dev, 0, 0x08, 0);
  988. for (i = 0; i < j; i++) {
  989. m = 1;
  990. m = m << i;
  991. if ((m & assignid_map) != 0) {
  992. continue;
  993. }
  994. atp_writeb_io(dev, 0, 0x0f, 0);
  995. atp_writeb_io(dev, 0, 0x12, 0);
  996. atp_writeb_io(dev, 0, 0x13, 0);
  997. atp_writeb_io(dev, 0, 0x14, 0);
  998. if (i > 7) {
  999. k = (i & 0x07) | 0x40;
  1000. } else {
  1001. k = i;
  1002. }
  1003. atp_writeb_io(dev, 0, 0x15, k);
  1004. if (wide_chip)
  1005. atp_writeb_io(dev, 0, 0x1b, 0x01);
  1006. else
  1007. atp_writeb_io(dev, 0, 0x1b, 0x00);
  1008. do {
  1009. atp_writeb_io(dev, 0, 0x18, 0x09);
  1010. while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
  1011. cpu_relax();
  1012. k = atp_readb_io(dev, 0, 0x17);
  1013. if ((k == 0x85) || (k == 0x42))
  1014. break;
  1015. if (k != 0x16)
  1016. atp_writeb_io(dev, 0, 0x10, 0x41);
  1017. } while (k != 0x16);
  1018. if ((k == 0x85) || (k == 0x42))
  1019. continue;
  1020. assignid_map |= m;
  1021. }
  1022. atp_writeb_io(dev, 0, 0x02, 0x7f);
  1023. atp_writeb_io(dev, 0, 0x1b, 0x02);
  1024. udelay(2);
  1025. val = 0x0080; /* bsy */
  1026. atp_writew_io(dev, 0, 0x1c, val);
  1027. val |= 0x0040; /* sel */
  1028. atp_writew_io(dev, 0, 0x1c, val);
  1029. val |= 0x0004; /* msg */
  1030. atp_writew_io(dev, 0, 0x1c, val);
  1031. udelay(2); /* 2 deskew delay(45ns*2=90ns) */
  1032. val &= 0x007f; /* no bsy */
  1033. atp_writew_io(dev, 0, 0x1c, val);
  1034. msleep(128);
  1035. val &= 0x00fb; /* after 1ms no msg */
  1036. atp_writew_io(dev, 0, 0x1c, val);
  1037. while ((atp_readb_io(dev, 0, 0x1c) & 0x04) != 0)
  1038. ;
  1039. udelay(2);
  1040. udelay(100);
  1041. for (n = 0; n < 0x30000; n++)
  1042. if ((atp_readb_io(dev, 0, 0x1c) & 0x80) != 0) /* bsy ? */
  1043. break;
  1044. if (n < 0x30000)
  1045. for (n = 0; n < 0x30000; n++)
  1046. if ((atp_readb_io(dev, 0, 0x1c) & 0x81) == 0x0081) {
  1047. udelay(2);
  1048. val |= 0x8003; /* io,cd,db7 */
  1049. atp_writew_io(dev, 0, 0x1c, val);
  1050. udelay(2);
  1051. val &= 0x00bf; /* no sel */
  1052. atp_writew_io(dev, 0, 0x1c, val);
  1053. udelay(2);
  1054. break;
  1055. }
  1056. while (1) {
  1057. /*
  1058. * The funny division into multiple delays is to accomodate
  1059. * arches like ARM where udelay() multiplies its argument by
  1060. * a large number to initialize a loop counter. To avoid
  1061. * overflow, the maximum supported udelay is 2000 microseconds.
  1062. *
  1063. * XXX it would be more polite to find a way to use msleep()
  1064. */
  1065. mdelay(2);
  1066. udelay(48);
  1067. if ((atp_readb_io(dev, 0, 0x1c) & 0x80) == 0x00) { /* bsy ? */
  1068. atp_writew_io(dev, 0, 0x1c, 0);
  1069. atp_writeb_io(dev, 0, 0x1b, 0);
  1070. atp_writeb_io(dev, 0, 0x15, 0);
  1071. atp_writeb_io(dev, 0, 0x18, 0x09);
  1072. while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0)
  1073. cpu_relax();
  1074. atp_readb_io(dev, 0, 0x17);
  1075. return;
  1076. }
  1077. val &= 0x00ff; /* synchronization */
  1078. val |= 0x3f00;
  1079. fun_scam(dev, &val);
  1080. udelay(2);
  1081. val &= 0x00ff; /* isolation */
  1082. val |= 0x2000;
  1083. fun_scam(dev, &val);
  1084. udelay(2);
  1085. i = 8;
  1086. j = 0;
  1087. while (1) {
  1088. if ((atp_readw_io(dev, 0, 0x1c) & 0x2000) == 0)
  1089. continue;
  1090. udelay(2);
  1091. val &= 0x00ff; /* get ID_STRING */
  1092. val |= 0x2000;
  1093. k = fun_scam(dev, &val);
  1094. if ((k & 0x03) == 0)
  1095. break;
  1096. mbuf[j] <<= 0x01;
  1097. mbuf[j] &= 0xfe;
  1098. if ((k & 0x02) != 0)
  1099. mbuf[j] |= 0x01;
  1100. i--;
  1101. if (i > 0)
  1102. continue;
  1103. j++;
  1104. i = 8;
  1105. }
  1106. /* isolation complete.. */
  1107. /* mbuf[32]=0;
  1108. printk(" \n%x %x %x %s\n ",assignid_map,mbuf[0],mbuf[1],&mbuf[2]); */
  1109. i = 15;
  1110. j = mbuf[0];
  1111. if ((j & 0x20) != 0) { /* bit5=1:ID up to 7 */
  1112. i = 7;
  1113. }
  1114. if ((j & 0x06) != 0) { /* IDvalid? */
  1115. k = mbuf[1];
  1116. while (1) {
  1117. m = 1;
  1118. m <<= k;
  1119. if ((m & assignid_map) == 0)
  1120. break;
  1121. if (k > 0)
  1122. k--;
  1123. else
  1124. break;
  1125. }
  1126. }
  1127. if ((m & assignid_map) != 0) { /* srch from max acceptable ID# */
  1128. k = i; /* max acceptable ID# */
  1129. while (1) {
  1130. m = 1;
  1131. m <<= k;
  1132. if ((m & assignid_map) == 0)
  1133. break;
  1134. if (k > 0)
  1135. k--;
  1136. else
  1137. break;
  1138. }
  1139. }
  1140. /* k=binID#, */
  1141. assignid_map |= m;
  1142. if (k < 8) {
  1143. quintet[0] = 0x38; /* 1st dft ID<8 */
  1144. } else {
  1145. quintet[0] = 0x31; /* 1st ID>=8 */
  1146. }
  1147. k &= 0x07;
  1148. quintet[1] = g2q_tab[k];
  1149. val &= 0x00ff; /* AssignID 1stQuintet,AH=001xxxxx */
  1150. m = quintet[0] << 8;
  1151. val |= m;
  1152. fun_scam(dev, &val);
  1153. val &= 0x00ff; /* AssignID 2ndQuintet,AH=001xxxxx */
  1154. m = quintet[1] << 8;
  1155. val |= m;
  1156. fun_scam(dev, &val);
  1157. }
  1158. }
  1159. static void atp870u_free_tables(struct Scsi_Host *host)
  1160. {
  1161. struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
  1162. int j, k;
  1163. for (j=0; j < 2; j++) {
  1164. for (k = 0; k < 16; k++) {
  1165. if (!atp_dev->id[j][k].prd_table)
  1166. continue;
  1167. dma_free_coherent(&atp_dev->pdev->dev, 1024,
  1168. atp_dev->id[j][k].prd_table,
  1169. atp_dev->id[j][k].prd_bus);
  1170. atp_dev->id[j][k].prd_table = NULL;
  1171. }
  1172. }
  1173. }
  1174. static int atp870u_init_tables(struct Scsi_Host *host)
  1175. {
  1176. struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
  1177. int c,k;
  1178. for(c=0;c < 2;c++) {
  1179. for(k=0;k<16;k++) {
  1180. atp_dev->id[c][k].prd_table =
  1181. dma_alloc_coherent(&atp_dev->pdev->dev, 1024,
  1182. &(atp_dev->id[c][k].prd_bus),
  1183. GFP_KERNEL);
  1184. if (!atp_dev->id[c][k].prd_table) {
  1185. printk("atp870u_init_tables fail\n");
  1186. atp870u_free_tables(host);
  1187. return -ENOMEM;
  1188. }
  1189. atp_dev->id[c][k].prdaddr = atp_dev->id[c][k].prd_bus;
  1190. atp_dev->id[c][k].devsp=0x20;
  1191. atp_dev->id[c][k].devtype = 0x7f;
  1192. atp_dev->id[c][k].curr_req = NULL;
  1193. }
  1194. atp_dev->active_id[c] = 0;
  1195. atp_dev->wide_id[c] = 0;
  1196. atp_dev->host_id[c] = 0x07;
  1197. atp_dev->quhd[c] = 0;
  1198. atp_dev->quend[c] = 0;
  1199. atp_dev->last_cmd[c] = 0xff;
  1200. atp_dev->in_snd[c] = 0;
  1201. atp_dev->in_int[c] = 0;
  1202. for (k = 0; k < qcnt; k++) {
  1203. atp_dev->quereq[c][k] = NULL;
  1204. }
  1205. for (k = 0; k < 16; k++) {
  1206. atp_dev->id[c][k].curr_req = NULL;
  1207. atp_dev->sp[c][k] = 0x04;
  1208. }
  1209. }
  1210. return 0;
  1211. }
  1212. static void atp_set_host_id(struct atp_unit *atp, u8 c, u8 host_id)
  1213. {
  1214. atp_writeb_io(atp, c, 0, host_id | 0x08);
  1215. atp_writeb_io(atp, c, 0x18, 0);
  1216. while ((atp_readb_io(atp, c, 0x1f) & 0x80) == 0)
  1217. mdelay(1);
  1218. atp_readb_io(atp, c, 0x17);
  1219. atp_writeb_io(atp, c, 1, 8);
  1220. atp_writeb_io(atp, c, 2, 0x7f);
  1221. atp_writeb_io(atp, c, 0x11, 0x20);
  1222. }
  1223. static void atp870_init(struct Scsi_Host *shpnt)
  1224. {
  1225. struct atp_unit *atpdev = shost_priv(shpnt);
  1226. struct pci_dev *pdev = atpdev->pdev;
  1227. unsigned char k, host_id;
  1228. u8 scam_on;
  1229. bool wide_chip =
  1230. (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7610 &&
  1231. pdev->revision == 4) ||
  1232. (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7612UW) ||
  1233. (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7612SUW);
  1234. pci_read_config_byte(pdev, 0x49, &host_id);
  1235. dev_info(&pdev->dev, "ACARD AEC-671X PCI Ultra/W SCSI-2/3 "
  1236. "Host Adapter: IO:%lx, IRQ:%d.\n",
  1237. shpnt->io_port, shpnt->irq);
  1238. atpdev->ioport[0] = shpnt->io_port;
  1239. atpdev->pciport[0] = shpnt->io_port + 0x20;
  1240. host_id &= 0x07;
  1241. atpdev->host_id[0] = host_id;
  1242. scam_on = atp_readb_pci(atpdev, 0, 2);
  1243. atpdev->global_map[0] = atp_readb_base(atpdev, 0x2d);
  1244. atpdev->ultra_map[0] = atp_readw_base(atpdev, 0x2e);
  1245. if (atpdev->ultra_map[0] == 0) {
  1246. scam_on = 0x00;
  1247. atpdev->global_map[0] = 0x20;
  1248. atpdev->ultra_map[0] = 0xffff;
  1249. }
  1250. if (pdev->revision > 0x07) /* check if atp876 chip */
  1251. atp_writeb_base(atpdev, 0x3e, 0x00); /* enable terminator */
  1252. k = (atp_readb_base(atpdev, 0x3a) & 0xf3) | 0x10;
  1253. atp_writeb_base(atpdev, 0x3a, k);
  1254. atp_writeb_base(atpdev, 0x3a, k & 0xdf);
  1255. msleep(32);
  1256. atp_writeb_base(atpdev, 0x3a, k);
  1257. msleep(32);
  1258. atp_set_host_id(atpdev, 0, host_id);
  1259. tscam(shpnt, wide_chip, scam_on);
  1260. atp_writeb_base(atpdev, 0x3a, atp_readb_base(atpdev, 0x3a) | 0x10);
  1261. atp_is(atpdev, 0, wide_chip, 0);
  1262. atp_writeb_base(atpdev, 0x3a, atp_readb_base(atpdev, 0x3a) & 0xef);
  1263. atp_writeb_base(atpdev, 0x3b, atp_readb_base(atpdev, 0x3b) | 0x20);
  1264. shpnt->max_id = wide_chip ? 16 : 8;
  1265. shpnt->this_id = host_id;
  1266. }
  1267. static void atp880_init(struct Scsi_Host *shpnt)
  1268. {
  1269. struct atp_unit *atpdev = shost_priv(shpnt);
  1270. struct pci_dev *pdev = atpdev->pdev;
  1271. unsigned char k, m, host_id;
  1272. unsigned int n;
  1273. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
  1274. atpdev->ioport[0] = shpnt->io_port + 0x40;
  1275. atpdev->pciport[0] = shpnt->io_port + 0x28;
  1276. host_id = atp_readb_base(atpdev, 0x39) >> 4;
  1277. dev_info(&pdev->dev, "ACARD AEC-67160 PCI Ultra3 LVD "
  1278. "Host Adapter: IO:%lx, IRQ:%d.\n",
  1279. shpnt->io_port, shpnt->irq);
  1280. atpdev->host_id[0] = host_id;
  1281. atpdev->global_map[0] = atp_readb_base(atpdev, 0x35);
  1282. atpdev->ultra_map[0] = atp_readw_base(atpdev, 0x3c);
  1283. n = 0x3f09;
  1284. while (n < 0x4000) {
  1285. m = 0;
  1286. atp_writew_base(atpdev, 0x34, n);
  1287. n += 0x0002;
  1288. if (atp_readb_base(atpdev, 0x30) == 0xff)
  1289. break;
  1290. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30);
  1291. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31);
  1292. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32);
  1293. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33);
  1294. atp_writew_base(atpdev, 0x34, n);
  1295. n += 0x0002;
  1296. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30);
  1297. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31);
  1298. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32);
  1299. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33);
  1300. atp_writew_base(atpdev, 0x34, n);
  1301. n += 0x0002;
  1302. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30);
  1303. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31);
  1304. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32);
  1305. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33);
  1306. atp_writew_base(atpdev, 0x34, n);
  1307. n += 0x0002;
  1308. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30);
  1309. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31);
  1310. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32);
  1311. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33);
  1312. n += 0x0018;
  1313. }
  1314. atp_writew_base(atpdev, 0x34, 0);
  1315. atpdev->ultra_map[0] = 0;
  1316. atpdev->async[0] = 0;
  1317. for (k = 0; k < 16; k++) {
  1318. n = 1 << k;
  1319. if (atpdev->sp[0][k] > 1)
  1320. atpdev->ultra_map[0] |= n;
  1321. else
  1322. if (atpdev->sp[0][k] == 0)
  1323. atpdev->async[0] |= n;
  1324. }
  1325. atpdev->async[0] = ~(atpdev->async[0]);
  1326. atp_writeb_base(atpdev, 0x35, atpdev->global_map[0]);
  1327. k = atp_readb_base(atpdev, 0x38) & 0x80;
  1328. atp_writeb_base(atpdev, 0x38, k);
  1329. atp_writeb_base(atpdev, 0x3b, 0x20);
  1330. msleep(32);
  1331. atp_writeb_base(atpdev, 0x3b, 0);
  1332. msleep(32);
  1333. atp_readb_io(atpdev, 0, 0x1b);
  1334. atp_readb_io(atpdev, 0, 0x17);
  1335. atp_set_host_id(atpdev, 0, host_id);
  1336. tscam(shpnt, true, atp_readb_base(atpdev, 0x22));
  1337. atp_is(atpdev, 0, true, atp_readb_base(atpdev, 0x3f) & 0x40);
  1338. atp_writeb_base(atpdev, 0x38, 0xb0);
  1339. shpnt->max_id = 16;
  1340. shpnt->this_id = host_id;
  1341. }
  1342. static void atp885_init(struct Scsi_Host *shpnt)
  1343. {
  1344. struct atp_unit *atpdev = shost_priv(shpnt);
  1345. struct pci_dev *pdev = atpdev->pdev;
  1346. unsigned char k, m, c;
  1347. unsigned int n;
  1348. unsigned char setupdata[2][16];
  1349. dev_info(&pdev->dev, "ACARD AEC-67162 PCI Ultra3 LVD "
  1350. "Host Adapter: IO:%lx, IRQ:%d.\n",
  1351. shpnt->io_port, shpnt->irq);
  1352. atpdev->ioport[0] = shpnt->io_port + 0x80;
  1353. atpdev->ioport[1] = shpnt->io_port + 0xc0;
  1354. atpdev->pciport[0] = shpnt->io_port + 0x40;
  1355. atpdev->pciport[1] = shpnt->io_port + 0x50;
  1356. c = atp_readb_base(atpdev, 0x29);
  1357. atp_writeb_base(atpdev, 0x29, c | 0x04);
  1358. n = 0x1f80;
  1359. while (n < 0x2000) {
  1360. atp_writew_base(atpdev, 0x3c, n);
  1361. if (atp_readl_base(atpdev, 0x38) == 0xffffffff)
  1362. break;
  1363. for (m = 0; m < 2; m++) {
  1364. atpdev->global_map[m] = 0;
  1365. for (k = 0; k < 4; k++) {
  1366. atp_writew_base(atpdev, 0x3c, n++);
  1367. ((u32 *)&setupdata[m][0])[k] =
  1368. atp_readl_base(atpdev, 0x38);
  1369. }
  1370. for (k = 0; k < 4; k++) {
  1371. atp_writew_base(atpdev, 0x3c, n++);
  1372. ((u32 *)&atpdev->sp[m][0])[k] =
  1373. atp_readl_base(atpdev, 0x38);
  1374. }
  1375. n += 8;
  1376. }
  1377. }
  1378. c = atp_readb_base(atpdev, 0x29);
  1379. atp_writeb_base(atpdev, 0x29, c & 0xfb);
  1380. for (c = 0; c < 2; c++) {
  1381. atpdev->ultra_map[c] = 0;
  1382. atpdev->async[c] = 0;
  1383. for (k = 0; k < 16; k++) {
  1384. n = 1 << k;
  1385. if (atpdev->sp[c][k] > 1)
  1386. atpdev->ultra_map[c] |= n;
  1387. else
  1388. if (atpdev->sp[c][k] == 0)
  1389. atpdev->async[c] |= n;
  1390. }
  1391. atpdev->async[c] = ~(atpdev->async[c]);
  1392. if (atpdev->global_map[c] == 0) {
  1393. k = setupdata[c][1];
  1394. if ((k & 0x40) != 0)
  1395. atpdev->global_map[c] |= 0x20;
  1396. k &= 0x07;
  1397. atpdev->global_map[c] |= k;
  1398. if ((setupdata[c][2] & 0x04) != 0)
  1399. atpdev->global_map[c] |= 0x08;
  1400. atpdev->host_id[c] = setupdata[c][0] & 0x07;
  1401. }
  1402. }
  1403. k = atp_readb_base(atpdev, 0x28) & 0x8f;
  1404. k |= 0x10;
  1405. atp_writeb_base(atpdev, 0x28, k);
  1406. atp_writeb_pci(atpdev, 0, 1, 0x80);
  1407. atp_writeb_pci(atpdev, 1, 1, 0x80);
  1408. msleep(100);
  1409. atp_writeb_pci(atpdev, 0, 1, 0);
  1410. atp_writeb_pci(atpdev, 1, 1, 0);
  1411. msleep(1000);
  1412. atp_readb_io(atpdev, 0, 0x1b);
  1413. atp_readb_io(atpdev, 0, 0x17);
  1414. atp_readb_io(atpdev, 1, 0x1b);
  1415. atp_readb_io(atpdev, 1, 0x17);
  1416. k = atpdev->host_id[0];
  1417. if (k > 7)
  1418. k = (k & 0x07) | 0x40;
  1419. atp_set_host_id(atpdev, 0, k);
  1420. k = atpdev->host_id[1];
  1421. if (k > 7)
  1422. k = (k & 0x07) | 0x40;
  1423. atp_set_host_id(atpdev, 1, k);
  1424. msleep(600); /* this delay used to be called tscam_885() */
  1425. dev_info(&pdev->dev, "Scanning Channel A SCSI Device ...\n");
  1426. atp_is(atpdev, 0, true, atp_readb_io(atpdev, 0, 0x1b) >> 7);
  1427. atp_writeb_io(atpdev, 0, 0x16, 0x80);
  1428. dev_info(&pdev->dev, "Scanning Channel B SCSI Device ...\n");
  1429. atp_is(atpdev, 1, true, atp_readb_io(atpdev, 1, 0x1b) >> 7);
  1430. atp_writeb_io(atpdev, 1, 0x16, 0x80);
  1431. k = atp_readb_base(atpdev, 0x28) & 0xcf;
  1432. k |= 0xc0;
  1433. atp_writeb_base(atpdev, 0x28, k);
  1434. k = atp_readb_base(atpdev, 0x1f) | 0x80;
  1435. atp_writeb_base(atpdev, 0x1f, k);
  1436. k = atp_readb_base(atpdev, 0x29) | 0x01;
  1437. atp_writeb_base(atpdev, 0x29, k);
  1438. shpnt->max_id = 16;
  1439. shpnt->max_lun = (atpdev->global_map[0] & 0x07) + 1;
  1440. shpnt->max_channel = 1;
  1441. shpnt->this_id = atpdev->host_id[0];
  1442. }
  1443. /* return non-zero on detection */
  1444. static int atp870u_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1445. {
  1446. struct Scsi_Host *shpnt = NULL;
  1447. struct atp_unit *atpdev;
  1448. int err;
  1449. if (ent->device == PCI_DEVICE_ID_ARTOP_AEC7610 && pdev->revision < 2) {
  1450. dev_err(&pdev->dev, "ATP850S chips (AEC6710L/F cards) are not supported.\n");
  1451. return -ENODEV;
  1452. }
  1453. err = pci_enable_device(pdev);
  1454. if (err)
  1455. goto fail;
  1456. if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
  1457. printk(KERN_ERR "atp870u: DMA mask required but not available.\n");
  1458. err = -EIO;
  1459. goto disable_device;
  1460. }
  1461. err = pci_request_regions(pdev, "atp870u");
  1462. if (err)
  1463. goto disable_device;
  1464. pci_set_master(pdev);
  1465. err = -ENOMEM;
  1466. shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
  1467. if (!shpnt)
  1468. goto release_region;
  1469. atpdev = shost_priv(shpnt);
  1470. atpdev->host = shpnt;
  1471. atpdev->pdev = pdev;
  1472. pci_set_drvdata(pdev, atpdev);
  1473. shpnt->io_port = pci_resource_start(pdev, 0);
  1474. shpnt->io_port &= 0xfffffff8;
  1475. shpnt->n_io_port = pci_resource_len(pdev, 0);
  1476. atpdev->baseport = shpnt->io_port;
  1477. shpnt->unique_id = shpnt->io_port;
  1478. shpnt->irq = pdev->irq;
  1479. err = atp870u_init_tables(shpnt);
  1480. if (err) {
  1481. dev_err(&pdev->dev, "Unable to allocate tables for Acard controller\n");
  1482. goto unregister;
  1483. }
  1484. if (is880(atpdev))
  1485. atp880_init(shpnt);
  1486. else if (is885(atpdev))
  1487. atp885_init(shpnt);
  1488. else
  1489. atp870_init(shpnt);
  1490. err = request_irq(shpnt->irq, atp870u_intr_handle, IRQF_SHARED, "atp870u", shpnt);
  1491. if (err) {
  1492. dev_err(&pdev->dev, "Unable to allocate IRQ %d.\n", shpnt->irq);
  1493. goto free_tables;
  1494. }
  1495. err = scsi_add_host(shpnt, &pdev->dev);
  1496. if (err)
  1497. goto scsi_add_fail;
  1498. scsi_scan_host(shpnt);
  1499. return 0;
  1500. scsi_add_fail:
  1501. free_irq(shpnt->irq, shpnt);
  1502. free_tables:
  1503. atp870u_free_tables(shpnt);
  1504. unregister:
  1505. scsi_host_put(shpnt);
  1506. release_region:
  1507. pci_release_regions(pdev);
  1508. disable_device:
  1509. pci_disable_device(pdev);
  1510. fail:
  1511. return err;
  1512. }
  1513. /* The abort command does not leave the device in a clean state where
  1514. it is available to be used again. Until this gets worked out, we will
  1515. leave it commented out. */
  1516. static int atp870u_abort(struct scsi_cmnd * SCpnt)
  1517. {
  1518. unsigned char j, k, c;
  1519. struct scsi_cmnd *workrequ;
  1520. struct atp_unit *dev;
  1521. struct Scsi_Host *host;
  1522. host = SCpnt->device->host;
  1523. dev = (struct atp_unit *)&host->hostdata;
  1524. c = scmd_channel(SCpnt);
  1525. printk(" atp870u: abort Channel = %x \n", c);
  1526. printk("working=%x last_cmd=%x ", dev->working[c], dev->last_cmd[c]);
  1527. printk(" quhdu=%x quendu=%x ", dev->quhd[c], dev->quend[c]);
  1528. for (j = 0; j < 0x18; j++) {
  1529. printk(" r%2x=%2x", j, atp_readb_io(dev, c, j));
  1530. }
  1531. printk(" r1c=%2x", atp_readb_io(dev, c, 0x1c));
  1532. printk(" r1f=%2x in_snd=%2x ", atp_readb_io(dev, c, 0x1f), dev->in_snd[c]);
  1533. printk(" d00=%2x", atp_readb_pci(dev, c, 0x00));
  1534. printk(" d02=%2x", atp_readb_pci(dev, c, 0x02));
  1535. for(j=0;j<16;j++) {
  1536. if (dev->id[c][j].curr_req != NULL) {
  1537. workrequ = dev->id[c][j].curr_req;
  1538. printk("\n que cdb= ");
  1539. for (k=0; k < workrequ->cmd_len; k++) {
  1540. printk(" %2x ",workrequ->cmnd[k]);
  1541. }
  1542. printk(" last_lenu= %x ",(unsigned int)dev->id[c][j].last_len);
  1543. }
  1544. }
  1545. return SUCCESS;
  1546. }
  1547. static const char *atp870u_info(struct Scsi_Host *notused)
  1548. {
  1549. static char buffer[128];
  1550. strcpy(buffer, "ACARD AEC-6710/6712/67160 PCI Ultra/W/LVD SCSI-3 Adapter Driver V2.6+ac ");
  1551. return buffer;
  1552. }
  1553. static int atp870u_show_info(struct seq_file *m, struct Scsi_Host *HBAptr)
  1554. {
  1555. seq_puts(m, "ACARD AEC-671X Driver Version: 2.6+ac\n\n"
  1556. "Adapter Configuration:\n");
  1557. seq_printf(m, " Base IO: %#.4lx\n", HBAptr->io_port);
  1558. seq_printf(m, " IRQ: %d\n", HBAptr->irq);
  1559. return 0;
  1560. }
  1561. static int atp870u_biosparam(struct scsi_device *disk, struct block_device *dev,
  1562. sector_t capacity, int *ip)
  1563. {
  1564. int heads, sectors, cylinders;
  1565. heads = 64;
  1566. sectors = 32;
  1567. cylinders = (unsigned long)capacity / (heads * sectors);
  1568. if (cylinders > 1024) {
  1569. heads = 255;
  1570. sectors = 63;
  1571. cylinders = (unsigned long)capacity / (heads * sectors);
  1572. }
  1573. ip[0] = heads;
  1574. ip[1] = sectors;
  1575. ip[2] = cylinders;
  1576. return 0;
  1577. }
  1578. static void atp870u_remove (struct pci_dev *pdev)
  1579. {
  1580. struct atp_unit *devext = pci_get_drvdata(pdev);
  1581. struct Scsi_Host *pshost = devext->host;
  1582. scsi_remove_host(pshost);
  1583. free_irq(pshost->irq, pshost);
  1584. pci_release_regions(pdev);
  1585. pci_disable_device(pdev);
  1586. atp870u_free_tables(pshost);
  1587. scsi_host_put(pshost);
  1588. }
  1589. MODULE_DESCRIPTION("ACARD SCSI host adapter driver");
  1590. MODULE_LICENSE("GPL");
  1591. static const struct scsi_host_template atp870u_template = {
  1592. .module = THIS_MODULE,
  1593. .name = "atp870u" /* name */,
  1594. .proc_name = "atp870u",
  1595. .show_info = atp870u_show_info,
  1596. .info = atp870u_info /* info */,
  1597. .queuecommand = atp870u_queuecommand /* queuecommand */,
  1598. .eh_abort_handler = atp870u_abort /* abort */,
  1599. .bios_param = atp870u_biosparam /* biosparm */,
  1600. .can_queue = qcnt /* can_queue */,
  1601. .this_id = 7 /* SCSI ID */,
  1602. .sg_tablesize = ATP870U_SCATTER /*SG_ALL*/,
  1603. .max_sectors = ATP870U_MAX_SECTORS,
  1604. };
  1605. static struct pci_device_id atp870u_id_table[] = {
  1606. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP885_DEVID) },
  1607. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID1) },
  1608. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID2) },
  1609. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7610) },
  1610. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612UW) },
  1611. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612U) },
  1612. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612S) },
  1613. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612D) },
  1614. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612SUW) },
  1615. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_8060) },
  1616. { 0, },
  1617. };
  1618. MODULE_DEVICE_TABLE(pci, atp870u_id_table);
  1619. static struct pci_driver atp870u_driver = {
  1620. .id_table = atp870u_id_table,
  1621. .name = "atp870u",
  1622. .probe = atp870u_probe,
  1623. .remove = atp870u_remove,
  1624. };
  1625. module_pci_driver(atp870u_driver);
  1626. static void atp_is(struct atp_unit *dev, unsigned char c, bool wide_chip,
  1627. unsigned char lvdmode)
  1628. {
  1629. unsigned char i, j, k, rmb, n;
  1630. unsigned short int m;
  1631. static unsigned char mbuf[512];
  1632. static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
  1633. static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
  1634. static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
  1635. unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
  1636. static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
  1637. static unsigned char synw_870[6] = { 0x80, 1, 3, 1, 0x0c, 0x07 };
  1638. unsigned char synuw[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
  1639. static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
  1640. static unsigned char u3[9] = { 0x80, 1, 6, 4, 0x09, 00, 0x0e, 0x01, 0x02 };
  1641. for (i = 0; i < 16; i++) {
  1642. if (!wide_chip && (i > 7))
  1643. break;
  1644. m = 1;
  1645. m = m << i;
  1646. if ((m & dev->active_id[c]) != 0) {
  1647. continue;
  1648. }
  1649. if (i == dev->host_id[c]) {
  1650. printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[c]);
  1651. continue;
  1652. }
  1653. atp_writeb_io(dev, c, 0x1b, wide_chip ? 0x01 : 0x00);
  1654. atp_writeb_io(dev, c, 1, 0x08);
  1655. atp_writeb_io(dev, c, 2, 0x7f);
  1656. atp_writeb_io(dev, c, 3, satn[0]);
  1657. atp_writeb_io(dev, c, 4, satn[1]);
  1658. atp_writeb_io(dev, c, 5, satn[2]);
  1659. atp_writeb_io(dev, c, 6, satn[3]);
  1660. atp_writeb_io(dev, c, 7, satn[4]);
  1661. atp_writeb_io(dev, c, 8, satn[5]);
  1662. atp_writeb_io(dev, c, 0x0f, 0);
  1663. atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
  1664. atp_writeb_io(dev, c, 0x12, 0);
  1665. atp_writeb_io(dev, c, 0x13, satn[6]);
  1666. atp_writeb_io(dev, c, 0x14, satn[7]);
  1667. j = i;
  1668. if ((j & 0x08) != 0) {
  1669. j = (j & 0x07) | 0x40;
  1670. }
  1671. atp_writeb_io(dev, c, 0x15, j);
  1672. atp_writeb_io(dev, c, 0x18, satn[8]);
  1673. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1674. cpu_relax();
  1675. if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
  1676. continue;
  1677. while (atp_readb_io(dev, c, 0x17) != 0x8e)
  1678. cpu_relax();
  1679. dev->active_id[c] |= m;
  1680. atp_writeb_io(dev, c, 0x10, 0x30);
  1681. if (is885(dev) || is880(dev))
  1682. atp_writeb_io(dev, c, 0x14, 0x00);
  1683. else /* result of is870() merge - is this a bug? */
  1684. atp_writeb_io(dev, c, 0x04, 0x00);
  1685. phase_cmd:
  1686. atp_writeb_io(dev, c, 0x18, 0x08);
  1687. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1688. cpu_relax();
  1689. j = atp_readb_io(dev, c, 0x17);
  1690. if (j != 0x16) {
  1691. atp_writeb_io(dev, c, 0x10, 0x41);
  1692. goto phase_cmd;
  1693. }
  1694. sel_ok:
  1695. atp_writeb_io(dev, c, 3, inqd[0]);
  1696. atp_writeb_io(dev, c, 4, inqd[1]);
  1697. atp_writeb_io(dev, c, 5, inqd[2]);
  1698. atp_writeb_io(dev, c, 6, inqd[3]);
  1699. atp_writeb_io(dev, c, 7, inqd[4]);
  1700. atp_writeb_io(dev, c, 8, inqd[5]);
  1701. atp_writeb_io(dev, c, 0x0f, 0);
  1702. atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
  1703. atp_writeb_io(dev, c, 0x12, 0);
  1704. atp_writeb_io(dev, c, 0x13, inqd[6]);
  1705. atp_writeb_io(dev, c, 0x14, inqd[7]);
  1706. atp_writeb_io(dev, c, 0x18, inqd[8]);
  1707. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1708. cpu_relax();
  1709. if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
  1710. continue;
  1711. while (atp_readb_io(dev, c, 0x17) != 0x8e)
  1712. cpu_relax();
  1713. if (wide_chip)
  1714. atp_writeb_io(dev, c, 0x1b, 0x00);
  1715. atp_writeb_io(dev, c, 0x18, 0x08);
  1716. j = 0;
  1717. rd_inq_data:
  1718. k = atp_readb_io(dev, c, 0x1f);
  1719. if ((k & 0x01) != 0) {
  1720. mbuf[j++] = atp_readb_io(dev, c, 0x19);
  1721. goto rd_inq_data;
  1722. }
  1723. if ((k & 0x80) == 0) {
  1724. goto rd_inq_data;
  1725. }
  1726. j = atp_readb_io(dev, c, 0x17);
  1727. if (j == 0x16) {
  1728. goto inq_ok;
  1729. }
  1730. atp_writeb_io(dev, c, 0x10, 0x46);
  1731. atp_writeb_io(dev, c, 0x12, 0);
  1732. atp_writeb_io(dev, c, 0x13, 0);
  1733. atp_writeb_io(dev, c, 0x14, 0);
  1734. atp_writeb_io(dev, c, 0x18, 0x08);
  1735. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1736. cpu_relax();
  1737. if (atp_readb_io(dev, c, 0x17) != 0x16)
  1738. goto sel_ok;
  1739. inq_ok:
  1740. mbuf[36] = 0;
  1741. printk(KERN_INFO " ID: %2d %s\n", i, &mbuf[8]);
  1742. dev->id[c][i].devtype = mbuf[0];
  1743. rmb = mbuf[1];
  1744. n = mbuf[7];
  1745. if (!wide_chip)
  1746. goto not_wide;
  1747. if ((mbuf[7] & 0x60) == 0) {
  1748. goto not_wide;
  1749. }
  1750. if (is885(dev) || is880(dev)) {
  1751. if ((i < 8) && ((dev->global_map[c] & 0x20) == 0))
  1752. goto not_wide;
  1753. } else { /* result of is870() merge - is this a bug? */
  1754. if ((dev->global_map[c] & 0x20) == 0)
  1755. goto not_wide;
  1756. }
  1757. if (lvdmode == 0) {
  1758. goto chg_wide;
  1759. }
  1760. if (dev->sp[c][i] != 0x04) // force u2
  1761. {
  1762. goto chg_wide;
  1763. }
  1764. atp_writeb_io(dev, c, 0x1b, 0x01);
  1765. atp_writeb_io(dev, c, 3, satn[0]);
  1766. atp_writeb_io(dev, c, 4, satn[1]);
  1767. atp_writeb_io(dev, c, 5, satn[2]);
  1768. atp_writeb_io(dev, c, 6, satn[3]);
  1769. atp_writeb_io(dev, c, 7, satn[4]);
  1770. atp_writeb_io(dev, c, 8, satn[5]);
  1771. atp_writeb_io(dev, c, 0x0f, 0);
  1772. atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
  1773. atp_writeb_io(dev, c, 0x12, 0);
  1774. atp_writeb_io(dev, c, 0x13, satn[6]);
  1775. atp_writeb_io(dev, c, 0x14, satn[7]);
  1776. atp_writeb_io(dev, c, 0x18, satn[8]);
  1777. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1778. cpu_relax();
  1779. if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
  1780. continue;
  1781. while (atp_readb_io(dev, c, 0x17) != 0x8e)
  1782. cpu_relax();
  1783. try_u3:
  1784. j = 0;
  1785. atp_writeb_io(dev, c, 0x14, 0x09);
  1786. atp_writeb_io(dev, c, 0x18, 0x20);
  1787. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
  1788. if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
  1789. atp_writeb_io(dev, c, 0x19, u3[j++]);
  1790. cpu_relax();
  1791. }
  1792. while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
  1793. cpu_relax();
  1794. j = atp_readb_io(dev, c, 0x17) & 0x0f;
  1795. if (j == 0x0f) {
  1796. goto u3p_in;
  1797. }
  1798. if (j == 0x0a) {
  1799. goto u3p_cmd;
  1800. }
  1801. if (j == 0x0e) {
  1802. goto try_u3;
  1803. }
  1804. continue;
  1805. u3p_out:
  1806. atp_writeb_io(dev, c, 0x18, 0x20);
  1807. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
  1808. if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
  1809. atp_writeb_io(dev, c, 0x19, 0);
  1810. cpu_relax();
  1811. }
  1812. j = atp_readb_io(dev, c, 0x17) & 0x0f;
  1813. if (j == 0x0f) {
  1814. goto u3p_in;
  1815. }
  1816. if (j == 0x0a) {
  1817. goto u3p_cmd;
  1818. }
  1819. if (j == 0x0e) {
  1820. goto u3p_out;
  1821. }
  1822. continue;
  1823. u3p_in:
  1824. atp_writeb_io(dev, c, 0x14, 0x09);
  1825. atp_writeb_io(dev, c, 0x18, 0x20);
  1826. k = 0;
  1827. u3p_in1:
  1828. j = atp_readb_io(dev, c, 0x1f);
  1829. if ((j & 0x01) != 0) {
  1830. mbuf[k++] = atp_readb_io(dev, c, 0x19);
  1831. goto u3p_in1;
  1832. }
  1833. if ((j & 0x80) == 0x00) {
  1834. goto u3p_in1;
  1835. }
  1836. j = atp_readb_io(dev, c, 0x17) & 0x0f;
  1837. if (j == 0x0f) {
  1838. goto u3p_in;
  1839. }
  1840. if (j == 0x0a) {
  1841. goto u3p_cmd;
  1842. }
  1843. if (j == 0x0e) {
  1844. goto u3p_out;
  1845. }
  1846. continue;
  1847. u3p_cmd:
  1848. atp_writeb_io(dev, c, 0x10, 0x30);
  1849. atp_writeb_io(dev, c, 0x14, 0x00);
  1850. atp_writeb_io(dev, c, 0x18, 0x08);
  1851. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00);
  1852. j = atp_readb_io(dev, c, 0x17);
  1853. if (j != 0x16) {
  1854. if (j == 0x4e) {
  1855. goto u3p_out;
  1856. }
  1857. continue;
  1858. }
  1859. if (mbuf[0] != 0x01) {
  1860. goto chg_wide;
  1861. }
  1862. if (mbuf[1] != 0x06) {
  1863. goto chg_wide;
  1864. }
  1865. if (mbuf[2] != 0x04) {
  1866. goto chg_wide;
  1867. }
  1868. if (mbuf[3] == 0x09) {
  1869. m = 1;
  1870. m = m << i;
  1871. dev->wide_id[c] |= m;
  1872. dev->id[c][i].devsp = 0xce;
  1873. #ifdef ED_DBGP
  1874. printk("dev->id[%2d][%2d].devsp = %2x\n",
  1875. c, i, dev->id[c][i].devsp);
  1876. #endif
  1877. continue;
  1878. }
  1879. chg_wide:
  1880. atp_writeb_io(dev, c, 0x1b, 0x01);
  1881. atp_writeb_io(dev, c, 3, satn[0]);
  1882. atp_writeb_io(dev, c, 4, satn[1]);
  1883. atp_writeb_io(dev, c, 5, satn[2]);
  1884. atp_writeb_io(dev, c, 6, satn[3]);
  1885. atp_writeb_io(dev, c, 7, satn[4]);
  1886. atp_writeb_io(dev, c, 8, satn[5]);
  1887. atp_writeb_io(dev, c, 0x0f, 0);
  1888. atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
  1889. atp_writeb_io(dev, c, 0x12, 0);
  1890. atp_writeb_io(dev, c, 0x13, satn[6]);
  1891. atp_writeb_io(dev, c, 0x14, satn[7]);
  1892. atp_writeb_io(dev, c, 0x18, satn[8]);
  1893. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1894. cpu_relax();
  1895. if (atp_readb_io(dev, c, 0x17) != 0x11 &&
  1896. atp_readb_io(dev, c, 0x17) != 0x8e)
  1897. continue;
  1898. while (atp_readb_io(dev, c, 0x17) != 0x8e)
  1899. cpu_relax();
  1900. try_wide:
  1901. j = 0;
  1902. atp_writeb_io(dev, c, 0x14, 0x05);
  1903. atp_writeb_io(dev, c, 0x18, 0x20);
  1904. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
  1905. if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
  1906. atp_writeb_io(dev, c, 0x19, wide[j++]);
  1907. cpu_relax();
  1908. }
  1909. while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
  1910. cpu_relax();
  1911. j = atp_readb_io(dev, c, 0x17) & 0x0f;
  1912. if (j == 0x0f) {
  1913. goto widep_in;
  1914. }
  1915. if (j == 0x0a) {
  1916. goto widep_cmd;
  1917. }
  1918. if (j == 0x0e) {
  1919. goto try_wide;
  1920. }
  1921. continue;
  1922. widep_out:
  1923. atp_writeb_io(dev, c, 0x18, 0x20);
  1924. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
  1925. if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
  1926. atp_writeb_io(dev, c, 0x19, 0);
  1927. cpu_relax();
  1928. }
  1929. j = atp_readb_io(dev, c, 0x17) & 0x0f;
  1930. if (j == 0x0f) {
  1931. goto widep_in;
  1932. }
  1933. if (j == 0x0a) {
  1934. goto widep_cmd;
  1935. }
  1936. if (j == 0x0e) {
  1937. goto widep_out;
  1938. }
  1939. continue;
  1940. widep_in:
  1941. atp_writeb_io(dev, c, 0x14, 0xff);
  1942. atp_writeb_io(dev, c, 0x18, 0x20);
  1943. k = 0;
  1944. widep_in1:
  1945. j = atp_readb_io(dev, c, 0x1f);
  1946. if ((j & 0x01) != 0) {
  1947. mbuf[k++] = atp_readb_io(dev, c, 0x19);
  1948. goto widep_in1;
  1949. }
  1950. if ((j & 0x80) == 0x00) {
  1951. goto widep_in1;
  1952. }
  1953. j = atp_readb_io(dev, c, 0x17) & 0x0f;
  1954. if (j == 0x0f) {
  1955. goto widep_in;
  1956. }
  1957. if (j == 0x0a) {
  1958. goto widep_cmd;
  1959. }
  1960. if (j == 0x0e) {
  1961. goto widep_out;
  1962. }
  1963. continue;
  1964. widep_cmd:
  1965. atp_writeb_io(dev, c, 0x10, 0x30);
  1966. atp_writeb_io(dev, c, 0x14, 0x00);
  1967. atp_writeb_io(dev, c, 0x18, 0x08);
  1968. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1969. cpu_relax();
  1970. j = atp_readb_io(dev, c, 0x17);
  1971. if (j != 0x16) {
  1972. if (j == 0x4e) {
  1973. goto widep_out;
  1974. }
  1975. continue;
  1976. }
  1977. if (mbuf[0] != 0x01) {
  1978. goto not_wide;
  1979. }
  1980. if (mbuf[1] != 0x02) {
  1981. goto not_wide;
  1982. }
  1983. if (mbuf[2] != 0x03) {
  1984. goto not_wide;
  1985. }
  1986. if (mbuf[3] != 0x01) {
  1987. goto not_wide;
  1988. }
  1989. m = 1;
  1990. m = m << i;
  1991. dev->wide_id[c] |= m;
  1992. not_wide:
  1993. if ((dev->id[c][i].devtype == 0x00) ||
  1994. (dev->id[c][i].devtype == 0x07) ||
  1995. ((dev->id[c][i].devtype == 0x05) && ((n & 0x10) != 0))) {
  1996. m = 1;
  1997. m = m << i;
  1998. if ((dev->async[c] & m) != 0) {
  1999. goto set_sync;
  2000. }
  2001. }
  2002. continue;
  2003. set_sync:
  2004. if ((!is885(dev) && !is880(dev)) || (dev->sp[c][i] == 0x02)) {
  2005. synu[4] = 0x0c;
  2006. synuw[4] = 0x0c;
  2007. } else {
  2008. if (dev->sp[c][i] >= 0x03) {
  2009. synu[4] = 0x0a;
  2010. synuw[4] = 0x0a;
  2011. }
  2012. }
  2013. j = 0;
  2014. if ((m & dev->wide_id[c]) != 0) {
  2015. j |= 0x01;
  2016. }
  2017. atp_writeb_io(dev, c, 0x1b, j);
  2018. atp_writeb_io(dev, c, 3, satn[0]);
  2019. atp_writeb_io(dev, c, 4, satn[1]);
  2020. atp_writeb_io(dev, c, 5, satn[2]);
  2021. atp_writeb_io(dev, c, 6, satn[3]);
  2022. atp_writeb_io(dev, c, 7, satn[4]);
  2023. atp_writeb_io(dev, c, 8, satn[5]);
  2024. atp_writeb_io(dev, c, 0x0f, 0);
  2025. atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
  2026. atp_writeb_io(dev, c, 0x12, 0);
  2027. atp_writeb_io(dev, c, 0x13, satn[6]);
  2028. atp_writeb_io(dev, c, 0x14, satn[7]);
  2029. atp_writeb_io(dev, c, 0x18, satn[8]);
  2030. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  2031. cpu_relax();
  2032. if (atp_readb_io(dev, c, 0x17) != 0x11 &&
  2033. atp_readb_io(dev, c, 0x17) != 0x8e)
  2034. continue;
  2035. while (atp_readb_io(dev, c, 0x17) != 0x8e)
  2036. cpu_relax();
  2037. try_sync:
  2038. j = 0;
  2039. atp_writeb_io(dev, c, 0x14, 0x06);
  2040. atp_writeb_io(dev, c, 0x18, 0x20);
  2041. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
  2042. if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) {
  2043. if ((m & dev->wide_id[c]) != 0) {
  2044. if (is885(dev) || is880(dev)) {
  2045. if ((m & dev->ultra_map[c]) != 0) {
  2046. atp_writeb_io(dev, c, 0x19, synuw[j++]);
  2047. } else {
  2048. atp_writeb_io(dev, c, 0x19, synw[j++]);
  2049. }
  2050. } else
  2051. atp_writeb_io(dev, c, 0x19, synw_870[j++]);
  2052. } else {
  2053. if ((m & dev->ultra_map[c]) != 0) {
  2054. atp_writeb_io(dev, c, 0x19, synu[j++]);
  2055. } else {
  2056. atp_writeb_io(dev, c, 0x19, synn[j++]);
  2057. }
  2058. }
  2059. }
  2060. }
  2061. while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
  2062. cpu_relax();
  2063. j = atp_readb_io(dev, c, 0x17) & 0x0f;
  2064. if (j == 0x0f) {
  2065. goto phase_ins;
  2066. }
  2067. if (j == 0x0a) {
  2068. goto phase_cmds;
  2069. }
  2070. if (j == 0x0e) {
  2071. goto try_sync;
  2072. }
  2073. continue;
  2074. phase_outs:
  2075. atp_writeb_io(dev, c, 0x18, 0x20);
  2076. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) {
  2077. if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0x00)
  2078. atp_writeb_io(dev, c, 0x19, 0x00);
  2079. cpu_relax();
  2080. }
  2081. j = atp_readb_io(dev, c, 0x17);
  2082. if (j == 0x85) {
  2083. goto tar_dcons;
  2084. }
  2085. j &= 0x0f;
  2086. if (j == 0x0f) {
  2087. goto phase_ins;
  2088. }
  2089. if (j == 0x0a) {
  2090. goto phase_cmds;
  2091. }
  2092. if (j == 0x0e) {
  2093. goto phase_outs;
  2094. }
  2095. continue;
  2096. phase_ins:
  2097. if (is885(dev) || is880(dev))
  2098. atp_writeb_io(dev, c, 0x14, 0x06);
  2099. else
  2100. atp_writeb_io(dev, c, 0x14, 0xff);
  2101. atp_writeb_io(dev, c, 0x18, 0x20);
  2102. k = 0;
  2103. phase_ins1:
  2104. j = atp_readb_io(dev, c, 0x1f);
  2105. if ((j & 0x01) != 0x00) {
  2106. mbuf[k++] = atp_readb_io(dev, c, 0x19);
  2107. goto phase_ins1;
  2108. }
  2109. if ((j & 0x80) == 0x00) {
  2110. goto phase_ins1;
  2111. }
  2112. while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00);
  2113. j = atp_readb_io(dev, c, 0x17);
  2114. if (j == 0x85) {
  2115. goto tar_dcons;
  2116. }
  2117. j &= 0x0f;
  2118. if (j == 0x0f) {
  2119. goto phase_ins;
  2120. }
  2121. if (j == 0x0a) {
  2122. goto phase_cmds;
  2123. }
  2124. if (j == 0x0e) {
  2125. goto phase_outs;
  2126. }
  2127. continue;
  2128. phase_cmds:
  2129. atp_writeb_io(dev, c, 0x10, 0x30);
  2130. tar_dcons:
  2131. atp_writeb_io(dev, c, 0x14, 0x00);
  2132. atp_writeb_io(dev, c, 0x18, 0x08);
  2133. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  2134. cpu_relax();
  2135. j = atp_readb_io(dev, c, 0x17);
  2136. if (j != 0x16) {
  2137. continue;
  2138. }
  2139. if (mbuf[0] != 0x01) {
  2140. continue;
  2141. }
  2142. if (mbuf[1] != 0x03) {
  2143. continue;
  2144. }
  2145. if (mbuf[4] == 0x00) {
  2146. continue;
  2147. }
  2148. if (mbuf[3] > 0x64) {
  2149. continue;
  2150. }
  2151. if (is885(dev) || is880(dev)) {
  2152. if (mbuf[4] > 0x0e) {
  2153. mbuf[4] = 0x0e;
  2154. }
  2155. } else {
  2156. if (mbuf[4] > 0x0c) {
  2157. mbuf[4] = 0x0c;
  2158. }
  2159. }
  2160. dev->id[c][i].devsp = mbuf[4];
  2161. if (is885(dev) || is880(dev))
  2162. if (mbuf[3] < 0x0c) {
  2163. j = 0xb0;
  2164. goto set_syn_ok;
  2165. }
  2166. if ((mbuf[3] < 0x0d) && (rmb == 0)) {
  2167. j = 0xa0;
  2168. goto set_syn_ok;
  2169. }
  2170. if (mbuf[3] < 0x1a) {
  2171. j = 0x20;
  2172. goto set_syn_ok;
  2173. }
  2174. if (mbuf[3] < 0x33) {
  2175. j = 0x40;
  2176. goto set_syn_ok;
  2177. }
  2178. if (mbuf[3] < 0x4c) {
  2179. j = 0x50;
  2180. goto set_syn_ok;
  2181. }
  2182. j = 0x60;
  2183. set_syn_ok:
  2184. dev->id[c][i].devsp = (dev->id[c][i].devsp & 0x0f) | j;
  2185. #ifdef ED_DBGP
  2186. printk("dev->id[%2d][%2d].devsp = %2x\n",
  2187. c,i,dev->id[c][i].devsp);
  2188. #endif
  2189. }
  2190. }