qla_mr.c 89 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * QLogic Fibre Channel HBA Driver
  4. * Copyright (c) 2003-2014 QLogic Corporation
  5. */
  6. #include "qla_def.h"
  7. #include <linux/delay.h>
  8. #include <linux/ktime.h>
  9. #include <linux/pci.h>
  10. #include <linux/ratelimit.h>
  11. #include <linux/vmalloc.h>
  12. #include <scsi/scsi_tcq.h>
  13. #include <linux/utsname.h>
  14. /* QLAFX00 specific Mailbox implementation functions */
  15. /*
  16. * qlafx00_mailbox_command
  17. * Issue mailbox command and waits for completion.
  18. *
  19. * Input:
  20. * ha = adapter block pointer.
  21. * mcp = driver internal mbx struct pointer.
  22. *
  23. * Output:
  24. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  25. *
  26. * Returns:
  27. * 0 : QLA_SUCCESS = cmd performed success
  28. * 1 : QLA_FUNCTION_FAILED (error encountered)
  29. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  30. *
  31. * Context:
  32. * Kernel context.
  33. */
  34. static int
  35. qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
  36. {
  37. int rval;
  38. unsigned long flags = 0;
  39. device_reg_t *reg;
  40. uint8_t abort_active;
  41. uint8_t io_lock_on;
  42. uint16_t command = 0;
  43. uint32_t *iptr;
  44. __le32 __iomem *optr;
  45. uint32_t cnt;
  46. uint32_t mboxes;
  47. unsigned long wait_time;
  48. struct qla_hw_data *ha = vha->hw;
  49. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  50. if (ha->pdev->error_state == pci_channel_io_perm_failure) {
  51. ql_log(ql_log_warn, vha, 0x115c,
  52. "PCI channel failed permanently, exiting.\n");
  53. return QLA_FUNCTION_TIMEOUT;
  54. }
  55. if (vha->device_flags & DFLG_DEV_FAILED) {
  56. ql_log(ql_log_warn, vha, 0x115f,
  57. "Device in failed state, exiting.\n");
  58. return QLA_FUNCTION_TIMEOUT;
  59. }
  60. reg = ha->iobase;
  61. io_lock_on = base_vha->flags.init_done;
  62. rval = QLA_SUCCESS;
  63. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  64. if (ha->flags.pci_channel_io_perm_failure) {
  65. ql_log(ql_log_warn, vha, 0x1175,
  66. "Perm failure on EEH timeout MBX, exiting.\n");
  67. return QLA_FUNCTION_TIMEOUT;
  68. }
  69. if (ha->flags.isp82xx_fw_hung) {
  70. /* Setting Link-Down error */
  71. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  72. ql_log(ql_log_warn, vha, 0x1176,
  73. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  74. rval = QLA_FUNCTION_FAILED;
  75. goto premature_exit;
  76. }
  77. /*
  78. * Wait for active mailbox commands to finish by waiting at most tov
  79. * seconds. This is to serialize actual issuing of mailbox cmds during
  80. * non ISP abort time.
  81. */
  82. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  83. /* Timeout occurred. Return error. */
  84. ql_log(ql_log_warn, vha, 0x1177,
  85. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  86. mcp->mb[0]);
  87. return QLA_FUNCTION_TIMEOUT;
  88. }
  89. ha->flags.mbox_busy = 1;
  90. /* Save mailbox command for debug */
  91. ha->mcp32 = mcp;
  92. ql_dbg(ql_dbg_mbx, vha, 0x1178,
  93. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  94. spin_lock_irqsave(&ha->hardware_lock, flags);
  95. /* Load mailbox registers. */
  96. optr = &reg->ispfx00.mailbox0;
  97. iptr = mcp->mb;
  98. command = mcp->mb[0];
  99. mboxes = mcp->out_mb;
  100. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  101. if (mboxes & BIT_0)
  102. wrt_reg_dword(optr, *iptr);
  103. mboxes >>= 1;
  104. optr++;
  105. iptr++;
  106. }
  107. /* Issue set host interrupt command to send cmd out. */
  108. ha->flags.mbox_int = 0;
  109. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  110. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
  111. (uint8_t *)mcp->mb, 16);
  112. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
  113. ((uint8_t *)mcp->mb + 0x10), 16);
  114. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
  115. ((uint8_t *)mcp->mb + 0x20), 8);
  116. /* Unlock mbx registers and wait for interrupt */
  117. ql_dbg(ql_dbg_mbx, vha, 0x1179,
  118. "Going to unlock irq & waiting for interrupts. "
  119. "jiffies=%lx.\n", jiffies);
  120. /* Wait for mbx cmd completion until timeout */
  121. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  122. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  123. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  124. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  125. WARN_ON_ONCE(wait_for_completion_timeout(&ha->mbx_intr_comp,
  126. mcp->tov * HZ) != 0);
  127. } else {
  128. ql_dbg(ql_dbg_mbx, vha, 0x112c,
  129. "Cmd=%x Polling Mode.\n", command);
  130. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  131. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  132. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  133. while (!ha->flags.mbox_int) {
  134. if (time_after(jiffies, wait_time))
  135. break;
  136. /* Check for pending interrupts. */
  137. qla2x00_poll(ha->rsp_q_map[0]);
  138. if (!ha->flags.mbox_int &&
  139. !(IS_QLA2200(ha) &&
  140. command == MBC_LOAD_RISC_RAM_EXTENDED))
  141. usleep_range(10000, 11000);
  142. } /* while */
  143. ql_dbg(ql_dbg_mbx, vha, 0x112d,
  144. "Waited %d sec.\n",
  145. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  146. }
  147. /* Check whether we timed out */
  148. if (ha->flags.mbox_int) {
  149. uint32_t *iptr2;
  150. ql_dbg(ql_dbg_mbx, vha, 0x112e,
  151. "Cmd=%x completed.\n", command);
  152. /* Got interrupt. Clear the flag. */
  153. ha->flags.mbox_int = 0;
  154. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  155. if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
  156. rval = QLA_FUNCTION_FAILED;
  157. /* Load return mailbox registers. */
  158. iptr2 = mcp->mb;
  159. iptr = (uint32_t *)&ha->mailbox_out32[0];
  160. mboxes = mcp->in_mb;
  161. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  162. if (mboxes & BIT_0)
  163. *iptr2 = *iptr;
  164. mboxes >>= 1;
  165. iptr2++;
  166. iptr++;
  167. }
  168. } else {
  169. rval = QLA_FUNCTION_TIMEOUT;
  170. }
  171. ha->flags.mbox_busy = 0;
  172. /* Clean up */
  173. ha->mcp32 = NULL;
  174. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  175. ql_dbg(ql_dbg_mbx, vha, 0x113a,
  176. "checking for additional resp interrupt.\n");
  177. /* polling mode for non isp_abort commands. */
  178. qla2x00_poll(ha->rsp_q_map[0]);
  179. }
  180. if (rval == QLA_FUNCTION_TIMEOUT &&
  181. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  182. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  183. ha->flags.eeh_busy) {
  184. /* not in dpc. schedule it for dpc to take over. */
  185. ql_dbg(ql_dbg_mbx, vha, 0x115d,
  186. "Timeout, schedule isp_abort_needed.\n");
  187. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  188. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  189. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  190. ql_log(ql_log_info, base_vha, 0x115e,
  191. "Mailbox cmd timeout occurred, cmd=0x%x, "
  192. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  193. "abort.\n", command, mcp->mb[0],
  194. ha->flags.eeh_busy);
  195. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  196. qla2xxx_wake_dpc(vha);
  197. }
  198. } else if (!abort_active) {
  199. /* call abort directly since we are in the DPC thread */
  200. ql_dbg(ql_dbg_mbx, vha, 0x1160,
  201. "Timeout, calling abort_isp.\n");
  202. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  203. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  204. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  205. ql_log(ql_log_info, base_vha, 0x1161,
  206. "Mailbox cmd timeout occurred, cmd=0x%x, "
  207. "mb[0]=0x%x. Scheduling ISP abort ",
  208. command, mcp->mb[0]);
  209. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  210. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  211. if (ha->isp_ops->abort_isp(vha)) {
  212. /* Failed. retry later. */
  213. set_bit(ISP_ABORT_NEEDED,
  214. &vha->dpc_flags);
  215. }
  216. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  217. ql_dbg(ql_dbg_mbx, vha, 0x1162,
  218. "Finished abort_isp.\n");
  219. }
  220. }
  221. }
  222. premature_exit:
  223. /* Allow next mbx cmd to come in. */
  224. complete(&ha->mbx_cmd_comp);
  225. if (rval) {
  226. ql_log(ql_log_warn, base_vha, 0x1163,
  227. "**** Failed=%x mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
  228. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
  229. command);
  230. } else {
  231. ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
  232. }
  233. return rval;
  234. }
  235. /*
  236. * qlafx00_driver_shutdown
  237. * Indicate a driver shutdown to firmware.
  238. *
  239. * Input:
  240. * ha = adapter block pointer.
  241. *
  242. * Returns:
  243. * local function return status code.
  244. *
  245. * Context:
  246. * Kernel context.
  247. */
  248. int
  249. qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
  250. {
  251. int rval;
  252. struct mbx_cmd_32 mc;
  253. struct mbx_cmd_32 *mcp = &mc;
  254. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
  255. "Entered %s.\n", __func__);
  256. mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
  257. mcp->out_mb = MBX_0;
  258. mcp->in_mb = MBX_0;
  259. if (tmo)
  260. mcp->tov = tmo;
  261. else
  262. mcp->tov = MBX_TOV_SECONDS;
  263. mcp->flags = 0;
  264. rval = qlafx00_mailbox_command(vha, mcp);
  265. if (rval != QLA_SUCCESS) {
  266. ql_dbg(ql_dbg_mbx, vha, 0x1167,
  267. "Failed=%x.\n", rval);
  268. } else {
  269. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
  270. "Done %s.\n", __func__);
  271. }
  272. return rval;
  273. }
  274. /*
  275. * qlafx00_get_firmware_state
  276. * Get adapter firmware state.
  277. *
  278. * Input:
  279. * ha = adapter block pointer.
  280. * TARGET_QUEUE_LOCK must be released.
  281. * ADAPTER_STATE_LOCK must be released.
  282. *
  283. * Returns:
  284. * qla7xxx local function return status code.
  285. *
  286. * Context:
  287. * Kernel context.
  288. */
  289. static int
  290. qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
  291. {
  292. int rval;
  293. struct mbx_cmd_32 mc;
  294. struct mbx_cmd_32 *mcp = &mc;
  295. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
  296. "Entered %s.\n", __func__);
  297. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  298. mcp->out_mb = MBX_0;
  299. mcp->in_mb = MBX_1|MBX_0;
  300. mcp->tov = MBX_TOV_SECONDS;
  301. mcp->flags = 0;
  302. rval = qlafx00_mailbox_command(vha, mcp);
  303. /* Return firmware states. */
  304. states[0] = mcp->mb[1];
  305. if (rval != QLA_SUCCESS) {
  306. ql_dbg(ql_dbg_mbx, vha, 0x116a,
  307. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  308. } else {
  309. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
  310. "Done %s.\n", __func__);
  311. }
  312. return rval;
  313. }
  314. /*
  315. * qlafx00_init_firmware
  316. * Initialize adapter firmware.
  317. *
  318. * Input:
  319. * ha = adapter block pointer.
  320. * dptr = Initialization control block pointer.
  321. * size = size of initialization control block.
  322. * TARGET_QUEUE_LOCK must be released.
  323. * ADAPTER_STATE_LOCK must be released.
  324. *
  325. * Returns:
  326. * qlafx00 local function return status code.
  327. *
  328. * Context:
  329. * Kernel context.
  330. */
  331. int
  332. qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  333. {
  334. int rval;
  335. struct mbx_cmd_32 mc;
  336. struct mbx_cmd_32 *mcp = &mc;
  337. struct qla_hw_data *ha = vha->hw;
  338. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
  339. "Entered %s.\n", __func__);
  340. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  341. mcp->mb[1] = 0;
  342. mcp->mb[2] = MSD(ha->init_cb_dma);
  343. mcp->mb[3] = LSD(ha->init_cb_dma);
  344. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  345. mcp->in_mb = MBX_0;
  346. mcp->buf_size = size;
  347. mcp->flags = MBX_DMA_OUT;
  348. mcp->tov = MBX_TOV_SECONDS;
  349. rval = qlafx00_mailbox_command(vha, mcp);
  350. if (rval != QLA_SUCCESS) {
  351. ql_dbg(ql_dbg_mbx, vha, 0x116d,
  352. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  353. } else {
  354. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
  355. "Done %s.\n", __func__);
  356. }
  357. return rval;
  358. }
  359. /*
  360. * qlafx00_mbx_reg_test
  361. */
  362. static int
  363. qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
  364. {
  365. int rval;
  366. struct mbx_cmd_32 mc;
  367. struct mbx_cmd_32 *mcp = &mc;
  368. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
  369. "Entered %s.\n", __func__);
  370. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  371. mcp->mb[1] = 0xAAAA;
  372. mcp->mb[2] = 0x5555;
  373. mcp->mb[3] = 0xAA55;
  374. mcp->mb[4] = 0x55AA;
  375. mcp->mb[5] = 0xA5A5;
  376. mcp->mb[6] = 0x5A5A;
  377. mcp->mb[7] = 0x2525;
  378. mcp->mb[8] = 0xBBBB;
  379. mcp->mb[9] = 0x6666;
  380. mcp->mb[10] = 0xBB66;
  381. mcp->mb[11] = 0x66BB;
  382. mcp->mb[12] = 0xB6B6;
  383. mcp->mb[13] = 0x6B6B;
  384. mcp->mb[14] = 0x3636;
  385. mcp->mb[15] = 0xCCCC;
  386. mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  387. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  388. mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  389. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  390. mcp->buf_size = 0;
  391. mcp->flags = MBX_DMA_OUT;
  392. mcp->tov = MBX_TOV_SECONDS;
  393. rval = qlafx00_mailbox_command(vha, mcp);
  394. if (rval == QLA_SUCCESS) {
  395. if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
  396. mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
  397. rval = QLA_FUNCTION_FAILED;
  398. if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
  399. mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
  400. rval = QLA_FUNCTION_FAILED;
  401. if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
  402. mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
  403. rval = QLA_FUNCTION_FAILED;
  404. if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
  405. mcp->mb[31] != 0xCCCC)
  406. rval = QLA_FUNCTION_FAILED;
  407. }
  408. if (rval != QLA_SUCCESS) {
  409. ql_dbg(ql_dbg_mbx, vha, 0x1170,
  410. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  411. } else {
  412. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
  413. "Done %s.\n", __func__);
  414. }
  415. return rval;
  416. }
  417. /**
  418. * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers.
  419. * @vha: HA context
  420. *
  421. * Returns 0 on success.
  422. */
  423. int
  424. qlafx00_pci_config(scsi_qla_host_t *vha)
  425. {
  426. uint16_t w;
  427. struct qla_hw_data *ha = vha->hw;
  428. pci_set_master(ha->pdev);
  429. pci_try_set_mwi(ha->pdev);
  430. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  431. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  432. w &= ~PCI_COMMAND_INTX_DISABLE;
  433. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  434. /* PCIe -- adjust Maximum Read Request Size (2048). */
  435. if (pci_is_pcie(ha->pdev))
  436. pcie_set_readrq(ha->pdev, 2048);
  437. ha->chip_revision = ha->pdev->revision;
  438. return QLA_SUCCESS;
  439. }
  440. /**
  441. * qlafx00_soc_cpu_reset() - Perform warm reset of iSA(CPUs being reset on SOC).
  442. * @vha: HA context
  443. *
  444. */
  445. static inline void
  446. qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
  447. {
  448. unsigned long flags = 0;
  449. struct qla_hw_data *ha = vha->hw;
  450. int i, core;
  451. uint32_t cnt;
  452. uint32_t reg_val;
  453. spin_lock_irqsave(&ha->hardware_lock, flags);
  454. QLAFX00_SET_HBA_SOC_REG(ha, 0x80004, 0);
  455. QLAFX00_SET_HBA_SOC_REG(ha, 0x82004, 0);
  456. /* stop the XOR DMA engines */
  457. QLAFX00_SET_HBA_SOC_REG(ha, 0x60920, 0x02);
  458. QLAFX00_SET_HBA_SOC_REG(ha, 0x60924, 0x02);
  459. QLAFX00_SET_HBA_SOC_REG(ha, 0xf0920, 0x02);
  460. QLAFX00_SET_HBA_SOC_REG(ha, 0xf0924, 0x02);
  461. /* stop the IDMA engines */
  462. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840);
  463. reg_val &= ~(1<<12);
  464. QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val);
  465. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844);
  466. reg_val &= ~(1<<12);
  467. QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val);
  468. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848);
  469. reg_val &= ~(1<<12);
  470. QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val);
  471. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C);
  472. reg_val &= ~(1<<12);
  473. QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val);
  474. for (i = 0; i < 100000; i++) {
  475. if ((QLAFX00_GET_HBA_SOC_REG(ha, 0xd0000) & 0x10000000) == 0 &&
  476. (QLAFX00_GET_HBA_SOC_REG(ha, 0x10600) & 0x1) == 0)
  477. break;
  478. udelay(100);
  479. }
  480. /* Set all 4 cores in reset */
  481. for (i = 0; i < 4; i++) {
  482. QLAFX00_SET_HBA_SOC_REG(ha,
  483. (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
  484. QLAFX00_SET_HBA_SOC_REG(ha,
  485. (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
  486. }
  487. /* Reset all units in Fabric */
  488. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x011f0101));
  489. /* */
  490. QLAFX00_SET_HBA_SOC_REG(ha, 0x10610, 1);
  491. QLAFX00_SET_HBA_SOC_REG(ha, 0x10600, 0);
  492. /* Set all 4 core Memory Power Down Registers */
  493. for (i = 0; i < 5; i++) {
  494. QLAFX00_SET_HBA_SOC_REG(ha,
  495. (SOC_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i), (0x0));
  496. }
  497. /* Reset all interrupt control registers */
  498. for (i = 0; i < 115; i++) {
  499. QLAFX00_SET_HBA_SOC_REG(ha,
  500. (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
  501. }
  502. /* Reset Timers control registers. per core */
  503. for (core = 0; core < 4; core++)
  504. for (i = 0; i < 8; i++)
  505. QLAFX00_SET_HBA_SOC_REG(ha,
  506. (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
  507. /* Reset per core IRQ ack register */
  508. for (core = 0; core < 4; core++)
  509. QLAFX00_SET_HBA_SOC_REG(ha,
  510. (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
  511. /* Set Fabric control and config to defaults */
  512. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
  513. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
  514. /* Kick in Fabric units */
  515. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
  516. /* Kick in Core0 to start boot process */
  517. QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
  518. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  519. /* Wait 10secs for soft-reset to complete. */
  520. for (cnt = 10; cnt; cnt--) {
  521. msleep(1000);
  522. barrier();
  523. }
  524. }
  525. /**
  526. * qlafx00_soft_reset() - Soft Reset ISPFx00.
  527. * @vha: HA context
  528. *
  529. * Returns 0 on success.
  530. */
  531. int
  532. qlafx00_soft_reset(scsi_qla_host_t *vha)
  533. {
  534. struct qla_hw_data *ha = vha->hw;
  535. int rval = QLA_FUNCTION_FAILED;
  536. if (unlikely(pci_channel_offline(ha->pdev) &&
  537. ha->flags.pci_channel_io_perm_failure))
  538. return rval;
  539. ha->isp_ops->disable_intrs(ha);
  540. qlafx00_soc_cpu_reset(vha);
  541. return QLA_SUCCESS;
  542. }
  543. /**
  544. * qlafx00_chip_diag() - Test ISPFx00 for proper operation.
  545. * @vha: HA context
  546. *
  547. * Returns 0 on success.
  548. */
  549. int
  550. qlafx00_chip_diag(scsi_qla_host_t *vha)
  551. {
  552. int rval = 0;
  553. struct qla_hw_data *ha = vha->hw;
  554. struct req_que *req = ha->req_q_map[0];
  555. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  556. rval = qlafx00_mbx_reg_test(vha);
  557. if (rval) {
  558. ql_log(ql_log_warn, vha, 0x1165,
  559. "Failed mailbox send register test\n");
  560. } else {
  561. /* Flag a successful rval */
  562. rval = QLA_SUCCESS;
  563. }
  564. return rval;
  565. }
  566. void
  567. qlafx00_config_rings(struct scsi_qla_host *vha)
  568. {
  569. struct qla_hw_data *ha = vha->hw;
  570. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  571. wrt_reg_dword(&reg->req_q_in, 0);
  572. wrt_reg_dword(&reg->req_q_out, 0);
  573. wrt_reg_dword(&reg->rsp_q_in, 0);
  574. wrt_reg_dword(&reg->rsp_q_out, 0);
  575. /* PCI posting */
  576. rd_reg_dword(&reg->rsp_q_out);
  577. }
  578. char *
  579. qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
  580. {
  581. struct qla_hw_data *ha = vha->hw;
  582. if (pci_is_pcie(ha->pdev))
  583. strscpy(str, "PCIe iSA", str_len);
  584. return str;
  585. }
  586. char *
  587. qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
  588. {
  589. struct qla_hw_data *ha = vha->hw;
  590. snprintf(str, size, "%s", ha->mr.fw_version);
  591. return str;
  592. }
  593. void
  594. qlafx00_enable_intrs(struct qla_hw_data *ha)
  595. {
  596. unsigned long flags = 0;
  597. spin_lock_irqsave(&ha->hardware_lock, flags);
  598. ha->interrupts_on = 1;
  599. QLAFX00_ENABLE_ICNTRL_REG(ha);
  600. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  601. }
  602. void
  603. qlafx00_disable_intrs(struct qla_hw_data *ha)
  604. {
  605. unsigned long flags = 0;
  606. spin_lock_irqsave(&ha->hardware_lock, flags);
  607. ha->interrupts_on = 0;
  608. QLAFX00_DISABLE_ICNTRL_REG(ha);
  609. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  610. }
  611. int
  612. qlafx00_abort_target(fc_port_t *fcport, uint64_t l, int tag)
  613. {
  614. return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  615. }
  616. int
  617. qlafx00_lun_reset(fc_port_t *fcport, uint64_t l, int tag)
  618. {
  619. return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  620. }
  621. int
  622. qlafx00_iospace_config(struct qla_hw_data *ha)
  623. {
  624. if (pci_request_selected_regions(ha->pdev, ha->bars,
  625. QLA2XXX_DRIVER_NAME)) {
  626. ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
  627. "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
  628. pci_name(ha->pdev));
  629. goto iospace_error_exit;
  630. }
  631. /* Use MMIO operations for all accesses. */
  632. if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
  633. ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
  634. "Invalid pci I/O region size (%s).\n",
  635. pci_name(ha->pdev));
  636. goto iospace_error_exit;
  637. }
  638. if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
  639. ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
  640. "Invalid PCI mem BAR0 region size (%s), aborting\n",
  641. pci_name(ha->pdev));
  642. goto iospace_error_exit;
  643. }
  644. ha->cregbase =
  645. ioremap(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
  646. if (!ha->cregbase) {
  647. ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
  648. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  649. goto iospace_error_exit;
  650. }
  651. if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
  652. ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
  653. "region #2 not an MMIO resource (%s), aborting\n",
  654. pci_name(ha->pdev));
  655. goto iospace_error_exit;
  656. }
  657. if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
  658. ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
  659. "Invalid PCI mem BAR2 region size (%s), aborting\n",
  660. pci_name(ha->pdev));
  661. goto iospace_error_exit;
  662. }
  663. ha->iobase =
  664. ioremap(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
  665. if (!ha->iobase) {
  666. ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
  667. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  668. goto iospace_error_exit;
  669. }
  670. /* Determine queue resources */
  671. ha->max_req_queues = ha->max_rsp_queues = 1;
  672. ql_log_pci(ql_log_info, ha->pdev, 0x012c,
  673. "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
  674. ha->bars, ha->cregbase, ha->iobase);
  675. return 0;
  676. iospace_error_exit:
  677. return -ENOMEM;
  678. }
  679. static void
  680. qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
  681. {
  682. struct qla_hw_data *ha = vha->hw;
  683. struct req_que *req = ha->req_q_map[0];
  684. struct rsp_que *rsp = ha->rsp_q_map[0];
  685. req->length_fx00 = req->length;
  686. req->ring_fx00 = req->ring;
  687. req->dma_fx00 = req->dma;
  688. rsp->length_fx00 = rsp->length;
  689. rsp->ring_fx00 = rsp->ring;
  690. rsp->dma_fx00 = rsp->dma;
  691. ql_dbg(ql_dbg_init, vha, 0x012d,
  692. "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
  693. "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
  694. req->length_fx00, (u64)req->dma_fx00);
  695. ql_dbg(ql_dbg_init, vha, 0x012e,
  696. "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
  697. "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
  698. rsp->length_fx00, (u64)rsp->dma_fx00);
  699. }
  700. static int
  701. qlafx00_config_queues(struct scsi_qla_host *vha)
  702. {
  703. struct qla_hw_data *ha = vha->hw;
  704. struct req_que *req = ha->req_q_map[0];
  705. struct rsp_que *rsp = ha->rsp_q_map[0];
  706. dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
  707. req->length = ha->req_que_len;
  708. req->ring = (void __force *)ha->iobase + ha->req_que_off;
  709. req->dma = bar2_hdl + ha->req_que_off;
  710. if ((!req->ring) || (req->length == 0)) {
  711. ql_log_pci(ql_log_info, ha->pdev, 0x012f,
  712. "Unable to allocate memory for req_ring\n");
  713. return QLA_FUNCTION_FAILED;
  714. }
  715. ql_dbg(ql_dbg_init, vha, 0x0130,
  716. "req: %p req_ring pointer %p req len 0x%x "
  717. "req off 0x%x\n, req->dma: 0x%llx",
  718. req, req->ring, req->length,
  719. ha->req_que_off, (u64)req->dma);
  720. rsp->length = ha->rsp_que_len;
  721. rsp->ring = (void __force *)ha->iobase + ha->rsp_que_off;
  722. rsp->dma = bar2_hdl + ha->rsp_que_off;
  723. if ((!rsp->ring) || (rsp->length == 0)) {
  724. ql_log_pci(ql_log_info, ha->pdev, 0x0131,
  725. "Unable to allocate memory for rsp_ring\n");
  726. return QLA_FUNCTION_FAILED;
  727. }
  728. ql_dbg(ql_dbg_init, vha, 0x0132,
  729. "rsp: %p rsp_ring pointer %p rsp len 0x%x "
  730. "rsp off 0x%x, rsp->dma: 0x%llx\n",
  731. rsp, rsp->ring, rsp->length,
  732. ha->rsp_que_off, (u64)rsp->dma);
  733. return QLA_SUCCESS;
  734. }
  735. static int
  736. qlafx00_init_fw_ready(scsi_qla_host_t *vha)
  737. {
  738. int rval = 0;
  739. unsigned long wtime;
  740. uint16_t wait_time; /* Wait time */
  741. struct qla_hw_data *ha = vha->hw;
  742. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  743. uint32_t aenmbx, aenmbx7 = 0;
  744. uint32_t pseudo_aen;
  745. uint32_t state[5];
  746. bool done = false;
  747. /* 30 seconds wait - Adjust if required */
  748. wait_time = 30;
  749. pseudo_aen = rd_reg_dword(&reg->pseudoaen);
  750. if (pseudo_aen == 1) {
  751. aenmbx7 = rd_reg_dword(&reg->initval7);
  752. ha->mbx_intr_code = MSW(aenmbx7);
  753. ha->rqstq_intr_code = LSW(aenmbx7);
  754. rval = qlafx00_driver_shutdown(vha, 10);
  755. if (rval != QLA_SUCCESS)
  756. qlafx00_soft_reset(vha);
  757. }
  758. /* wait time before firmware ready */
  759. wtime = jiffies + (wait_time * HZ);
  760. do {
  761. aenmbx = rd_reg_dword(&reg->aenmailbox0);
  762. barrier();
  763. ql_dbg(ql_dbg_mbx, vha, 0x0133,
  764. "aenmbx: 0x%x\n", aenmbx);
  765. switch (aenmbx) {
  766. case MBA_FW_NOT_STARTED:
  767. case MBA_FW_STARTING:
  768. break;
  769. case MBA_SYSTEM_ERR:
  770. case MBA_REQ_TRANSFER_ERR:
  771. case MBA_RSP_TRANSFER_ERR:
  772. case MBA_FW_INIT_FAILURE:
  773. qlafx00_soft_reset(vha);
  774. break;
  775. case MBA_FW_RESTART_CMPLT:
  776. /* Set the mbx and rqstq intr code */
  777. aenmbx7 = rd_reg_dword(&reg->aenmailbox7);
  778. ha->mbx_intr_code = MSW(aenmbx7);
  779. ha->rqstq_intr_code = LSW(aenmbx7);
  780. ha->req_que_off = rd_reg_dword(&reg->aenmailbox1);
  781. ha->rsp_que_off = rd_reg_dword(&reg->aenmailbox3);
  782. ha->req_que_len = rd_reg_dword(&reg->aenmailbox5);
  783. ha->rsp_que_len = rd_reg_dword(&reg->aenmailbox6);
  784. wrt_reg_dword(&reg->aenmailbox0, 0);
  785. rd_reg_dword_relaxed(&reg->aenmailbox0);
  786. ql_dbg(ql_dbg_init, vha, 0x0134,
  787. "f/w returned mbx_intr_code: 0x%x, "
  788. "rqstq_intr_code: 0x%x\n",
  789. ha->mbx_intr_code, ha->rqstq_intr_code);
  790. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  791. rval = QLA_SUCCESS;
  792. done = true;
  793. break;
  794. default:
  795. if ((aenmbx & 0xFF00) == MBA_FW_INIT_INPROGRESS)
  796. break;
  797. /* If fw is apparently not ready. In order to continue,
  798. * we might need to issue Mbox cmd, but the problem is
  799. * that the DoorBell vector values that come with the
  800. * 8060 AEN are most likely gone by now (and thus no
  801. * bell would be rung on the fw side when mbox cmd is
  802. * issued). We have to therefore grab the 8060 AEN
  803. * shadow regs (filled in by FW when the last 8060
  804. * AEN was being posted).
  805. * Do the following to determine what is needed in
  806. * order to get the FW ready:
  807. * 1. reload the 8060 AEN values from the shadow regs
  808. * 2. clear int status to get rid of possible pending
  809. * interrupts
  810. * 3. issue Get FW State Mbox cmd to determine fw state
  811. * Set the mbx and rqstq intr code from Shadow Regs
  812. */
  813. aenmbx7 = rd_reg_dword(&reg->initval7);
  814. ha->mbx_intr_code = MSW(aenmbx7);
  815. ha->rqstq_intr_code = LSW(aenmbx7);
  816. ha->req_que_off = rd_reg_dword(&reg->initval1);
  817. ha->rsp_que_off = rd_reg_dword(&reg->initval3);
  818. ha->req_que_len = rd_reg_dword(&reg->initval5);
  819. ha->rsp_que_len = rd_reg_dword(&reg->initval6);
  820. ql_dbg(ql_dbg_init, vha, 0x0135,
  821. "f/w returned mbx_intr_code: 0x%x, "
  822. "rqstq_intr_code: 0x%x\n",
  823. ha->mbx_intr_code, ha->rqstq_intr_code);
  824. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  825. /* Get the FW state */
  826. rval = qlafx00_get_firmware_state(vha, state);
  827. if (rval != QLA_SUCCESS) {
  828. /* Retry if timer has not expired */
  829. break;
  830. }
  831. if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
  832. /* Firmware is waiting to be
  833. * initialized by driver
  834. */
  835. rval = QLA_SUCCESS;
  836. done = true;
  837. break;
  838. }
  839. /* Issue driver shutdown and wait until f/w recovers.
  840. * Driver should continue to poll until 8060 AEN is
  841. * received indicating firmware recovery.
  842. */
  843. ql_dbg(ql_dbg_init, vha, 0x0136,
  844. "Sending Driver shutdown fw_state 0x%x\n",
  845. state[0]);
  846. rval = qlafx00_driver_shutdown(vha, 10);
  847. if (rval != QLA_SUCCESS) {
  848. rval = QLA_FUNCTION_FAILED;
  849. break;
  850. }
  851. msleep(500);
  852. wtime = jiffies + (wait_time * HZ);
  853. break;
  854. }
  855. if (!done) {
  856. if (time_after_eq(jiffies, wtime)) {
  857. ql_dbg(ql_dbg_init, vha, 0x0137,
  858. "Init f/w failed: aen[7]: 0x%x\n",
  859. rd_reg_dword(&reg->aenmailbox7));
  860. rval = QLA_FUNCTION_FAILED;
  861. done = true;
  862. break;
  863. }
  864. /* Delay for a while */
  865. msleep(500);
  866. }
  867. } while (!done);
  868. if (rval)
  869. ql_dbg(ql_dbg_init, vha, 0x0138,
  870. "%s **** FAILED ****.\n", __func__);
  871. else
  872. ql_dbg(ql_dbg_init, vha, 0x0139,
  873. "%s **** SUCCESS ****.\n", __func__);
  874. return rval;
  875. }
  876. /*
  877. * qlafx00_fw_ready() - Waits for firmware ready.
  878. * @ha: HA context
  879. *
  880. * Returns 0 on success.
  881. */
  882. int
  883. qlafx00_fw_ready(scsi_qla_host_t *vha)
  884. {
  885. int rval;
  886. unsigned long wtime;
  887. uint16_t wait_time; /* Wait time if loop is coming ready */
  888. uint32_t state[5];
  889. rval = QLA_SUCCESS;
  890. wait_time = 10;
  891. /* wait time before firmware ready */
  892. wtime = jiffies + (wait_time * HZ);
  893. /* Wait for ISP to finish init */
  894. if (!vha->flags.init_done)
  895. ql_dbg(ql_dbg_init, vha, 0x013a,
  896. "Waiting for init to complete...\n");
  897. do {
  898. rval = qlafx00_get_firmware_state(vha, state);
  899. if (rval == QLA_SUCCESS) {
  900. if (state[0] == FSTATE_FX00_INITIALIZED) {
  901. ql_dbg(ql_dbg_init, vha, 0x013b,
  902. "fw_state=%x\n", state[0]);
  903. rval = QLA_SUCCESS;
  904. break;
  905. }
  906. }
  907. rval = QLA_FUNCTION_FAILED;
  908. if (time_after_eq(jiffies, wtime))
  909. break;
  910. /* Delay for a while */
  911. msleep(500);
  912. ql_dbg(ql_dbg_init, vha, 0x013c,
  913. "fw_state=%x curr time=%lx.\n", state[0], jiffies);
  914. } while (1);
  915. if (rval)
  916. ql_dbg(ql_dbg_init, vha, 0x013d,
  917. "Firmware ready **** FAILED ****.\n");
  918. else
  919. ql_dbg(ql_dbg_init, vha, 0x013e,
  920. "Firmware ready **** SUCCESS ****.\n");
  921. return rval;
  922. }
  923. static int
  924. qlafx00_find_all_targets(scsi_qla_host_t *vha,
  925. struct list_head *new_fcports)
  926. {
  927. int rval;
  928. uint16_t tgt_id;
  929. fc_port_t *fcport, *new_fcport;
  930. int found;
  931. struct qla_hw_data *ha = vha->hw;
  932. rval = QLA_SUCCESS;
  933. if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
  934. return QLA_FUNCTION_FAILED;
  935. if ((atomic_read(&vha->loop_down_timer) ||
  936. STATE_TRANSITION(vha))) {
  937. atomic_set(&vha->loop_down_timer, 0);
  938. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  939. return QLA_FUNCTION_FAILED;
  940. }
  941. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
  942. "Listing Target bit map...\n");
  943. ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha, 0x2089,
  944. ha->gid_list, 32);
  945. /* Allocate temporary rmtport for any new rmtports discovered. */
  946. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  947. if (new_fcport == NULL)
  948. return QLA_MEMORY_ALLOC_FAILED;
  949. for_each_set_bit(tgt_id, (void *)ha->gid_list,
  950. QLAFX00_TGT_NODE_LIST_SIZE) {
  951. /* Send get target node info */
  952. new_fcport->tgt_id = tgt_id;
  953. rval = qlafx00_fx_disc(vha, new_fcport,
  954. FXDISC_GET_TGT_NODE_INFO);
  955. if (rval != QLA_SUCCESS) {
  956. ql_log(ql_log_warn, vha, 0x208a,
  957. "Target info scan failed -- assuming zero-entry "
  958. "result...\n");
  959. continue;
  960. }
  961. /* Locate matching device in database. */
  962. found = 0;
  963. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  964. if (memcmp(new_fcport->port_name,
  965. fcport->port_name, WWN_SIZE))
  966. continue;
  967. found++;
  968. /*
  969. * If tgt_id is same and state FCS_ONLINE, nothing
  970. * changed.
  971. */
  972. if (fcport->tgt_id == new_fcport->tgt_id &&
  973. atomic_read(&fcport->state) == FCS_ONLINE)
  974. break;
  975. /*
  976. * Tgt ID changed or device was marked to be updated.
  977. */
  978. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
  979. "TGT-ID Change(%s): Present tgt id: "
  980. "0x%x state: 0x%x "
  981. "wwnn = %llx wwpn = %llx.\n",
  982. __func__, fcport->tgt_id,
  983. atomic_read(&fcport->state),
  984. (unsigned long long)wwn_to_u64(fcport->node_name),
  985. (unsigned long long)wwn_to_u64(fcport->port_name));
  986. ql_log(ql_log_info, vha, 0x208c,
  987. "TGT-ID Announce(%s): Discovered tgt "
  988. "id 0x%x wwnn = %llx "
  989. "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
  990. (unsigned long long)
  991. wwn_to_u64(new_fcport->node_name),
  992. (unsigned long long)
  993. wwn_to_u64(new_fcport->port_name));
  994. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  995. fcport->old_tgt_id = fcport->tgt_id;
  996. fcport->tgt_id = new_fcport->tgt_id;
  997. ql_log(ql_log_info, vha, 0x208d,
  998. "TGT-ID: New fcport Added: %p\n", fcport);
  999. qla2x00_update_fcport(vha, fcport);
  1000. } else {
  1001. ql_log(ql_log_info, vha, 0x208e,
  1002. " Existing TGT-ID %x did not get "
  1003. " offline event from firmware.\n",
  1004. fcport->old_tgt_id);
  1005. qla2x00_mark_device_lost(vha, fcport, 0);
  1006. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1007. qla2x00_free_fcport(new_fcport);
  1008. return rval;
  1009. }
  1010. break;
  1011. }
  1012. if (found)
  1013. continue;
  1014. /* If device was not in our fcports list, then add it. */
  1015. list_add_tail(&new_fcport->list, new_fcports);
  1016. /* Allocate a new replacement fcport. */
  1017. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  1018. if (new_fcport == NULL)
  1019. return QLA_MEMORY_ALLOC_FAILED;
  1020. }
  1021. qla2x00_free_fcport(new_fcport);
  1022. return rval;
  1023. }
  1024. /*
  1025. * qlafx00_configure_all_targets
  1026. * Setup target devices with node ID's.
  1027. *
  1028. * Input:
  1029. * ha = adapter block pointer.
  1030. *
  1031. * Returns:
  1032. * 0 = success.
  1033. * BIT_0 = error
  1034. */
  1035. static int
  1036. qlafx00_configure_all_targets(scsi_qla_host_t *vha)
  1037. {
  1038. int rval;
  1039. fc_port_t *fcport, *rmptemp;
  1040. LIST_HEAD(new_fcports);
  1041. rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
  1042. FXDISC_GET_TGT_NODE_LIST);
  1043. if (rval != QLA_SUCCESS) {
  1044. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1045. return rval;
  1046. }
  1047. rval = qlafx00_find_all_targets(vha, &new_fcports);
  1048. if (rval != QLA_SUCCESS) {
  1049. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1050. return rval;
  1051. }
  1052. /*
  1053. * Delete all previous devices marked lost.
  1054. */
  1055. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1056. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1057. break;
  1058. if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
  1059. if (fcport->port_type != FCT_INITIATOR)
  1060. qla2x00_mark_device_lost(vha, fcport, 0);
  1061. }
  1062. }
  1063. /*
  1064. * Add the new devices to our devices list.
  1065. */
  1066. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1067. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1068. break;
  1069. qla2x00_update_fcport(vha, fcport);
  1070. list_move_tail(&fcport->list, &vha->vp_fcports);
  1071. ql_log(ql_log_info, vha, 0x208f,
  1072. "Attach new target id 0x%x wwnn = %llx "
  1073. "wwpn = %llx.\n",
  1074. fcport->tgt_id,
  1075. (unsigned long long)wwn_to_u64(fcport->node_name),
  1076. (unsigned long long)wwn_to_u64(fcport->port_name));
  1077. }
  1078. /* Free all new device structures not processed. */
  1079. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1080. list_del(&fcport->list);
  1081. qla2x00_free_fcport(fcport);
  1082. }
  1083. return rval;
  1084. }
  1085. /*
  1086. * qlafx00_configure_devices
  1087. * Updates Fibre Channel Device Database with what is actually on loop.
  1088. *
  1089. * Input:
  1090. * ha = adapter block pointer.
  1091. *
  1092. * Returns:
  1093. * 0 = success.
  1094. * 1 = error.
  1095. * 2 = database was full and device was not configured.
  1096. */
  1097. int
  1098. qlafx00_configure_devices(scsi_qla_host_t *vha)
  1099. {
  1100. int rval;
  1101. unsigned long flags;
  1102. rval = QLA_SUCCESS;
  1103. flags = vha->dpc_flags;
  1104. ql_dbg(ql_dbg_disc, vha, 0x2090,
  1105. "Configure devices -- dpc flags =0x%lx\n", flags);
  1106. rval = qlafx00_configure_all_targets(vha);
  1107. if (rval == QLA_SUCCESS) {
  1108. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  1109. rval = QLA_FUNCTION_FAILED;
  1110. } else {
  1111. atomic_set(&vha->loop_state, LOOP_READY);
  1112. ql_log(ql_log_info, vha, 0x2091,
  1113. "Device Ready\n");
  1114. }
  1115. }
  1116. if (rval) {
  1117. ql_dbg(ql_dbg_disc, vha, 0x2092,
  1118. "%s *** FAILED ***.\n", __func__);
  1119. } else {
  1120. ql_dbg(ql_dbg_disc, vha, 0x2093,
  1121. "%s: exiting normally.\n", __func__);
  1122. }
  1123. return rval;
  1124. }
  1125. static void
  1126. qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp)
  1127. {
  1128. struct qla_hw_data *ha = vha->hw;
  1129. fc_port_t *fcport;
  1130. vha->flags.online = 0;
  1131. ha->mr.fw_hbt_en = 0;
  1132. if (!critemp) {
  1133. ha->flags.chip_reset_done = 0;
  1134. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1135. vha->qla_stats.total_isp_aborts++;
  1136. ql_log(ql_log_info, vha, 0x013f,
  1137. "Performing ISP error recovery - ha = %p.\n", ha);
  1138. ha->isp_ops->reset_chip(vha);
  1139. }
  1140. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  1141. atomic_set(&vha->loop_state, LOOP_DOWN);
  1142. atomic_set(&vha->loop_down_timer,
  1143. QLAFX00_LOOP_DOWN_TIME);
  1144. } else {
  1145. if (!atomic_read(&vha->loop_down_timer))
  1146. atomic_set(&vha->loop_down_timer,
  1147. QLAFX00_LOOP_DOWN_TIME);
  1148. }
  1149. /* Clear all async request states across all VPs. */
  1150. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1151. fcport->flags = 0;
  1152. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1153. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  1154. }
  1155. if (!ha->flags.eeh_busy) {
  1156. if (critemp) {
  1157. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  1158. } else {
  1159. /* Requeue all commands in outstanding command list. */
  1160. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  1161. }
  1162. }
  1163. qla2x00_free_irqs(vha);
  1164. if (critemp)
  1165. set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags);
  1166. else
  1167. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1168. /* Clear the Interrupts */
  1169. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1170. ql_log(ql_log_info, vha, 0x0140,
  1171. "%s Done done - ha=%p.\n", __func__, ha);
  1172. }
  1173. /**
  1174. * qlafx00_init_response_q_entries() - Initializes response queue entries.
  1175. * @rsp: response queue
  1176. *
  1177. * Beginning of request ring has initialization control block already built
  1178. * by nvram config routine.
  1179. *
  1180. * Returns 0 on success.
  1181. */
  1182. void
  1183. qlafx00_init_response_q_entries(struct rsp_que *rsp)
  1184. {
  1185. uint16_t cnt;
  1186. response_t *pkt;
  1187. rsp->ring_ptr = rsp->ring;
  1188. rsp->ring_index = 0;
  1189. rsp->status_srb = NULL;
  1190. pkt = rsp->ring_ptr;
  1191. for (cnt = 0; cnt < rsp->length; cnt++) {
  1192. pkt->signature = RESPONSE_PROCESSED;
  1193. wrt_reg_dword((void __force __iomem *)&pkt->signature,
  1194. RESPONSE_PROCESSED);
  1195. pkt++;
  1196. }
  1197. }
  1198. int
  1199. qlafx00_rescan_isp(scsi_qla_host_t *vha)
  1200. {
  1201. uint32_t status = QLA_FUNCTION_FAILED;
  1202. struct qla_hw_data *ha = vha->hw;
  1203. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1204. uint32_t aenmbx7;
  1205. qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
  1206. aenmbx7 = rd_reg_dword(&reg->aenmailbox7);
  1207. ha->mbx_intr_code = MSW(aenmbx7);
  1208. ha->rqstq_intr_code = LSW(aenmbx7);
  1209. ha->req_que_off = rd_reg_dword(&reg->aenmailbox1);
  1210. ha->rsp_que_off = rd_reg_dword(&reg->aenmailbox3);
  1211. ha->req_que_len = rd_reg_dword(&reg->aenmailbox5);
  1212. ha->rsp_que_len = rd_reg_dword(&reg->aenmailbox6);
  1213. ql_dbg(ql_dbg_disc, vha, 0x2094,
  1214. "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
  1215. " Req que offset 0x%x Rsp que offset 0x%x\n",
  1216. ha->mbx_intr_code, ha->rqstq_intr_code,
  1217. ha->req_que_off, ha->rsp_que_len);
  1218. /* Clear the Interrupts */
  1219. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1220. status = qla2x00_init_rings(vha);
  1221. if (!status) {
  1222. vha->flags.online = 1;
  1223. /* if no cable then assume it's good */
  1224. if ((vha->device_flags & DFLG_NO_CABLE))
  1225. status = 0;
  1226. /* Register system information */
  1227. if (qlafx00_fx_disc(vha,
  1228. &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
  1229. ql_dbg(ql_dbg_disc, vha, 0x2095,
  1230. "failed to register host info\n");
  1231. }
  1232. scsi_unblock_requests(vha->host);
  1233. return status;
  1234. }
  1235. void
  1236. qlafx00_timer_routine(scsi_qla_host_t *vha)
  1237. {
  1238. struct qla_hw_data *ha = vha->hw;
  1239. uint32_t fw_heart_beat;
  1240. uint32_t aenmbx0;
  1241. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1242. uint32_t tempc;
  1243. /* Check firmware health */
  1244. if (ha->mr.fw_hbt_cnt)
  1245. ha->mr.fw_hbt_cnt--;
  1246. else {
  1247. if ((!ha->flags.mr_reset_hdlr_active) &&
  1248. (!test_bit(UNLOADING, &vha->dpc_flags)) &&
  1249. (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
  1250. (ha->mr.fw_hbt_en)) {
  1251. fw_heart_beat = rd_reg_dword(&reg->fwheartbeat);
  1252. if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
  1253. ha->mr.old_fw_hbt_cnt = fw_heart_beat;
  1254. ha->mr.fw_hbt_miss_cnt = 0;
  1255. } else {
  1256. ha->mr.fw_hbt_miss_cnt++;
  1257. if (ha->mr.fw_hbt_miss_cnt ==
  1258. QLAFX00_HEARTBEAT_MISS_CNT) {
  1259. set_bit(ISP_ABORT_NEEDED,
  1260. &vha->dpc_flags);
  1261. qla2xxx_wake_dpc(vha);
  1262. ha->mr.fw_hbt_miss_cnt = 0;
  1263. }
  1264. }
  1265. }
  1266. ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
  1267. }
  1268. if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
  1269. /* Reset recovery to be performed in timer routine */
  1270. aenmbx0 = rd_reg_dword(&reg->aenmailbox0);
  1271. if (ha->mr.fw_reset_timer_exp) {
  1272. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1273. qla2xxx_wake_dpc(vha);
  1274. ha->mr.fw_reset_timer_exp = 0;
  1275. } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
  1276. /* Wake up DPC to rescan the targets */
  1277. set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
  1278. clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1279. qla2xxx_wake_dpc(vha);
  1280. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1281. } else if ((aenmbx0 == MBA_FW_STARTING) &&
  1282. (!ha->mr.fw_hbt_en)) {
  1283. ha->mr.fw_hbt_en = 1;
  1284. } else if (!ha->mr.fw_reset_timer_tick) {
  1285. if (aenmbx0 == ha->mr.old_aenmbx0_state)
  1286. ha->mr.fw_reset_timer_exp = 1;
  1287. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1288. } else if (aenmbx0 == 0xFFFFFFFF) {
  1289. uint32_t data0, data1;
  1290. data0 = QLAFX00_RD_REG(ha,
  1291. QLAFX00_BAR1_BASE_ADDR_REG);
  1292. data1 = QLAFX00_RD_REG(ha,
  1293. QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
  1294. data0 &= 0xffff0000;
  1295. data1 &= 0x0000ffff;
  1296. QLAFX00_WR_REG(ha,
  1297. QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
  1298. (data0 | data1));
  1299. } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
  1300. ha->mr.fw_reset_timer_tick =
  1301. QLAFX00_MAX_RESET_INTERVAL;
  1302. } else if (aenmbx0 == MBA_FW_RESET_FCT) {
  1303. ha->mr.fw_reset_timer_tick =
  1304. QLAFX00_MAX_RESET_INTERVAL;
  1305. }
  1306. if (ha->mr.old_aenmbx0_state != aenmbx0) {
  1307. ha->mr.old_aenmbx0_state = aenmbx0;
  1308. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1309. }
  1310. ha->mr.fw_reset_timer_tick--;
  1311. }
  1312. if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) {
  1313. /*
  1314. * Critical temperature recovery to be
  1315. * performed in timer routine
  1316. */
  1317. if (ha->mr.fw_critemp_timer_tick == 0) {
  1318. tempc = QLAFX00_GET_TEMPERATURE(ha);
  1319. ql_dbg(ql_dbg_timer, vha, 0x6012,
  1320. "ISPFx00(%s): Critical temp timer, "
  1321. "current SOC temperature: %d\n",
  1322. __func__, tempc);
  1323. if (tempc < ha->mr.critical_temperature) {
  1324. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1325. clear_bit(FX00_CRITEMP_RECOVERY,
  1326. &vha->dpc_flags);
  1327. qla2xxx_wake_dpc(vha);
  1328. }
  1329. ha->mr.fw_critemp_timer_tick =
  1330. QLAFX00_CRITEMP_INTERVAL;
  1331. } else {
  1332. ha->mr.fw_critemp_timer_tick--;
  1333. }
  1334. }
  1335. if (ha->mr.host_info_resend) {
  1336. /*
  1337. * Incomplete host info might be sent to firmware
  1338. * durinng system boot - info should be resend
  1339. */
  1340. if (ha->mr.hinfo_resend_timer_tick == 0) {
  1341. ha->mr.host_info_resend = false;
  1342. set_bit(FX00_HOST_INFO_RESEND, &vha->dpc_flags);
  1343. ha->mr.hinfo_resend_timer_tick =
  1344. QLAFX00_HINFO_RESEND_INTERVAL;
  1345. qla2xxx_wake_dpc(vha);
  1346. } else {
  1347. ha->mr.hinfo_resend_timer_tick--;
  1348. }
  1349. }
  1350. }
  1351. /*
  1352. * qlfx00a_reset_initialize
  1353. * Re-initialize after a iSA device reset.
  1354. *
  1355. * Input:
  1356. * ha = adapter block pointer.
  1357. *
  1358. * Returns:
  1359. * 0 = success
  1360. */
  1361. int
  1362. qlafx00_reset_initialize(scsi_qla_host_t *vha)
  1363. {
  1364. struct qla_hw_data *ha = vha->hw;
  1365. if (vha->device_flags & DFLG_DEV_FAILED) {
  1366. ql_dbg(ql_dbg_init, vha, 0x0142,
  1367. "Device in failed state\n");
  1368. return QLA_SUCCESS;
  1369. }
  1370. ha->flags.mr_reset_hdlr_active = 1;
  1371. if (vha->flags.online) {
  1372. scsi_block_requests(vha->host);
  1373. qlafx00_abort_isp_cleanup(vha, false);
  1374. }
  1375. ql_log(ql_log_info, vha, 0x0143,
  1376. "(%s): succeeded.\n", __func__);
  1377. ha->flags.mr_reset_hdlr_active = 0;
  1378. return QLA_SUCCESS;
  1379. }
  1380. /*
  1381. * qlafx00_abort_isp
  1382. * Resets ISP and aborts all outstanding commands.
  1383. *
  1384. * Input:
  1385. * ha = adapter block pointer.
  1386. *
  1387. * Returns:
  1388. * 0 = success
  1389. */
  1390. int
  1391. qlafx00_abort_isp(scsi_qla_host_t *vha)
  1392. {
  1393. struct qla_hw_data *ha = vha->hw;
  1394. if (vha->flags.online) {
  1395. if (unlikely(pci_channel_offline(ha->pdev) &&
  1396. ha->flags.pci_channel_io_perm_failure)) {
  1397. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  1398. return QLA_SUCCESS;
  1399. }
  1400. scsi_block_requests(vha->host);
  1401. qlafx00_abort_isp_cleanup(vha, false);
  1402. } else {
  1403. scsi_block_requests(vha->host);
  1404. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1405. vha->qla_stats.total_isp_aborts++;
  1406. ha->isp_ops->reset_chip(vha);
  1407. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1408. /* Clear the Interrupts */
  1409. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1410. }
  1411. ql_log(ql_log_info, vha, 0x0145,
  1412. "(%s): succeeded.\n", __func__);
  1413. return QLA_SUCCESS;
  1414. }
  1415. static inline fc_port_t*
  1416. qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
  1417. {
  1418. fc_port_t *fcport;
  1419. /* Check for matching device in remote port list. */
  1420. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1421. if (fcport->tgt_id == tgt_id) {
  1422. ql_dbg(ql_dbg_async, vha, 0x5072,
  1423. "Matching fcport(%p) found with TGT-ID: 0x%x "
  1424. "and Remote TGT_ID: 0x%x\n",
  1425. fcport, fcport->tgt_id, tgt_id);
  1426. return fcport;
  1427. }
  1428. }
  1429. return NULL;
  1430. }
  1431. static void
  1432. qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
  1433. {
  1434. fc_port_t *fcport;
  1435. ql_log(ql_log_info, vha, 0x5073,
  1436. "Detach TGT-ID: 0x%x\n", tgt_id);
  1437. fcport = qlafx00_get_fcport(vha, tgt_id);
  1438. if (!fcport)
  1439. return;
  1440. qla2x00_mark_device_lost(vha, fcport, 0);
  1441. return;
  1442. }
  1443. void
  1444. qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
  1445. {
  1446. uint32_t aen_code, aen_data;
  1447. aen_code = FCH_EVT_VENDOR_UNIQUE;
  1448. aen_data = evt->u.aenfx.evtcode;
  1449. switch (evt->u.aenfx.evtcode) {
  1450. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  1451. if (evt->u.aenfx.mbx[1] == 0) {
  1452. if (evt->u.aenfx.mbx[2] == 1) {
  1453. if (!vha->flags.fw_tgt_reported)
  1454. vha->flags.fw_tgt_reported = 1;
  1455. atomic_set(&vha->loop_down_timer, 0);
  1456. atomic_set(&vha->loop_state, LOOP_UP);
  1457. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1458. qla2xxx_wake_dpc(vha);
  1459. } else if (evt->u.aenfx.mbx[2] == 2) {
  1460. qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
  1461. }
  1462. } else if (evt->u.aenfx.mbx[1] == 0xffff) {
  1463. if (evt->u.aenfx.mbx[2] == 1) {
  1464. if (!vha->flags.fw_tgt_reported)
  1465. vha->flags.fw_tgt_reported = 1;
  1466. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1467. } else if (evt->u.aenfx.mbx[2] == 2) {
  1468. vha->device_flags |= DFLG_NO_CABLE;
  1469. qla2x00_mark_all_devices_lost(vha);
  1470. }
  1471. }
  1472. break;
  1473. case QLAFX00_MBA_LINK_UP:
  1474. aen_code = FCH_EVT_LINKUP;
  1475. aen_data = 0;
  1476. break;
  1477. case QLAFX00_MBA_LINK_DOWN:
  1478. aen_code = FCH_EVT_LINKDOWN;
  1479. aen_data = 0;
  1480. break;
  1481. case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
  1482. ql_log(ql_log_info, vha, 0x5082,
  1483. "Process critical temperature event "
  1484. "aenmb[0]: %x\n",
  1485. evt->u.aenfx.evtcode);
  1486. scsi_block_requests(vha->host);
  1487. qlafx00_abort_isp_cleanup(vha, true);
  1488. scsi_unblock_requests(vha->host);
  1489. break;
  1490. }
  1491. fc_host_post_event(vha->host, fc_get_event_number(),
  1492. aen_code, aen_data);
  1493. }
  1494. static void
  1495. qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
  1496. {
  1497. u64 port_name = 0, node_name = 0;
  1498. port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
  1499. node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
  1500. fc_host_node_name(vha->host) = node_name;
  1501. fc_host_port_name(vha->host) = port_name;
  1502. if (!pinfo->port_type)
  1503. vha->hw->current_topology = ISP_CFG_F;
  1504. if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
  1505. atomic_set(&vha->loop_state, LOOP_READY);
  1506. else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
  1507. atomic_set(&vha->loop_state, LOOP_DOWN);
  1508. vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
  1509. }
  1510. static void
  1511. qla2x00_fxdisc_iocb_timeout(void *data)
  1512. {
  1513. srb_t *sp = data;
  1514. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1515. complete(&lio->u.fxiocb.fxiocb_comp);
  1516. }
  1517. static void qla2x00_fxdisc_sp_done(srb_t *sp, int res)
  1518. {
  1519. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1520. complete(&lio->u.fxiocb.fxiocb_comp);
  1521. }
  1522. int
  1523. qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
  1524. {
  1525. srb_t *sp;
  1526. struct srb_iocb *fdisc;
  1527. int rval = QLA_FUNCTION_FAILED;
  1528. struct qla_hw_data *ha = vha->hw;
  1529. struct host_system_info *phost_info;
  1530. struct register_host_info *preg_hsi;
  1531. struct new_utsname *p_sysid = NULL;
  1532. /* ref: INIT */
  1533. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1534. if (!sp)
  1535. goto done;
  1536. sp->type = SRB_FXIOCB_DCMD;
  1537. sp->name = "fxdisc";
  1538. qla2x00_init_async_sp(sp, FXDISC_TIMEOUT,
  1539. qla2x00_fxdisc_sp_done);
  1540. sp->u.iocb_cmd.timeout = qla2x00_fxdisc_iocb_timeout;
  1541. fdisc = &sp->u.iocb_cmd;
  1542. switch (fx_type) {
  1543. case FXDISC_GET_CONFIG_INFO:
  1544. fdisc->u.fxiocb.flags =
  1545. SRB_FXDISC_RESP_DMA_VALID;
  1546. fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
  1547. break;
  1548. case FXDISC_GET_PORT_INFO:
  1549. fdisc->u.fxiocb.flags =
  1550. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1551. fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
  1552. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
  1553. break;
  1554. case FXDISC_GET_TGT_NODE_INFO:
  1555. fdisc->u.fxiocb.flags =
  1556. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1557. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
  1558. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
  1559. break;
  1560. case FXDISC_GET_TGT_NODE_LIST:
  1561. fdisc->u.fxiocb.flags =
  1562. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1563. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
  1564. break;
  1565. case FXDISC_REG_HOST_INFO:
  1566. fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
  1567. fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
  1568. p_sysid = utsname();
  1569. if (!p_sysid) {
  1570. ql_log(ql_log_warn, vha, 0x303c,
  1571. "Not able to get the system information\n");
  1572. goto done_free_sp;
  1573. }
  1574. break;
  1575. case FXDISC_ABORT_IOCTL:
  1576. default:
  1577. break;
  1578. }
  1579. if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  1580. fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
  1581. fdisc->u.fxiocb.req_len,
  1582. &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
  1583. if (!fdisc->u.fxiocb.req_addr)
  1584. goto done_free_sp;
  1585. if (fx_type == FXDISC_REG_HOST_INFO) {
  1586. preg_hsi = (struct register_host_info *)
  1587. fdisc->u.fxiocb.req_addr;
  1588. phost_info = &preg_hsi->hsi;
  1589. memset(preg_hsi, 0, sizeof(struct register_host_info));
  1590. phost_info->os_type = OS_TYPE_LINUX;
  1591. strscpy(phost_info->sysname, p_sysid->sysname,
  1592. sizeof(phost_info->sysname));
  1593. strscpy(phost_info->nodename, p_sysid->nodename,
  1594. sizeof(phost_info->nodename));
  1595. if (!strcmp(phost_info->nodename, "(none)"))
  1596. ha->mr.host_info_resend = true;
  1597. strscpy(phost_info->release, p_sysid->release,
  1598. sizeof(phost_info->release));
  1599. strscpy(phost_info->version, p_sysid->version,
  1600. sizeof(phost_info->version));
  1601. strscpy(phost_info->machine, p_sysid->machine,
  1602. sizeof(phost_info->machine));
  1603. strscpy(phost_info->domainname, p_sysid->domainname,
  1604. sizeof(phost_info->domainname));
  1605. strscpy(phost_info->hostdriver, QLA2XXX_VERSION,
  1606. sizeof(phost_info->hostdriver));
  1607. preg_hsi->utc = (uint64_t)ktime_get_real_seconds();
  1608. ql_dbg(ql_dbg_init, vha, 0x0149,
  1609. "ISP%04X: Host registration with firmware\n",
  1610. ha->pdev->device);
  1611. ql_dbg(ql_dbg_init, vha, 0x014a,
  1612. "os_type = '%d', sysname = '%s', nodname = '%s'\n",
  1613. phost_info->os_type,
  1614. phost_info->sysname,
  1615. phost_info->nodename);
  1616. ql_dbg(ql_dbg_init, vha, 0x014b,
  1617. "release = '%s', version = '%s'\n",
  1618. phost_info->release,
  1619. phost_info->version);
  1620. ql_dbg(ql_dbg_init, vha, 0x014c,
  1621. "machine = '%s' "
  1622. "domainname = '%s', hostdriver = '%s'\n",
  1623. phost_info->machine,
  1624. phost_info->domainname,
  1625. phost_info->hostdriver);
  1626. ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
  1627. phost_info, sizeof(*phost_info));
  1628. }
  1629. }
  1630. if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  1631. fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
  1632. fdisc->u.fxiocb.rsp_len,
  1633. &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
  1634. if (!fdisc->u.fxiocb.rsp_addr)
  1635. goto done_unmap_req;
  1636. }
  1637. fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
  1638. rval = qla2x00_start_sp(sp);
  1639. if (rval != QLA_SUCCESS)
  1640. goto done_unmap_dma;
  1641. wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
  1642. if (fx_type == FXDISC_GET_CONFIG_INFO) {
  1643. struct config_info_data *pinfo =
  1644. (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
  1645. memtostr(vha->hw->model_number, pinfo->model_num);
  1646. memtostr(vha->hw->model_desc, pinfo->model_description);
  1647. memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
  1648. sizeof(vha->hw->mr.symbolic_name));
  1649. memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
  1650. sizeof(vha->hw->mr.serial_num));
  1651. memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
  1652. sizeof(vha->hw->mr.hw_version));
  1653. memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
  1654. sizeof(vha->hw->mr.fw_version));
  1655. strim(vha->hw->mr.fw_version);
  1656. memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
  1657. sizeof(vha->hw->mr.uboot_version));
  1658. memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
  1659. sizeof(vha->hw->mr.fru_serial_num));
  1660. vha->hw->mr.critical_temperature =
  1661. (pinfo->nominal_temp_value) ?
  1662. pinfo->nominal_temp_value : QLAFX00_CRITEMP_THRSHLD;
  1663. ha->mr.extended_io_enabled = (pinfo->enabled_capabilities &
  1664. QLAFX00_EXTENDED_IO_EN_MASK) != 0;
  1665. } else if (fx_type == FXDISC_GET_PORT_INFO) {
  1666. struct port_info_data *pinfo =
  1667. (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
  1668. memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
  1669. memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
  1670. vha->d_id.b.domain = pinfo->port_id[0];
  1671. vha->d_id.b.area = pinfo->port_id[1];
  1672. vha->d_id.b.al_pa = pinfo->port_id[2];
  1673. qlafx00_update_host_attr(vha, pinfo);
  1674. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
  1675. pinfo, 16);
  1676. } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
  1677. struct qlafx00_tgt_node_info *pinfo =
  1678. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1679. memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
  1680. memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
  1681. fcport->port_type = FCT_TARGET;
  1682. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
  1683. pinfo, 16);
  1684. } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
  1685. struct qlafx00_tgt_node_info *pinfo =
  1686. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1687. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
  1688. pinfo, 16);
  1689. memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
  1690. } else if (fx_type == FXDISC_ABORT_IOCTL)
  1691. fdisc->u.fxiocb.result =
  1692. (fdisc->u.fxiocb.result ==
  1693. cpu_to_le32(QLAFX00_IOCTL_ICOB_ABORT_SUCCESS)) ?
  1694. cpu_to_le32(QLA_SUCCESS) : cpu_to_le32(QLA_FUNCTION_FAILED);
  1695. rval = le32_to_cpu(fdisc->u.fxiocb.result);
  1696. done_unmap_dma:
  1697. if (fdisc->u.fxiocb.rsp_addr)
  1698. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
  1699. fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
  1700. done_unmap_req:
  1701. if (fdisc->u.fxiocb.req_addr)
  1702. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
  1703. fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
  1704. done_free_sp:
  1705. /* ref: INIT */
  1706. kref_put(&sp->cmd_kref, qla2x00_sp_release);
  1707. done:
  1708. return rval;
  1709. }
  1710. /*
  1711. * qlafx00_initialize_adapter
  1712. * Initialize board.
  1713. *
  1714. * Input:
  1715. * ha = adapter block pointer.
  1716. *
  1717. * Returns:
  1718. * 0 = success
  1719. */
  1720. int
  1721. qlafx00_initialize_adapter(scsi_qla_host_t *vha)
  1722. {
  1723. int rval;
  1724. struct qla_hw_data *ha = vha->hw;
  1725. uint32_t tempc;
  1726. /* Clear adapter flags. */
  1727. vha->flags.online = 0;
  1728. ha->flags.chip_reset_done = 0;
  1729. vha->flags.reset_active = 0;
  1730. ha->flags.pci_channel_io_perm_failure = 0;
  1731. ha->flags.eeh_busy = 0;
  1732. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1733. atomic_set(&vha->loop_state, LOOP_DOWN);
  1734. vha->device_flags = DFLG_NO_CABLE;
  1735. vha->dpc_flags = 0;
  1736. vha->flags.management_server_logged_in = 0;
  1737. ha->isp_abort_cnt = 0;
  1738. ha->beacon_blink_led = 0;
  1739. set_bit(0, ha->req_qid_map);
  1740. set_bit(0, ha->rsp_qid_map);
  1741. ql_dbg(ql_dbg_init, vha, 0x0147,
  1742. "Configuring PCI space...\n");
  1743. rval = ha->isp_ops->pci_config(vha);
  1744. if (rval) {
  1745. ql_log(ql_log_warn, vha, 0x0148,
  1746. "Unable to configure PCI space.\n");
  1747. return rval;
  1748. }
  1749. rval = qlafx00_init_fw_ready(vha);
  1750. if (rval != QLA_SUCCESS)
  1751. return rval;
  1752. qlafx00_save_queue_ptrs(vha);
  1753. rval = qlafx00_config_queues(vha);
  1754. if (rval != QLA_SUCCESS)
  1755. return rval;
  1756. /*
  1757. * Allocate the array of outstanding commands
  1758. * now that we know the firmware resources.
  1759. */
  1760. rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
  1761. if (rval != QLA_SUCCESS)
  1762. return rval;
  1763. rval = qla2x00_init_rings(vha);
  1764. ha->flags.chip_reset_done = 1;
  1765. tempc = QLAFX00_GET_TEMPERATURE(ha);
  1766. ql_dbg(ql_dbg_init, vha, 0x0152,
  1767. "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n",
  1768. __func__, tempc);
  1769. return rval;
  1770. }
  1771. uint32_t
  1772. qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
  1773. char *buf)
  1774. {
  1775. scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
  1776. int rval = QLA_FUNCTION_FAILED;
  1777. uint32_t state[1];
  1778. if (qla2x00_reset_active(vha))
  1779. ql_log(ql_log_warn, vha, 0x70ce,
  1780. "ISP reset active.\n");
  1781. else if (!vha->hw->flags.eeh_busy) {
  1782. rval = qlafx00_get_firmware_state(vha, state);
  1783. }
  1784. if (rval != QLA_SUCCESS)
  1785. memset(state, -1, sizeof(state));
  1786. return state[0];
  1787. }
  1788. void
  1789. qlafx00_get_host_speed(struct Scsi_Host *shost)
  1790. {
  1791. struct qla_hw_data *ha = ((struct scsi_qla_host *)
  1792. (shost_priv(shost)))->hw;
  1793. u32 speed = FC_PORTSPEED_UNKNOWN;
  1794. switch (ha->link_data_rate) {
  1795. case QLAFX00_PORT_SPEED_2G:
  1796. speed = FC_PORTSPEED_2GBIT;
  1797. break;
  1798. case QLAFX00_PORT_SPEED_4G:
  1799. speed = FC_PORTSPEED_4GBIT;
  1800. break;
  1801. case QLAFX00_PORT_SPEED_8G:
  1802. speed = FC_PORTSPEED_8GBIT;
  1803. break;
  1804. case QLAFX00_PORT_SPEED_10G:
  1805. speed = FC_PORTSPEED_10GBIT;
  1806. break;
  1807. }
  1808. fc_host_speed(shost) = speed;
  1809. }
  1810. /** QLAFX00 specific ISR implementation functions */
  1811. static inline void
  1812. qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1813. uint32_t sense_len, struct rsp_que *rsp, int res)
  1814. {
  1815. struct scsi_qla_host *vha = sp->vha;
  1816. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1817. uint32_t track_sense_len;
  1818. SET_FW_SENSE_LEN(sp, sense_len);
  1819. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1820. sense_len = SCSI_SENSE_BUFFERSIZE;
  1821. SET_CMD_SENSE_LEN(sp, sense_len);
  1822. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1823. track_sense_len = sense_len;
  1824. if (sense_len > par_sense_len)
  1825. sense_len = par_sense_len;
  1826. memcpy(cp->sense_buffer, sense_data, sense_len);
  1827. SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
  1828. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1829. track_sense_len -= sense_len;
  1830. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1831. ql_dbg(ql_dbg_io, vha, 0x304d,
  1832. "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
  1833. sense_len, par_sense_len, track_sense_len);
  1834. if (GET_FW_SENSE_LEN(sp) > 0) {
  1835. rsp->status_srb = sp;
  1836. cp->result = res;
  1837. }
  1838. if (sense_len) {
  1839. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
  1840. "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
  1841. sp->vha->host_no, cp->device->id, cp->device->lun,
  1842. cp);
  1843. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
  1844. cp->sense_buffer, sense_len);
  1845. }
  1846. }
  1847. static void
  1848. qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1849. struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
  1850. __le16 sstatus, __le16 cpstatus)
  1851. {
  1852. struct srb_iocb *tmf;
  1853. tmf = &sp->u.iocb_cmd;
  1854. if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
  1855. (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
  1856. cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
  1857. tmf->u.tmf.comp_status = cpstatus;
  1858. sp->done(sp, 0);
  1859. }
  1860. static void
  1861. qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1862. struct abort_iocb_entry_fx00 *pkt)
  1863. {
  1864. const char func[] = "ABT_IOCB";
  1865. srb_t *sp;
  1866. struct srb_iocb *abt;
  1867. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1868. if (!sp)
  1869. return;
  1870. abt = &sp->u.iocb_cmd;
  1871. abt->u.abt.comp_status = pkt->tgt_id_sts;
  1872. sp->done(sp, 0);
  1873. }
  1874. static void
  1875. qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1876. struct ioctl_iocb_entry_fx00 *pkt)
  1877. {
  1878. const char func[] = "IOSB_IOCB";
  1879. srb_t *sp;
  1880. struct bsg_job *bsg_job;
  1881. struct fc_bsg_reply *bsg_reply;
  1882. struct srb_iocb *iocb_job;
  1883. int res = 0;
  1884. struct qla_mt_iocb_rsp_fx00 fstatus;
  1885. uint8_t *fw_sts_ptr;
  1886. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1887. if (!sp)
  1888. return;
  1889. if (sp->type == SRB_FXIOCB_DCMD) {
  1890. iocb_job = &sp->u.iocb_cmd;
  1891. iocb_job->u.fxiocb.seq_number = pkt->seq_no;
  1892. iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
  1893. iocb_job->u.fxiocb.result = pkt->status;
  1894. if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
  1895. iocb_job->u.fxiocb.req_data =
  1896. pkt->dataword_r;
  1897. } else {
  1898. bsg_job = sp->u.bsg_job;
  1899. bsg_reply = bsg_job->reply;
  1900. memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
  1901. fstatus.reserved_1 = pkt->reserved_0;
  1902. fstatus.func_type = pkt->comp_func_num;
  1903. fstatus.ioctl_flags = pkt->fw_iotcl_flags;
  1904. fstatus.ioctl_data = pkt->dataword_r;
  1905. fstatus.adapid = pkt->adapid;
  1906. fstatus.reserved_2 = pkt->dataword_r_extra;
  1907. fstatus.res_count = pkt->residuallen;
  1908. fstatus.status = pkt->status;
  1909. fstatus.seq_number = pkt->seq_no;
  1910. memcpy(fstatus.reserved_3,
  1911. pkt->reserved_2, 20 * sizeof(uint8_t));
  1912. fw_sts_ptr = bsg_job->reply + sizeof(struct fc_bsg_reply);
  1913. memcpy(fw_sts_ptr, &fstatus, sizeof(fstatus));
  1914. bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
  1915. sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
  1916. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  1917. sp->vha, 0x5080, pkt, sizeof(*pkt));
  1918. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  1919. sp->vha, 0x5074,
  1920. fw_sts_ptr, sizeof(fstatus));
  1921. res = bsg_reply->result = DID_OK << 16;
  1922. bsg_reply->reply_payload_rcv_len =
  1923. bsg_job->reply_payload.payload_len;
  1924. }
  1925. sp->done(sp, res);
  1926. }
  1927. /**
  1928. * qlafx00_status_entry() - Process a Status IOCB entry.
  1929. * @vha: SCSI driver HA context
  1930. * @rsp: response queue
  1931. * @pkt: Entry pointer
  1932. */
  1933. static void
  1934. qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1935. {
  1936. srb_t *sp;
  1937. fc_port_t *fcport;
  1938. struct scsi_cmnd *cp;
  1939. struct sts_entry_fx00 *sts;
  1940. __le16 comp_status;
  1941. __le16 scsi_status;
  1942. __le16 lscsi_status;
  1943. int32_t resid;
  1944. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1945. fw_resid_len;
  1946. uint8_t *rsp_info = NULL, *sense_data = NULL;
  1947. struct qla_hw_data *ha = vha->hw;
  1948. uint32_t hindex, handle;
  1949. uint16_t que;
  1950. struct req_que *req;
  1951. int logit = 1;
  1952. int res = 0;
  1953. sts = (struct sts_entry_fx00 *) pkt;
  1954. comp_status = sts->comp_status;
  1955. scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
  1956. hindex = sts->handle;
  1957. handle = LSW(hindex);
  1958. que = MSW(hindex);
  1959. req = ha->req_q_map[que];
  1960. /* Validate handle. */
  1961. if (handle < req->num_outstanding_cmds)
  1962. sp = req->outstanding_cmds[handle];
  1963. else
  1964. sp = NULL;
  1965. if (sp == NULL) {
  1966. ql_dbg(ql_dbg_io, vha, 0x3034,
  1967. "Invalid status handle (0x%x).\n", handle);
  1968. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1969. qla2xxx_wake_dpc(vha);
  1970. return;
  1971. }
  1972. if (sp->type == SRB_TM_CMD) {
  1973. req->outstanding_cmds[handle] = NULL;
  1974. qlafx00_tm_iocb_entry(vha, req, pkt, sp,
  1975. scsi_status, comp_status);
  1976. return;
  1977. }
  1978. /* Fast path completion. */
  1979. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1980. qla2x00_process_completed_request(vha, req, handle);
  1981. return;
  1982. }
  1983. req->outstanding_cmds[handle] = NULL;
  1984. cp = GET_CMD_SP(sp);
  1985. if (cp == NULL) {
  1986. ql_dbg(ql_dbg_io, vha, 0x3048,
  1987. "Command already returned (0x%x/%p).\n",
  1988. handle, sp);
  1989. return;
  1990. }
  1991. lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
  1992. fcport = sp->fcport;
  1993. sense_len = par_sense_len = rsp_info_len = resid_len =
  1994. fw_resid_len = 0;
  1995. if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
  1996. sense_len = sts->sense_len;
  1997. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  1998. | (uint16_t)SS_RESIDUAL_OVER)))
  1999. resid_len = le32_to_cpu(sts->residual_len);
  2000. if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
  2001. fw_resid_len = le32_to_cpu(sts->residual_len);
  2002. rsp_info = sense_data = sts->data;
  2003. par_sense_len = sizeof(sts->data);
  2004. /* Check for overrun. */
  2005. if (comp_status == CS_COMPLETE &&
  2006. scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
  2007. comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
  2008. /*
  2009. * Based on Host and scsi status generate status code for Linux
  2010. */
  2011. switch (le16_to_cpu(comp_status)) {
  2012. case CS_COMPLETE:
  2013. case CS_QUEUE_FULL:
  2014. if (scsi_status == 0) {
  2015. res = DID_OK << 16;
  2016. break;
  2017. }
  2018. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2019. | (uint16_t)SS_RESIDUAL_OVER))) {
  2020. resid = resid_len;
  2021. scsi_set_resid(cp, resid);
  2022. if (!lscsi_status &&
  2023. ((unsigned)(scsi_bufflen(cp) - resid) <
  2024. cp->underflow)) {
  2025. ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
  2026. "Mid-layer underflow "
  2027. "detected (0x%x of 0x%x bytes).\n",
  2028. resid, scsi_bufflen(cp));
  2029. res = DID_ERROR << 16;
  2030. break;
  2031. }
  2032. }
  2033. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2034. if (lscsi_status ==
  2035. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2036. ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
  2037. "QUEUE FULL detected.\n");
  2038. break;
  2039. }
  2040. logit = 0;
  2041. if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2042. break;
  2043. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2044. if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2045. break;
  2046. qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  2047. rsp, res);
  2048. break;
  2049. case CS_DATA_UNDERRUN:
  2050. /* Use F/W calculated residual length. */
  2051. if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2052. resid = fw_resid_len;
  2053. else
  2054. resid = resid_len;
  2055. scsi_set_resid(cp, resid);
  2056. if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
  2057. if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2058. && fw_resid_len != resid_len) {
  2059. ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
  2060. "Dropped frame(s) detected "
  2061. "(0x%x of 0x%x bytes).\n",
  2062. resid, scsi_bufflen(cp));
  2063. res = DID_ERROR << 16 |
  2064. le16_to_cpu(lscsi_status);
  2065. goto check_scsi_status;
  2066. }
  2067. if (!lscsi_status &&
  2068. ((unsigned)(scsi_bufflen(cp) - resid) <
  2069. cp->underflow)) {
  2070. ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
  2071. "Mid-layer underflow "
  2072. "detected (0x%x of 0x%x bytes, "
  2073. "cp->underflow: 0x%x).\n",
  2074. resid, scsi_bufflen(cp), cp->underflow);
  2075. res = DID_ERROR << 16;
  2076. break;
  2077. }
  2078. } else if (lscsi_status !=
  2079. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
  2080. lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
  2081. /*
  2082. * scsi status of task set and busy are considered
  2083. * to be task not completed.
  2084. */
  2085. ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
  2086. "Dropped frame(s) detected (0x%x "
  2087. "of 0x%x bytes).\n", resid,
  2088. scsi_bufflen(cp));
  2089. res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
  2090. goto check_scsi_status;
  2091. } else {
  2092. ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
  2093. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  2094. scsi_status, lscsi_status);
  2095. }
  2096. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2097. logit = 0;
  2098. check_scsi_status:
  2099. /*
  2100. * Check to see if SCSI Status is non zero. If so report SCSI
  2101. * Status.
  2102. */
  2103. if (lscsi_status != 0) {
  2104. if (lscsi_status ==
  2105. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2106. ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
  2107. "QUEUE FULL detected.\n");
  2108. logit = 1;
  2109. break;
  2110. }
  2111. if (lscsi_status !=
  2112. cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2113. break;
  2114. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2115. if (!(scsi_status &
  2116. cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2117. break;
  2118. qlafx00_handle_sense(sp, sense_data, par_sense_len,
  2119. sense_len, rsp, res);
  2120. }
  2121. break;
  2122. case CS_PORT_LOGGED_OUT:
  2123. case CS_PORT_CONFIG_CHG:
  2124. case CS_PORT_BUSY:
  2125. case CS_INCOMPLETE:
  2126. case CS_PORT_UNAVAILABLE:
  2127. case CS_TIMEOUT:
  2128. case CS_RESET:
  2129. /*
  2130. * We are going to have the fc class block the rport
  2131. * while we try to recover so instruct the mid layer
  2132. * to requeue until the class decides how to handle this.
  2133. */
  2134. res = DID_TRANSPORT_DISRUPTED << 16;
  2135. ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
  2136. "Port down status: port-state=0x%x.\n",
  2137. atomic_read(&fcport->state));
  2138. if (atomic_read(&fcport->state) == FCS_ONLINE)
  2139. qla2x00_mark_device_lost(fcport->vha, fcport, 1);
  2140. break;
  2141. case CS_ABORTED:
  2142. res = DID_RESET << 16;
  2143. break;
  2144. default:
  2145. res = DID_ERROR << 16;
  2146. break;
  2147. }
  2148. if (logit)
  2149. ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
  2150. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
  2151. "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
  2152. "rsp_info=%p resid=0x%x fw_resid=0x%x sense_len=0x%x, "
  2153. "par_sense_len=0x%x, rsp_info_len=0x%x\n",
  2154. comp_status, scsi_status, res, vha->host_no,
  2155. cp->device->id, cp->device->lun, fcport->tgt_id,
  2156. lscsi_status, cp->cmnd, scsi_bufflen(cp),
  2157. rsp_info, resid_len, fw_resid_len, sense_len,
  2158. par_sense_len, rsp_info_len);
  2159. if (rsp->status_srb == NULL)
  2160. sp->done(sp, res);
  2161. else
  2162. WARN_ON_ONCE(true);
  2163. }
  2164. /**
  2165. * qlafx00_status_cont_entry() - Process a Status Continuations entry.
  2166. * @rsp: response queue
  2167. * @pkt: Entry pointer
  2168. *
  2169. * Extended sense data.
  2170. */
  2171. static void
  2172. qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  2173. {
  2174. uint8_t sense_sz = 0;
  2175. struct qla_hw_data *ha = rsp->hw;
  2176. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  2177. srb_t *sp = rsp->status_srb;
  2178. struct scsi_cmnd *cp;
  2179. uint32_t sense_len;
  2180. uint8_t *sense_ptr;
  2181. if (!sp) {
  2182. ql_dbg(ql_dbg_io, vha, 0x3037,
  2183. "no SP, sp = %p\n", sp);
  2184. return;
  2185. }
  2186. if (!GET_FW_SENSE_LEN(sp)) {
  2187. ql_dbg(ql_dbg_io, vha, 0x304b,
  2188. "no fw sense data, sp = %p\n", sp);
  2189. return;
  2190. }
  2191. cp = GET_CMD_SP(sp);
  2192. if (cp == NULL) {
  2193. ql_log(ql_log_warn, vha, 0x303b,
  2194. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  2195. rsp->status_srb = NULL;
  2196. return;
  2197. }
  2198. if (!GET_CMD_SENSE_LEN(sp)) {
  2199. ql_dbg(ql_dbg_io, vha, 0x304c,
  2200. "no sense data, sp = %p\n", sp);
  2201. } else {
  2202. sense_len = GET_CMD_SENSE_LEN(sp);
  2203. sense_ptr = GET_CMD_SENSE_PTR(sp);
  2204. ql_dbg(ql_dbg_io, vha, 0x304f,
  2205. "sp=%p sense_len=0x%x sense_ptr=%p.\n",
  2206. sp, sense_len, sense_ptr);
  2207. if (sense_len > sizeof(pkt->data))
  2208. sense_sz = sizeof(pkt->data);
  2209. else
  2210. sense_sz = sense_len;
  2211. /* Move sense data. */
  2212. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
  2213. pkt, sizeof(*pkt));
  2214. memcpy(sense_ptr, pkt->data, sense_sz);
  2215. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
  2216. sense_ptr, sense_sz);
  2217. sense_len -= sense_sz;
  2218. sense_ptr += sense_sz;
  2219. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2220. SET_CMD_SENSE_LEN(sp, sense_len);
  2221. }
  2222. sense_len = GET_FW_SENSE_LEN(sp);
  2223. sense_len = (sense_len > sizeof(pkt->data)) ?
  2224. (sense_len - sizeof(pkt->data)) : 0;
  2225. SET_FW_SENSE_LEN(sp, sense_len);
  2226. /* Place command on done queue. */
  2227. if (sense_len == 0) {
  2228. rsp->status_srb = NULL;
  2229. sp->done(sp, cp->result);
  2230. } else {
  2231. WARN_ON_ONCE(true);
  2232. }
  2233. }
  2234. /**
  2235. * qlafx00_multistatus_entry() - Process Multi response queue entries.
  2236. * @vha: SCSI driver HA context
  2237. * @rsp: response queue
  2238. * @pkt: received packet
  2239. */
  2240. static void
  2241. qlafx00_multistatus_entry(struct scsi_qla_host *vha,
  2242. struct rsp_que *rsp, void *pkt)
  2243. {
  2244. srb_t *sp;
  2245. struct multi_sts_entry_fx00 *stsmfx;
  2246. struct qla_hw_data *ha = vha->hw;
  2247. uint32_t handle, hindex, handle_count, i;
  2248. uint16_t que;
  2249. struct req_que *req;
  2250. __le32 *handle_ptr;
  2251. stsmfx = (struct multi_sts_entry_fx00 *) pkt;
  2252. handle_count = stsmfx->handle_count;
  2253. if (handle_count > MAX_HANDLE_COUNT) {
  2254. ql_dbg(ql_dbg_io, vha, 0x3035,
  2255. "Invalid handle count (0x%x).\n", handle_count);
  2256. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2257. qla2xxx_wake_dpc(vha);
  2258. return;
  2259. }
  2260. handle_ptr = &stsmfx->handles[0];
  2261. for (i = 0; i < handle_count; i++) {
  2262. hindex = le32_to_cpu(*handle_ptr);
  2263. handle = LSW(hindex);
  2264. que = MSW(hindex);
  2265. req = ha->req_q_map[que];
  2266. /* Validate handle. */
  2267. if (handle < req->num_outstanding_cmds)
  2268. sp = req->outstanding_cmds[handle];
  2269. else
  2270. sp = NULL;
  2271. if (sp == NULL) {
  2272. ql_dbg(ql_dbg_io, vha, 0x3044,
  2273. "Invalid status handle (0x%x).\n", handle);
  2274. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2275. qla2xxx_wake_dpc(vha);
  2276. return;
  2277. }
  2278. qla2x00_process_completed_request(vha, req, handle);
  2279. handle_ptr++;
  2280. }
  2281. }
  2282. /**
  2283. * qlafx00_error_entry() - Process an error entry.
  2284. * @vha: SCSI driver HA context
  2285. * @rsp: response queue
  2286. * @pkt: Entry pointer
  2287. */
  2288. static void
  2289. qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
  2290. struct sts_entry_fx00 *pkt)
  2291. {
  2292. srb_t *sp;
  2293. struct qla_hw_data *ha = vha->hw;
  2294. const char func[] = "ERROR-IOCB";
  2295. uint16_t que = 0;
  2296. struct req_que *req = NULL;
  2297. int res = DID_ERROR << 16;
  2298. req = ha->req_q_map[que];
  2299. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2300. if (sp) {
  2301. sp->done(sp, res);
  2302. return;
  2303. }
  2304. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2305. qla2xxx_wake_dpc(vha);
  2306. }
  2307. /**
  2308. * qlafx00_process_response_queue() - Process response queue entries.
  2309. * @vha: SCSI driver HA context
  2310. * @rsp: response queue
  2311. */
  2312. static void
  2313. qlafx00_process_response_queue(struct scsi_qla_host *vha,
  2314. struct rsp_que *rsp)
  2315. {
  2316. struct sts_entry_fx00 *pkt;
  2317. response_t *lptr;
  2318. uint16_t lreq_q_in = 0;
  2319. uint16_t lreq_q_out = 0;
  2320. lreq_q_in = rd_reg_dword(rsp->rsp_q_in);
  2321. lreq_q_out = rsp->ring_index;
  2322. while (lreq_q_in != lreq_q_out) {
  2323. lptr = rsp->ring_ptr;
  2324. memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
  2325. sizeof(rsp->rsp_pkt));
  2326. pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
  2327. rsp->ring_index++;
  2328. lreq_q_out++;
  2329. if (rsp->ring_index == rsp->length) {
  2330. lreq_q_out = 0;
  2331. rsp->ring_index = 0;
  2332. rsp->ring_ptr = rsp->ring;
  2333. } else {
  2334. rsp->ring_ptr++;
  2335. }
  2336. if (pkt->entry_status != 0 &&
  2337. pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
  2338. ql_dbg(ql_dbg_async, vha, 0x507f,
  2339. "type of error status in response: 0x%x\n",
  2340. pkt->entry_status);
  2341. qlafx00_error_entry(vha, rsp,
  2342. (struct sts_entry_fx00 *)pkt);
  2343. continue;
  2344. }
  2345. switch (pkt->entry_type) {
  2346. case STATUS_TYPE_FX00:
  2347. qlafx00_status_entry(vha, rsp, pkt);
  2348. break;
  2349. case STATUS_CONT_TYPE_FX00:
  2350. qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2351. break;
  2352. case MULTI_STATUS_TYPE_FX00:
  2353. qlafx00_multistatus_entry(vha, rsp, pkt);
  2354. break;
  2355. case ABORT_IOCB_TYPE_FX00:
  2356. qlafx00_abort_iocb_entry(vha, rsp->req,
  2357. (struct abort_iocb_entry_fx00 *)pkt);
  2358. break;
  2359. case IOCTL_IOSB_TYPE_FX00:
  2360. qlafx00_ioctl_iosb_entry(vha, rsp->req,
  2361. (struct ioctl_iocb_entry_fx00 *)pkt);
  2362. break;
  2363. default:
  2364. /* Type Not Supported. */
  2365. ql_dbg(ql_dbg_async, vha, 0x5081,
  2366. "Received unknown response pkt type %x "
  2367. "entry status=%x.\n",
  2368. pkt->entry_type, pkt->entry_status);
  2369. break;
  2370. }
  2371. }
  2372. /* Adjust ring index */
  2373. wrt_reg_dword(rsp->rsp_q_out, rsp->ring_index);
  2374. }
  2375. /**
  2376. * qlafx00_async_event() - Process aynchronous events.
  2377. * @vha: SCSI driver HA context
  2378. */
  2379. static void
  2380. qlafx00_async_event(scsi_qla_host_t *vha)
  2381. {
  2382. struct qla_hw_data *ha = vha->hw;
  2383. struct device_reg_fx00 __iomem *reg;
  2384. int data_size = 1;
  2385. reg = &ha->iobase->ispfx00;
  2386. /* Setup to process RIO completion. */
  2387. switch (ha->aenmb[0]) {
  2388. case QLAFX00_MBA_SYSTEM_ERR: /* System Error */
  2389. ql_log(ql_log_warn, vha, 0x5079,
  2390. "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
  2391. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2392. break;
  2393. case QLAFX00_MBA_SHUTDOWN_RQSTD: /* Shutdown requested */
  2394. ql_dbg(ql_dbg_async, vha, 0x5076,
  2395. "Asynchronous FW shutdown requested.\n");
  2396. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2397. qla2xxx_wake_dpc(vha);
  2398. break;
  2399. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  2400. ha->aenmb[1] = rd_reg_dword(&reg->aenmailbox1);
  2401. ha->aenmb[2] = rd_reg_dword(&reg->aenmailbox2);
  2402. ha->aenmb[3] = rd_reg_dword(&reg->aenmailbox3);
  2403. ql_dbg(ql_dbg_async, vha, 0x5077,
  2404. "Asynchronous port Update received "
  2405. "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
  2406. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
  2407. data_size = 4;
  2408. break;
  2409. case QLAFX00_MBA_TEMP_OVER: /* Over temperature event */
  2410. ql_log(ql_log_info, vha, 0x5085,
  2411. "Asynchronous over temperature event received "
  2412. "aenmb[0]: %x\n",
  2413. ha->aenmb[0]);
  2414. break;
  2415. case QLAFX00_MBA_TEMP_NORM: /* Normal temperature event */
  2416. ql_log(ql_log_info, vha, 0x5086,
  2417. "Asynchronous normal temperature event received "
  2418. "aenmb[0]: %x\n",
  2419. ha->aenmb[0]);
  2420. break;
  2421. case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
  2422. ql_log(ql_log_info, vha, 0x5083,
  2423. "Asynchronous critical temperature event received "
  2424. "aenmb[0]: %x\n",
  2425. ha->aenmb[0]);
  2426. break;
  2427. default:
  2428. ha->aenmb[1] = rd_reg_dword(&reg->aenmailbox1);
  2429. ha->aenmb[2] = rd_reg_dword(&reg->aenmailbox2);
  2430. ha->aenmb[3] = rd_reg_dword(&reg->aenmailbox3);
  2431. ha->aenmb[4] = rd_reg_dword(&reg->aenmailbox4);
  2432. ha->aenmb[5] = rd_reg_dword(&reg->aenmailbox5);
  2433. ha->aenmb[6] = rd_reg_dword(&reg->aenmailbox6);
  2434. ha->aenmb[7] = rd_reg_dword(&reg->aenmailbox7);
  2435. ql_dbg(ql_dbg_async, vha, 0x5078,
  2436. "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
  2437. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
  2438. ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
  2439. break;
  2440. }
  2441. qlafx00_post_aenfx_work(vha, ha->aenmb[0],
  2442. (uint32_t *)ha->aenmb, data_size);
  2443. }
  2444. /**
  2445. * qlafx00_mbx_completion() - Process mailbox command completions.
  2446. * @vha: SCSI driver HA context
  2447. * @mb0: value to be written into mailbox register 0
  2448. */
  2449. static void
  2450. qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
  2451. {
  2452. uint16_t cnt;
  2453. __le32 __iomem *wptr;
  2454. struct qla_hw_data *ha = vha->hw;
  2455. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  2456. if (!ha->mcp32)
  2457. ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
  2458. /* Load return mailbox registers. */
  2459. ha->flags.mbox_int = 1;
  2460. ha->mailbox_out32[0] = mb0;
  2461. wptr = &reg->mailbox17;
  2462. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2463. ha->mailbox_out32[cnt] = rd_reg_dword(wptr);
  2464. wptr++;
  2465. }
  2466. }
  2467. /**
  2468. * qlafx00_intr_handler() - Process interrupts for the ISPFX00.
  2469. * @irq: interrupt number
  2470. * @dev_id: SCSI driver HA context
  2471. *
  2472. * Called by system whenever the host adapter generates an interrupt.
  2473. *
  2474. * Returns handled flag.
  2475. */
  2476. irqreturn_t
  2477. qlafx00_intr_handler(int irq, void *dev_id)
  2478. {
  2479. scsi_qla_host_t *vha;
  2480. struct qla_hw_data *ha;
  2481. struct device_reg_fx00 __iomem *reg;
  2482. int status;
  2483. unsigned long iter;
  2484. uint32_t stat;
  2485. uint32_t mb[8];
  2486. struct rsp_que *rsp;
  2487. unsigned long flags;
  2488. uint32_t clr_intr = 0;
  2489. uint32_t intr_stat = 0;
  2490. rsp = (struct rsp_que *) dev_id;
  2491. if (!rsp) {
  2492. ql_log(ql_log_info, NULL, 0x507d,
  2493. "%s: NULL response queue pointer.\n", __func__);
  2494. return IRQ_NONE;
  2495. }
  2496. ha = rsp->hw;
  2497. reg = &ha->iobase->ispfx00;
  2498. status = 0;
  2499. if (unlikely(pci_channel_offline(ha->pdev)))
  2500. return IRQ_HANDLED;
  2501. spin_lock_irqsave(&ha->hardware_lock, flags);
  2502. vha = pci_get_drvdata(ha->pdev);
  2503. for (iter = 50; iter--; clr_intr = 0) {
  2504. stat = QLAFX00_RD_INTR_REG(ha);
  2505. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2506. break;
  2507. intr_stat = stat & QLAFX00_HST_INT_STS_BITS;
  2508. if (!intr_stat)
  2509. break;
  2510. if (stat & QLAFX00_INTR_MB_CMPLT) {
  2511. mb[0] = rd_reg_dword(&reg->mailbox16);
  2512. qlafx00_mbx_completion(vha, mb[0]);
  2513. status |= MBX_INTERRUPT;
  2514. clr_intr |= QLAFX00_INTR_MB_CMPLT;
  2515. }
  2516. if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) {
  2517. ha->aenmb[0] = rd_reg_dword(&reg->aenmailbox0);
  2518. qlafx00_async_event(vha);
  2519. clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
  2520. }
  2521. if (intr_stat & QLAFX00_INTR_RSP_CMPLT) {
  2522. qlafx00_process_response_queue(vha, rsp);
  2523. clr_intr |= QLAFX00_INTR_RSP_CMPLT;
  2524. }
  2525. QLAFX00_CLR_INTR_REG(ha, clr_intr);
  2526. QLAFX00_RD_INTR_REG(ha);
  2527. }
  2528. qla2x00_handle_mbx_completion(ha, status);
  2529. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2530. return IRQ_HANDLED;
  2531. }
  2532. /** QLAFX00 specific IOCB implementation functions */
  2533. static inline cont_a64_entry_t *
  2534. qlafx00_prep_cont_type1_iocb(struct req_que *req,
  2535. cont_a64_entry_t *lcont_pkt)
  2536. {
  2537. cont_a64_entry_t *cont_pkt;
  2538. /* Adjust ring index. */
  2539. req->ring_index++;
  2540. if (req->ring_index == req->length) {
  2541. req->ring_index = 0;
  2542. req->ring_ptr = req->ring;
  2543. } else {
  2544. req->ring_ptr++;
  2545. }
  2546. cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
  2547. /* Load packet defaults. */
  2548. lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
  2549. return cont_pkt;
  2550. }
  2551. static inline void
  2552. qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
  2553. uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
  2554. {
  2555. uint16_t avail_dsds;
  2556. struct dsd64 *cur_dsd;
  2557. scsi_qla_host_t *vha;
  2558. struct scsi_cmnd *cmd;
  2559. struct scatterlist *sg;
  2560. int i, cont;
  2561. struct req_que *req;
  2562. cont_a64_entry_t lcont_pkt;
  2563. cont_a64_entry_t *cont_pkt;
  2564. vha = sp->vha;
  2565. req = vha->req;
  2566. cmd = GET_CMD_SP(sp);
  2567. cont = 0;
  2568. cont_pkt = NULL;
  2569. /* Update entry type to indicate Command Type 3 IOCB */
  2570. lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
  2571. /* No data transfer */
  2572. if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
  2573. lcmd_pkt->byte_count = cpu_to_le32(0);
  2574. return;
  2575. }
  2576. /* Set transfer direction */
  2577. if (cmd->sc_data_direction == DMA_TO_DEVICE) {
  2578. lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
  2579. vha->qla_stats.output_bytes += scsi_bufflen(cmd);
  2580. } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
  2581. lcmd_pkt->cntrl_flags = TMF_READ_DATA;
  2582. vha->qla_stats.input_bytes += scsi_bufflen(cmd);
  2583. }
  2584. /* One DSD is available in the Command Type 3 IOCB */
  2585. avail_dsds = 1;
  2586. cur_dsd = &lcmd_pkt->dsd;
  2587. /* Load data segments */
  2588. scsi_for_each_sg(cmd, sg, tot_dsds, i) {
  2589. /* Allocate additional continuation packets? */
  2590. if (avail_dsds == 0) {
  2591. /*
  2592. * Five DSDs are available in the Continuation
  2593. * Type 1 IOCB.
  2594. */
  2595. memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
  2596. cont_pkt =
  2597. qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
  2598. cur_dsd = lcont_pkt.dsd;
  2599. avail_dsds = 5;
  2600. cont = 1;
  2601. }
  2602. append_dsd64(&cur_dsd, sg);
  2603. avail_dsds--;
  2604. if (avail_dsds == 0 && cont == 1) {
  2605. cont = 0;
  2606. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2607. sizeof(lcont_pkt));
  2608. }
  2609. }
  2610. if (avail_dsds != 0 && cont == 1) {
  2611. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2612. sizeof(lcont_pkt));
  2613. }
  2614. }
  2615. /**
  2616. * qlafx00_start_scsi() - Send a SCSI command to the ISP
  2617. * @sp: command to send to the ISP
  2618. *
  2619. * Returns non-zero if a failure occurred, else zero.
  2620. */
  2621. int
  2622. qlafx00_start_scsi(srb_t *sp)
  2623. {
  2624. int nseg;
  2625. unsigned long flags;
  2626. uint32_t handle;
  2627. uint16_t cnt;
  2628. uint16_t req_cnt;
  2629. uint16_t tot_dsds;
  2630. struct req_que *req = NULL;
  2631. struct rsp_que *rsp = NULL;
  2632. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  2633. struct scsi_qla_host *vha = sp->vha;
  2634. struct qla_hw_data *ha = vha->hw;
  2635. struct cmd_type_7_fx00 *cmd_pkt;
  2636. struct cmd_type_7_fx00 lcmd_pkt;
  2637. struct scsi_lun llun;
  2638. /* Setup device pointers. */
  2639. rsp = ha->rsp_q_map[0];
  2640. req = vha->req;
  2641. /* So we know we haven't pci_map'ed anything yet */
  2642. tot_dsds = 0;
  2643. /* Acquire ring specific lock */
  2644. spin_lock_irqsave(&ha->hardware_lock, flags);
  2645. handle = qla2xxx_get_next_handle(req);
  2646. if (handle == 0)
  2647. goto queuing_error;
  2648. /* Map the sg table so we have an accurate count of sg entries needed */
  2649. if (scsi_sg_count(cmd)) {
  2650. nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
  2651. scsi_sg_count(cmd), cmd->sc_data_direction);
  2652. if (unlikely(!nseg))
  2653. goto queuing_error;
  2654. } else
  2655. nseg = 0;
  2656. tot_dsds = nseg;
  2657. req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
  2658. if (req->cnt < (req_cnt + 2)) {
  2659. cnt = rd_reg_dword_relaxed(req->req_q_out);
  2660. if (req->ring_index < cnt)
  2661. req->cnt = cnt - req->ring_index;
  2662. else
  2663. req->cnt = req->length -
  2664. (req->ring_index - cnt);
  2665. if (req->cnt < (req_cnt + 2))
  2666. goto queuing_error;
  2667. }
  2668. /* Build command packet. */
  2669. req->current_outstanding_cmd = handle;
  2670. req->outstanding_cmds[handle] = sp;
  2671. sp->handle = handle;
  2672. cmd->host_scribble = (unsigned char *)(unsigned long)handle;
  2673. req->cnt -= req_cnt;
  2674. cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
  2675. memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
  2676. lcmd_pkt.handle = make_handle(req->id, sp->handle);
  2677. lcmd_pkt.reserved_0 = 0;
  2678. lcmd_pkt.port_path_ctrl = 0;
  2679. lcmd_pkt.reserved_1 = 0;
  2680. lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
  2681. lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
  2682. int_to_scsilun(cmd->device->lun, &llun);
  2683. host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
  2684. sizeof(lcmd_pkt.lun));
  2685. /* Load SCSI command packet. */
  2686. host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
  2687. lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
  2688. /* Build IOCB segments */
  2689. qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
  2690. /* Set total data segment count. */
  2691. lcmd_pkt.entry_count = (uint8_t)req_cnt;
  2692. /* Specify response queue number where completion should happen */
  2693. lcmd_pkt.entry_status = (uint8_t) rsp->id;
  2694. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
  2695. cmd->cmnd, cmd->cmd_len);
  2696. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
  2697. &lcmd_pkt, sizeof(lcmd_pkt));
  2698. memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
  2699. wmb();
  2700. /* Adjust ring index. */
  2701. req->ring_index++;
  2702. if (req->ring_index == req->length) {
  2703. req->ring_index = 0;
  2704. req->ring_ptr = req->ring;
  2705. } else
  2706. req->ring_ptr++;
  2707. sp->flags |= SRB_DMA_VALID;
  2708. /* Set chip new ring index. */
  2709. wrt_reg_dword(req->req_q_in, req->ring_index);
  2710. QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
  2711. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2712. return QLA_SUCCESS;
  2713. queuing_error:
  2714. if (tot_dsds)
  2715. scsi_dma_unmap(cmd);
  2716. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2717. return QLA_FUNCTION_FAILED;
  2718. }
  2719. void
  2720. qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
  2721. {
  2722. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2723. scsi_qla_host_t *vha = sp->vha;
  2724. struct req_que *req = vha->req;
  2725. struct tsk_mgmt_entry_fx00 tm_iocb;
  2726. struct scsi_lun llun;
  2727. memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
  2728. tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
  2729. tm_iocb.entry_count = 1;
  2730. tm_iocb.handle = make_handle(req->id, sp->handle);
  2731. tm_iocb.reserved_0 = 0;
  2732. tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
  2733. tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
  2734. if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
  2735. int_to_scsilun(fxio->u.tmf.lun, &llun);
  2736. host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
  2737. sizeof(struct scsi_lun));
  2738. }
  2739. memcpy(ptm_iocb, &tm_iocb,
  2740. sizeof(struct tsk_mgmt_entry_fx00));
  2741. wmb();
  2742. }
  2743. void
  2744. qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
  2745. {
  2746. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2747. scsi_qla_host_t *vha = sp->vha;
  2748. struct req_que *req = vha->req;
  2749. struct abort_iocb_entry_fx00 abt_iocb;
  2750. memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
  2751. abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
  2752. abt_iocb.entry_count = 1;
  2753. abt_iocb.handle = make_handle(req->id, sp->handle);
  2754. abt_iocb.abort_handle = make_handle(req->id, fxio->u.abt.cmd_hndl);
  2755. abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
  2756. abt_iocb.req_que_no = cpu_to_le16(req->id);
  2757. memcpy(pabt_iocb, &abt_iocb,
  2758. sizeof(struct abort_iocb_entry_fx00));
  2759. wmb();
  2760. }
  2761. void
  2762. qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
  2763. {
  2764. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2765. struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
  2766. struct bsg_job *bsg_job;
  2767. struct fc_bsg_request *bsg_request;
  2768. struct fxdisc_entry_fx00 fx_iocb;
  2769. uint8_t entry_cnt = 1;
  2770. memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
  2771. fx_iocb.entry_type = FX00_IOCB_TYPE;
  2772. fx_iocb.handle = sp->handle;
  2773. fx_iocb.entry_count = entry_cnt;
  2774. if (sp->type == SRB_FXIOCB_DCMD) {
  2775. fx_iocb.func_num =
  2776. sp->u.iocb_cmd.u.fxiocb.req_func_type;
  2777. fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
  2778. fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
  2779. fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
  2780. fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
  2781. fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
  2782. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  2783. fx_iocb.req_dsdcnt = cpu_to_le16(1);
  2784. fx_iocb.req_xfrcnt =
  2785. cpu_to_le16(fxio->u.fxiocb.req_len);
  2786. put_unaligned_le64(fxio->u.fxiocb.req_dma_handle,
  2787. &fx_iocb.dseg_rq[0].address);
  2788. fx_iocb.dseg_rq[0].length =
  2789. cpu_to_le32(fxio->u.fxiocb.req_len);
  2790. }
  2791. if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  2792. fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
  2793. fx_iocb.rsp_xfrcnt =
  2794. cpu_to_le16(fxio->u.fxiocb.rsp_len);
  2795. put_unaligned_le64(fxio->u.fxiocb.rsp_dma_handle,
  2796. &fx_iocb.dseg_rsp[0].address);
  2797. fx_iocb.dseg_rsp[0].length =
  2798. cpu_to_le32(fxio->u.fxiocb.rsp_len);
  2799. }
  2800. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
  2801. fx_iocb.dataword = fxio->u.fxiocb.req_data;
  2802. }
  2803. fx_iocb.flags = fxio->u.fxiocb.flags;
  2804. } else {
  2805. struct scatterlist *sg;
  2806. bsg_job = sp->u.bsg_job;
  2807. bsg_request = bsg_job->request;
  2808. piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
  2809. &bsg_request->rqst_data.h_vendor.vendor_cmd[1];
  2810. fx_iocb.func_num = piocb_rqst->func_type;
  2811. fx_iocb.adapid = piocb_rqst->adapid;
  2812. fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
  2813. fx_iocb.reserved_0 = piocb_rqst->reserved_0;
  2814. fx_iocb.reserved_1 = piocb_rqst->reserved_1;
  2815. fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
  2816. fx_iocb.dataword = piocb_rqst->dataword;
  2817. fx_iocb.req_xfrcnt = piocb_rqst->req_len;
  2818. fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
  2819. if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
  2820. int avail_dsds, tot_dsds;
  2821. cont_a64_entry_t lcont_pkt;
  2822. cont_a64_entry_t *cont_pkt = NULL;
  2823. struct dsd64 *cur_dsd;
  2824. int index = 0, cont = 0;
  2825. fx_iocb.req_dsdcnt =
  2826. cpu_to_le16(bsg_job->request_payload.sg_cnt);
  2827. tot_dsds =
  2828. bsg_job->request_payload.sg_cnt;
  2829. cur_dsd = &fx_iocb.dseg_rq[0];
  2830. avail_dsds = 1;
  2831. for_each_sg(bsg_job->request_payload.sg_list, sg,
  2832. tot_dsds, index) {
  2833. /* Allocate additional continuation packets? */
  2834. if (avail_dsds == 0) {
  2835. /*
  2836. * Five DSDs are available in the Cont.
  2837. * Type 1 IOCB.
  2838. */
  2839. memset(&lcont_pkt, 0,
  2840. REQUEST_ENTRY_SIZE);
  2841. cont_pkt =
  2842. qlafx00_prep_cont_type1_iocb(
  2843. sp->vha->req, &lcont_pkt);
  2844. cur_dsd = lcont_pkt.dsd;
  2845. avail_dsds = 5;
  2846. cont = 1;
  2847. entry_cnt++;
  2848. }
  2849. append_dsd64(&cur_dsd, sg);
  2850. avail_dsds--;
  2851. if (avail_dsds == 0 && cont == 1) {
  2852. cont = 0;
  2853. memcpy_toio(
  2854. (void __iomem *)cont_pkt,
  2855. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2856. ql_dump_buffer(
  2857. ql_dbg_user + ql_dbg_verbose,
  2858. sp->vha, 0x3042,
  2859. (uint8_t *)&lcont_pkt,
  2860. REQUEST_ENTRY_SIZE);
  2861. }
  2862. }
  2863. if (avail_dsds != 0 && cont == 1) {
  2864. memcpy_toio((void __iomem *)cont_pkt,
  2865. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2866. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2867. sp->vha, 0x3043,
  2868. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  2869. }
  2870. }
  2871. if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
  2872. int avail_dsds, tot_dsds;
  2873. cont_a64_entry_t lcont_pkt;
  2874. cont_a64_entry_t *cont_pkt = NULL;
  2875. struct dsd64 *cur_dsd;
  2876. int index = 0, cont = 0;
  2877. fx_iocb.rsp_dsdcnt =
  2878. cpu_to_le16(bsg_job->reply_payload.sg_cnt);
  2879. tot_dsds = bsg_job->reply_payload.sg_cnt;
  2880. cur_dsd = &fx_iocb.dseg_rsp[0];
  2881. avail_dsds = 1;
  2882. for_each_sg(bsg_job->reply_payload.sg_list, sg,
  2883. tot_dsds, index) {
  2884. /* Allocate additional continuation packets? */
  2885. if (avail_dsds == 0) {
  2886. /*
  2887. * Five DSDs are available in the Cont.
  2888. * Type 1 IOCB.
  2889. */
  2890. memset(&lcont_pkt, 0,
  2891. REQUEST_ENTRY_SIZE);
  2892. cont_pkt =
  2893. qlafx00_prep_cont_type1_iocb(
  2894. sp->vha->req, &lcont_pkt);
  2895. cur_dsd = lcont_pkt.dsd;
  2896. avail_dsds = 5;
  2897. cont = 1;
  2898. entry_cnt++;
  2899. }
  2900. append_dsd64(&cur_dsd, sg);
  2901. avail_dsds--;
  2902. if (avail_dsds == 0 && cont == 1) {
  2903. cont = 0;
  2904. memcpy_toio((void __iomem *)cont_pkt,
  2905. &lcont_pkt,
  2906. REQUEST_ENTRY_SIZE);
  2907. ql_dump_buffer(
  2908. ql_dbg_user + ql_dbg_verbose,
  2909. sp->vha, 0x3045,
  2910. (uint8_t *)&lcont_pkt,
  2911. REQUEST_ENTRY_SIZE);
  2912. }
  2913. }
  2914. if (avail_dsds != 0 && cont == 1) {
  2915. memcpy_toio((void __iomem *)cont_pkt,
  2916. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2917. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2918. sp->vha, 0x3046,
  2919. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  2920. }
  2921. }
  2922. if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
  2923. fx_iocb.dataword = piocb_rqst->dataword;
  2924. fx_iocb.flags = piocb_rqst->flags;
  2925. fx_iocb.entry_count = entry_cnt;
  2926. }
  2927. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2928. sp->vha, 0x3047, &fx_iocb, sizeof(fx_iocb));
  2929. memcpy_toio((void __iomem *)pfxiocb, &fx_iocb, sizeof(fx_iocb));
  2930. wmb();
  2931. }