smartpqi_init.c 304 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * driver for Microchip PQI-based storage controllers
  4. * Copyright (c) 2019-2023 Microchip Technology Inc. and its subsidiaries
  5. * Copyright (c) 2016-2018 Microsemi Corporation
  6. * Copyright (c) 2016 PMC-Sierra, Inc.
  7. *
  8. * Questions/Comments/Bugfixes to storagedev@microchip.com
  9. *
  10. */
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/pci.h>
  14. #include <linux/delay.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/sched.h>
  17. #include <linux/rtc.h>
  18. #include <linux/bcd.h>
  19. #include <linux/reboot.h>
  20. #include <linux/cciss_ioctl.h>
  21. #include <linux/blk-mq-pci.h>
  22. #include <scsi/scsi_host.h>
  23. #include <scsi/scsi_cmnd.h>
  24. #include <scsi/scsi_device.h>
  25. #include <scsi/scsi_eh.h>
  26. #include <scsi/scsi_transport_sas.h>
  27. #include <linux/unaligned.h>
  28. #include "smartpqi.h"
  29. #include "smartpqi_sis.h"
  30. #if !defined(BUILD_TIMESTAMP)
  31. #define BUILD_TIMESTAMP
  32. #endif
  33. #define DRIVER_VERSION "2.1.30-031"
  34. #define DRIVER_MAJOR 2
  35. #define DRIVER_MINOR 1
  36. #define DRIVER_RELEASE 30
  37. #define DRIVER_REVISION 31
  38. #define DRIVER_NAME "Microchip SmartPQI Driver (v" \
  39. DRIVER_VERSION BUILD_TIMESTAMP ")"
  40. #define DRIVER_NAME_SHORT "smartpqi"
  41. #define PQI_EXTRA_SGL_MEMORY (12 * sizeof(struct pqi_sg_descriptor))
  42. #define PQI_POST_RESET_DELAY_SECS 5
  43. #define PQI_POST_OFA_RESET_DELAY_UPON_TIMEOUT_SECS 10
  44. #define PQI_NO_COMPLETION ((void *)-1)
  45. MODULE_AUTHOR("Microchip");
  46. MODULE_DESCRIPTION("Driver for Microchip Smart Family Controller version "
  47. DRIVER_VERSION);
  48. MODULE_VERSION(DRIVER_VERSION);
  49. MODULE_LICENSE("GPL");
  50. struct pqi_cmd_priv {
  51. int this_residual;
  52. };
  53. static struct pqi_cmd_priv *pqi_cmd_priv(struct scsi_cmnd *cmd)
  54. {
  55. return scsi_cmd_priv(cmd);
  56. }
  57. static void pqi_verify_structures(void);
  58. static void pqi_take_ctrl_offline(struct pqi_ctrl_info *ctrl_info,
  59. enum pqi_ctrl_shutdown_reason ctrl_shutdown_reason);
  60. static void pqi_ctrl_offline_worker(struct work_struct *work);
  61. static int pqi_scan_scsi_devices(struct pqi_ctrl_info *ctrl_info);
  62. static void pqi_scan_start(struct Scsi_Host *shost);
  63. static void pqi_start_io(struct pqi_ctrl_info *ctrl_info,
  64. struct pqi_queue_group *queue_group, enum pqi_io_path path,
  65. struct pqi_io_request *io_request);
  66. static int pqi_submit_raid_request_synchronous(struct pqi_ctrl_info *ctrl_info,
  67. struct pqi_iu_header *request, unsigned int flags,
  68. struct pqi_raid_error_info *error_info);
  69. static int pqi_aio_submit_io(struct pqi_ctrl_info *ctrl_info,
  70. struct scsi_cmnd *scmd, u32 aio_handle, u8 *cdb,
  71. unsigned int cdb_length, struct pqi_queue_group *queue_group,
  72. struct pqi_encryption_info *encryption_info, bool raid_bypass, bool io_high_prio);
  73. static int pqi_aio_submit_r1_write_io(struct pqi_ctrl_info *ctrl_info,
  74. struct scsi_cmnd *scmd, struct pqi_queue_group *queue_group,
  75. struct pqi_encryption_info *encryption_info, struct pqi_scsi_dev *device,
  76. struct pqi_scsi_dev_raid_map_data *rmd);
  77. static int pqi_aio_submit_r56_write_io(struct pqi_ctrl_info *ctrl_info,
  78. struct scsi_cmnd *scmd, struct pqi_queue_group *queue_group,
  79. struct pqi_encryption_info *encryption_info, struct pqi_scsi_dev *device,
  80. struct pqi_scsi_dev_raid_map_data *rmd);
  81. static void pqi_ofa_ctrl_quiesce(struct pqi_ctrl_info *ctrl_info);
  82. static void pqi_ofa_ctrl_unquiesce(struct pqi_ctrl_info *ctrl_info);
  83. static int pqi_ofa_ctrl_restart(struct pqi_ctrl_info *ctrl_info, unsigned int delay_secs);
  84. static void pqi_host_setup_buffer(struct pqi_ctrl_info *ctrl_info, struct pqi_host_memory_descriptor *host_memory_descriptor, u32 total_size, u32 min_size);
  85. static void pqi_host_free_buffer(struct pqi_ctrl_info *ctrl_info, struct pqi_host_memory_descriptor *host_memory_descriptor);
  86. static int pqi_host_memory_update(struct pqi_ctrl_info *ctrl_info, struct pqi_host_memory_descriptor *host_memory_descriptor, u16 function_code);
  87. static int pqi_device_wait_for_pending_io(struct pqi_ctrl_info *ctrl_info,
  88. struct pqi_scsi_dev *device, u8 lun, unsigned long timeout_msecs);
  89. static void pqi_fail_all_outstanding_requests(struct pqi_ctrl_info *ctrl_info);
  90. static void pqi_tmf_worker(struct work_struct *work);
  91. /* for flags argument to pqi_submit_raid_request_synchronous() */
  92. #define PQI_SYNC_FLAGS_INTERRUPTABLE 0x1
  93. static struct scsi_transport_template *pqi_sas_transport_template;
  94. static atomic_t pqi_controller_count = ATOMIC_INIT(0);
  95. enum pqi_lockup_action {
  96. NONE,
  97. REBOOT,
  98. PANIC
  99. };
  100. static enum pqi_lockup_action pqi_lockup_action = NONE;
  101. static struct {
  102. enum pqi_lockup_action action;
  103. char *name;
  104. } pqi_lockup_actions[] = {
  105. {
  106. .action = NONE,
  107. .name = "none",
  108. },
  109. {
  110. .action = REBOOT,
  111. .name = "reboot",
  112. },
  113. {
  114. .action = PANIC,
  115. .name = "panic",
  116. },
  117. };
  118. static unsigned int pqi_supported_event_types[] = {
  119. PQI_EVENT_TYPE_HOTPLUG,
  120. PQI_EVENT_TYPE_HARDWARE,
  121. PQI_EVENT_TYPE_PHYSICAL_DEVICE,
  122. PQI_EVENT_TYPE_LOGICAL_DEVICE,
  123. PQI_EVENT_TYPE_OFA,
  124. PQI_EVENT_TYPE_AIO_STATE_CHANGE,
  125. PQI_EVENT_TYPE_AIO_CONFIG_CHANGE,
  126. };
  127. static int pqi_disable_device_id_wildcards;
  128. module_param_named(disable_device_id_wildcards,
  129. pqi_disable_device_id_wildcards, int, 0644);
  130. MODULE_PARM_DESC(disable_device_id_wildcards,
  131. "Disable device ID wildcards.");
  132. static int pqi_disable_heartbeat;
  133. module_param_named(disable_heartbeat,
  134. pqi_disable_heartbeat, int, 0644);
  135. MODULE_PARM_DESC(disable_heartbeat,
  136. "Disable heartbeat.");
  137. static int pqi_disable_ctrl_shutdown;
  138. module_param_named(disable_ctrl_shutdown,
  139. pqi_disable_ctrl_shutdown, int, 0644);
  140. MODULE_PARM_DESC(disable_ctrl_shutdown,
  141. "Disable controller shutdown when controller locked up.");
  142. static char *pqi_lockup_action_param;
  143. module_param_named(lockup_action,
  144. pqi_lockup_action_param, charp, 0644);
  145. MODULE_PARM_DESC(lockup_action, "Action to take when controller locked up.\n"
  146. "\t\tSupported: none, reboot, panic\n"
  147. "\t\tDefault: none");
  148. static int pqi_expose_ld_first;
  149. module_param_named(expose_ld_first,
  150. pqi_expose_ld_first, int, 0644);
  151. MODULE_PARM_DESC(expose_ld_first, "Expose logical drives before physical drives.");
  152. static int pqi_hide_vsep;
  153. module_param_named(hide_vsep,
  154. pqi_hide_vsep, int, 0644);
  155. MODULE_PARM_DESC(hide_vsep, "Hide the virtual SEP for direct attached drives.");
  156. static int pqi_disable_managed_interrupts;
  157. module_param_named(disable_managed_interrupts,
  158. pqi_disable_managed_interrupts, int, 0644);
  159. MODULE_PARM_DESC(disable_managed_interrupts,
  160. "Disable the kernel automatically assigning SMP affinity to IRQs.");
  161. static unsigned int pqi_ctrl_ready_timeout_secs;
  162. module_param_named(ctrl_ready_timeout,
  163. pqi_ctrl_ready_timeout_secs, uint, 0644);
  164. MODULE_PARM_DESC(ctrl_ready_timeout,
  165. "Timeout in seconds for driver to wait for controller ready.");
  166. static char *raid_levels[] = {
  167. "RAID-0",
  168. "RAID-4",
  169. "RAID-1(1+0)",
  170. "RAID-5",
  171. "RAID-5+1",
  172. "RAID-6",
  173. "RAID-1(Triple)",
  174. };
  175. static char *pqi_raid_level_to_string(u8 raid_level)
  176. {
  177. if (raid_level < ARRAY_SIZE(raid_levels))
  178. return raid_levels[raid_level];
  179. return "RAID UNKNOWN";
  180. }
  181. #define SA_RAID_0 0
  182. #define SA_RAID_4 1
  183. #define SA_RAID_1 2 /* also used for RAID 10 */
  184. #define SA_RAID_5 3 /* also used for RAID 50 */
  185. #define SA_RAID_51 4
  186. #define SA_RAID_6 5 /* also used for RAID 60 */
  187. #define SA_RAID_TRIPLE 6 /* also used for RAID 1+0 Triple */
  188. #define SA_RAID_MAX SA_RAID_TRIPLE
  189. #define SA_RAID_UNKNOWN 0xff
  190. static inline void pqi_scsi_done(struct scsi_cmnd *scmd)
  191. {
  192. pqi_prep_for_scsi_done(scmd);
  193. scsi_done(scmd);
  194. }
  195. static inline void pqi_disable_write_same(struct scsi_device *sdev)
  196. {
  197. sdev->no_write_same = 1;
  198. }
  199. static inline bool pqi_scsi3addr_equal(u8 *scsi3addr1, u8 *scsi3addr2)
  200. {
  201. return memcmp(scsi3addr1, scsi3addr2, 8) == 0;
  202. }
  203. static inline bool pqi_is_logical_device(struct pqi_scsi_dev *device)
  204. {
  205. return !device->is_physical_device;
  206. }
  207. static inline bool pqi_is_external_raid_addr(u8 *scsi3addr)
  208. {
  209. return scsi3addr[2] != 0;
  210. }
  211. static inline bool pqi_ctrl_offline(struct pqi_ctrl_info *ctrl_info)
  212. {
  213. return !ctrl_info->controller_online;
  214. }
  215. static inline void pqi_check_ctrl_health(struct pqi_ctrl_info *ctrl_info)
  216. {
  217. if (ctrl_info->controller_online)
  218. if (!sis_is_firmware_running(ctrl_info))
  219. pqi_take_ctrl_offline(ctrl_info, PQI_FIRMWARE_KERNEL_NOT_UP);
  220. }
  221. static inline bool pqi_is_hba_lunid(u8 *scsi3addr)
  222. {
  223. return pqi_scsi3addr_equal(scsi3addr, RAID_CTLR_LUNID);
  224. }
  225. #define PQI_DRIVER_SCRATCH_PQI_MODE 0x1
  226. #define PQI_DRIVER_SCRATCH_FW_TRIAGE_SUPPORTED 0x2
  227. static inline enum pqi_ctrl_mode pqi_get_ctrl_mode(struct pqi_ctrl_info *ctrl_info)
  228. {
  229. return sis_read_driver_scratch(ctrl_info) & PQI_DRIVER_SCRATCH_PQI_MODE ? PQI_MODE : SIS_MODE;
  230. }
  231. static inline void pqi_save_ctrl_mode(struct pqi_ctrl_info *ctrl_info,
  232. enum pqi_ctrl_mode mode)
  233. {
  234. u32 driver_scratch;
  235. driver_scratch = sis_read_driver_scratch(ctrl_info);
  236. if (mode == PQI_MODE)
  237. driver_scratch |= PQI_DRIVER_SCRATCH_PQI_MODE;
  238. else
  239. driver_scratch &= ~PQI_DRIVER_SCRATCH_PQI_MODE;
  240. sis_write_driver_scratch(ctrl_info, driver_scratch);
  241. }
  242. static inline bool pqi_is_fw_triage_supported(struct pqi_ctrl_info *ctrl_info)
  243. {
  244. return (sis_read_driver_scratch(ctrl_info) & PQI_DRIVER_SCRATCH_FW_TRIAGE_SUPPORTED) != 0;
  245. }
  246. static inline void pqi_save_fw_triage_setting(struct pqi_ctrl_info *ctrl_info, bool is_supported)
  247. {
  248. u32 driver_scratch;
  249. driver_scratch = sis_read_driver_scratch(ctrl_info);
  250. if (is_supported)
  251. driver_scratch |= PQI_DRIVER_SCRATCH_FW_TRIAGE_SUPPORTED;
  252. else
  253. driver_scratch &= ~PQI_DRIVER_SCRATCH_FW_TRIAGE_SUPPORTED;
  254. sis_write_driver_scratch(ctrl_info, driver_scratch);
  255. }
  256. static inline void pqi_ctrl_block_scan(struct pqi_ctrl_info *ctrl_info)
  257. {
  258. ctrl_info->scan_blocked = true;
  259. mutex_lock(&ctrl_info->scan_mutex);
  260. }
  261. static inline void pqi_ctrl_unblock_scan(struct pqi_ctrl_info *ctrl_info)
  262. {
  263. ctrl_info->scan_blocked = false;
  264. mutex_unlock(&ctrl_info->scan_mutex);
  265. }
  266. static inline bool pqi_ctrl_scan_blocked(struct pqi_ctrl_info *ctrl_info)
  267. {
  268. return ctrl_info->scan_blocked;
  269. }
  270. static inline void pqi_ctrl_block_device_reset(struct pqi_ctrl_info *ctrl_info)
  271. {
  272. mutex_lock(&ctrl_info->lun_reset_mutex);
  273. }
  274. static inline void pqi_ctrl_unblock_device_reset(struct pqi_ctrl_info *ctrl_info)
  275. {
  276. mutex_unlock(&ctrl_info->lun_reset_mutex);
  277. }
  278. static inline void pqi_scsi_block_requests(struct pqi_ctrl_info *ctrl_info)
  279. {
  280. struct Scsi_Host *shost;
  281. unsigned int num_loops;
  282. int msecs_sleep;
  283. shost = ctrl_info->scsi_host;
  284. scsi_block_requests(shost);
  285. num_loops = 0;
  286. msecs_sleep = 20;
  287. while (scsi_host_busy(shost)) {
  288. num_loops++;
  289. if (num_loops == 10)
  290. msecs_sleep = 500;
  291. msleep(msecs_sleep);
  292. }
  293. }
  294. static inline void pqi_scsi_unblock_requests(struct pqi_ctrl_info *ctrl_info)
  295. {
  296. scsi_unblock_requests(ctrl_info->scsi_host);
  297. }
  298. static inline void pqi_ctrl_busy(struct pqi_ctrl_info *ctrl_info)
  299. {
  300. atomic_inc(&ctrl_info->num_busy_threads);
  301. }
  302. static inline void pqi_ctrl_unbusy(struct pqi_ctrl_info *ctrl_info)
  303. {
  304. atomic_dec(&ctrl_info->num_busy_threads);
  305. }
  306. static inline bool pqi_ctrl_blocked(struct pqi_ctrl_info *ctrl_info)
  307. {
  308. return ctrl_info->block_requests;
  309. }
  310. static inline void pqi_ctrl_block_requests(struct pqi_ctrl_info *ctrl_info)
  311. {
  312. ctrl_info->block_requests = true;
  313. }
  314. static inline void pqi_ctrl_unblock_requests(struct pqi_ctrl_info *ctrl_info)
  315. {
  316. ctrl_info->block_requests = false;
  317. wake_up_all(&ctrl_info->block_requests_wait);
  318. }
  319. static void pqi_wait_if_ctrl_blocked(struct pqi_ctrl_info *ctrl_info)
  320. {
  321. if (!pqi_ctrl_blocked(ctrl_info))
  322. return;
  323. atomic_inc(&ctrl_info->num_blocked_threads);
  324. wait_event(ctrl_info->block_requests_wait,
  325. !pqi_ctrl_blocked(ctrl_info));
  326. atomic_dec(&ctrl_info->num_blocked_threads);
  327. }
  328. #define PQI_QUIESCE_WARNING_TIMEOUT_SECS 10
  329. static inline void pqi_ctrl_wait_until_quiesced(struct pqi_ctrl_info *ctrl_info)
  330. {
  331. unsigned long start_jiffies;
  332. unsigned long warning_timeout;
  333. bool displayed_warning;
  334. displayed_warning = false;
  335. start_jiffies = jiffies;
  336. warning_timeout = (PQI_QUIESCE_WARNING_TIMEOUT_SECS * HZ) + start_jiffies;
  337. while (atomic_read(&ctrl_info->num_busy_threads) >
  338. atomic_read(&ctrl_info->num_blocked_threads)) {
  339. if (time_after(jiffies, warning_timeout)) {
  340. dev_warn(&ctrl_info->pci_dev->dev,
  341. "waiting %u seconds for driver activity to quiesce\n",
  342. jiffies_to_msecs(jiffies - start_jiffies) / 1000);
  343. displayed_warning = true;
  344. warning_timeout = (PQI_QUIESCE_WARNING_TIMEOUT_SECS * HZ) + jiffies;
  345. }
  346. usleep_range(1000, 2000);
  347. }
  348. if (displayed_warning)
  349. dev_warn(&ctrl_info->pci_dev->dev,
  350. "driver activity quiesced after waiting for %u seconds\n",
  351. jiffies_to_msecs(jiffies - start_jiffies) / 1000);
  352. }
  353. static inline bool pqi_device_offline(struct pqi_scsi_dev *device)
  354. {
  355. return device->device_offline;
  356. }
  357. static inline void pqi_ctrl_ofa_start(struct pqi_ctrl_info *ctrl_info)
  358. {
  359. mutex_lock(&ctrl_info->ofa_mutex);
  360. }
  361. static inline void pqi_ctrl_ofa_done(struct pqi_ctrl_info *ctrl_info)
  362. {
  363. mutex_unlock(&ctrl_info->ofa_mutex);
  364. }
  365. static inline void pqi_wait_until_ofa_finished(struct pqi_ctrl_info *ctrl_info)
  366. {
  367. mutex_lock(&ctrl_info->ofa_mutex);
  368. mutex_unlock(&ctrl_info->ofa_mutex);
  369. }
  370. static inline bool pqi_ofa_in_progress(struct pqi_ctrl_info *ctrl_info)
  371. {
  372. return mutex_is_locked(&ctrl_info->ofa_mutex);
  373. }
  374. static inline void pqi_device_remove_start(struct pqi_scsi_dev *device)
  375. {
  376. device->in_remove = true;
  377. }
  378. static inline bool pqi_device_in_remove(struct pqi_scsi_dev *device)
  379. {
  380. return device->in_remove;
  381. }
  382. static inline void pqi_device_reset_start(struct pqi_scsi_dev *device, u8 lun)
  383. {
  384. device->in_reset[lun] = true;
  385. }
  386. static inline void pqi_device_reset_done(struct pqi_scsi_dev *device, u8 lun)
  387. {
  388. device->in_reset[lun] = false;
  389. }
  390. static inline bool pqi_device_in_reset(struct pqi_scsi_dev *device, u8 lun)
  391. {
  392. return device->in_reset[lun];
  393. }
  394. static inline int pqi_event_type_to_event_index(unsigned int event_type)
  395. {
  396. int index;
  397. for (index = 0; index < ARRAY_SIZE(pqi_supported_event_types); index++)
  398. if (event_type == pqi_supported_event_types[index])
  399. return index;
  400. return -1;
  401. }
  402. static inline bool pqi_is_supported_event(unsigned int event_type)
  403. {
  404. return pqi_event_type_to_event_index(event_type) != -1;
  405. }
  406. static inline void pqi_schedule_rescan_worker_with_delay(struct pqi_ctrl_info *ctrl_info,
  407. unsigned long delay)
  408. {
  409. if (pqi_ctrl_offline(ctrl_info))
  410. return;
  411. schedule_delayed_work(&ctrl_info->rescan_work, delay);
  412. }
  413. static inline void pqi_schedule_rescan_worker(struct pqi_ctrl_info *ctrl_info)
  414. {
  415. pqi_schedule_rescan_worker_with_delay(ctrl_info, 0);
  416. }
  417. #define PQI_RESCAN_WORK_DELAY (10 * HZ)
  418. static inline void pqi_schedule_rescan_worker_delayed(struct pqi_ctrl_info *ctrl_info)
  419. {
  420. pqi_schedule_rescan_worker_with_delay(ctrl_info, PQI_RESCAN_WORK_DELAY);
  421. }
  422. static inline void pqi_cancel_rescan_worker(struct pqi_ctrl_info *ctrl_info)
  423. {
  424. cancel_delayed_work_sync(&ctrl_info->rescan_work);
  425. }
  426. static inline u32 pqi_read_heartbeat_counter(struct pqi_ctrl_info *ctrl_info)
  427. {
  428. if (!ctrl_info->heartbeat_counter)
  429. return 0;
  430. return readl(ctrl_info->heartbeat_counter);
  431. }
  432. static inline u8 pqi_read_soft_reset_status(struct pqi_ctrl_info *ctrl_info)
  433. {
  434. return readb(ctrl_info->soft_reset_status);
  435. }
  436. static inline void pqi_clear_soft_reset_status(struct pqi_ctrl_info *ctrl_info)
  437. {
  438. u8 status;
  439. status = pqi_read_soft_reset_status(ctrl_info);
  440. status &= ~PQI_SOFT_RESET_ABORT;
  441. writeb(status, ctrl_info->soft_reset_status);
  442. }
  443. static inline bool pqi_is_io_high_priority(struct pqi_scsi_dev *device, struct scsi_cmnd *scmd)
  444. {
  445. bool io_high_prio;
  446. int priority_class;
  447. io_high_prio = false;
  448. if (device->ncq_prio_enable) {
  449. priority_class =
  450. IOPRIO_PRIO_CLASS(req_get_ioprio(scsi_cmd_to_rq(scmd)));
  451. if (priority_class == IOPRIO_CLASS_RT) {
  452. /* Set NCQ priority for read/write commands. */
  453. switch (scmd->cmnd[0]) {
  454. case WRITE_16:
  455. case READ_16:
  456. case WRITE_12:
  457. case READ_12:
  458. case WRITE_10:
  459. case READ_10:
  460. case WRITE_6:
  461. case READ_6:
  462. io_high_prio = true;
  463. break;
  464. }
  465. }
  466. }
  467. return io_high_prio;
  468. }
  469. static int pqi_map_single(struct pci_dev *pci_dev,
  470. struct pqi_sg_descriptor *sg_descriptor, void *buffer,
  471. size_t buffer_length, enum dma_data_direction data_direction)
  472. {
  473. dma_addr_t bus_address;
  474. if (!buffer || buffer_length == 0 || data_direction == DMA_NONE)
  475. return 0;
  476. bus_address = dma_map_single(&pci_dev->dev, buffer, buffer_length,
  477. data_direction);
  478. if (dma_mapping_error(&pci_dev->dev, bus_address))
  479. return -ENOMEM;
  480. put_unaligned_le64((u64)bus_address, &sg_descriptor->address);
  481. put_unaligned_le32(buffer_length, &sg_descriptor->length);
  482. put_unaligned_le32(CISS_SG_LAST, &sg_descriptor->flags);
  483. return 0;
  484. }
  485. static void pqi_pci_unmap(struct pci_dev *pci_dev,
  486. struct pqi_sg_descriptor *descriptors, int num_descriptors,
  487. enum dma_data_direction data_direction)
  488. {
  489. int i;
  490. if (data_direction == DMA_NONE)
  491. return;
  492. for (i = 0; i < num_descriptors; i++)
  493. dma_unmap_single(&pci_dev->dev,
  494. (dma_addr_t)get_unaligned_le64(&descriptors[i].address),
  495. get_unaligned_le32(&descriptors[i].length),
  496. data_direction);
  497. }
  498. static int pqi_build_raid_path_request(struct pqi_ctrl_info *ctrl_info,
  499. struct pqi_raid_path_request *request, u8 cmd,
  500. u8 *scsi3addr, void *buffer, size_t buffer_length,
  501. u16 vpd_page, enum dma_data_direction *dir)
  502. {
  503. u8 *cdb;
  504. size_t cdb_length = buffer_length;
  505. memset(request, 0, sizeof(*request));
  506. request->header.iu_type = PQI_REQUEST_IU_RAID_PATH_IO;
  507. put_unaligned_le16(offsetof(struct pqi_raid_path_request,
  508. sg_descriptors[1]) - PQI_REQUEST_HEADER_LENGTH,
  509. &request->header.iu_length);
  510. put_unaligned_le32(buffer_length, &request->buffer_length);
  511. memcpy(request->lun_number, scsi3addr, sizeof(request->lun_number));
  512. request->task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  513. request->additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_0;
  514. cdb = request->cdb;
  515. switch (cmd) {
  516. case INQUIRY:
  517. request->data_direction = SOP_READ_FLAG;
  518. cdb[0] = INQUIRY;
  519. if (vpd_page & VPD_PAGE) {
  520. cdb[1] = 0x1;
  521. cdb[2] = (u8)vpd_page;
  522. }
  523. cdb[4] = (u8)cdb_length;
  524. break;
  525. case CISS_REPORT_LOG:
  526. case CISS_REPORT_PHYS:
  527. request->data_direction = SOP_READ_FLAG;
  528. cdb[0] = cmd;
  529. if (cmd == CISS_REPORT_PHYS) {
  530. if (ctrl_info->rpl_extended_format_4_5_supported)
  531. cdb[1] = CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_4;
  532. else
  533. cdb[1] = CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_2;
  534. } else {
  535. cdb[1] = ctrl_info->ciss_report_log_flags;
  536. }
  537. put_unaligned_be32(cdb_length, &cdb[6]);
  538. break;
  539. case CISS_GET_RAID_MAP:
  540. request->data_direction = SOP_READ_FLAG;
  541. cdb[0] = CISS_READ;
  542. cdb[1] = CISS_GET_RAID_MAP;
  543. put_unaligned_be32(cdb_length, &cdb[6]);
  544. break;
  545. case SA_FLUSH_CACHE:
  546. request->header.driver_flags = PQI_DRIVER_NONBLOCKABLE_REQUEST;
  547. request->data_direction = SOP_WRITE_FLAG;
  548. cdb[0] = BMIC_WRITE;
  549. cdb[6] = BMIC_FLUSH_CACHE;
  550. put_unaligned_be16(cdb_length, &cdb[7]);
  551. break;
  552. case BMIC_SENSE_DIAG_OPTIONS:
  553. cdb_length = 0;
  554. fallthrough;
  555. case BMIC_IDENTIFY_CONTROLLER:
  556. case BMIC_IDENTIFY_PHYSICAL_DEVICE:
  557. case BMIC_SENSE_SUBSYSTEM_INFORMATION:
  558. case BMIC_SENSE_FEATURE:
  559. request->data_direction = SOP_READ_FLAG;
  560. cdb[0] = BMIC_READ;
  561. cdb[6] = cmd;
  562. put_unaligned_be16(cdb_length, &cdb[7]);
  563. break;
  564. case BMIC_SET_DIAG_OPTIONS:
  565. cdb_length = 0;
  566. fallthrough;
  567. case BMIC_WRITE_HOST_WELLNESS:
  568. request->data_direction = SOP_WRITE_FLAG;
  569. cdb[0] = BMIC_WRITE;
  570. cdb[6] = cmd;
  571. put_unaligned_be16(cdb_length, &cdb[7]);
  572. break;
  573. case BMIC_CSMI_PASSTHRU:
  574. request->data_direction = SOP_BIDIRECTIONAL;
  575. cdb[0] = BMIC_WRITE;
  576. cdb[5] = CSMI_CC_SAS_SMP_PASSTHRU;
  577. cdb[6] = cmd;
  578. put_unaligned_be16(cdb_length, &cdb[7]);
  579. break;
  580. default:
  581. dev_err(&ctrl_info->pci_dev->dev, "unknown command 0x%c\n", cmd);
  582. break;
  583. }
  584. switch (request->data_direction) {
  585. case SOP_READ_FLAG:
  586. *dir = DMA_FROM_DEVICE;
  587. break;
  588. case SOP_WRITE_FLAG:
  589. *dir = DMA_TO_DEVICE;
  590. break;
  591. case SOP_NO_DIRECTION_FLAG:
  592. *dir = DMA_NONE;
  593. break;
  594. default:
  595. *dir = DMA_BIDIRECTIONAL;
  596. break;
  597. }
  598. return pqi_map_single(ctrl_info->pci_dev, &request->sg_descriptors[0],
  599. buffer, buffer_length, *dir);
  600. }
  601. static inline void pqi_reinit_io_request(struct pqi_io_request *io_request)
  602. {
  603. io_request->scmd = NULL;
  604. io_request->status = 0;
  605. io_request->error_info = NULL;
  606. io_request->raid_bypass = false;
  607. }
  608. static inline struct pqi_io_request *pqi_alloc_io_request(struct pqi_ctrl_info *ctrl_info, struct scsi_cmnd *scmd)
  609. {
  610. struct pqi_io_request *io_request;
  611. u16 i;
  612. if (scmd) { /* SML I/O request */
  613. u32 blk_tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd));
  614. i = blk_mq_unique_tag_to_tag(blk_tag);
  615. io_request = &ctrl_info->io_request_pool[i];
  616. if (atomic_inc_return(&io_request->refcount) > 1) {
  617. atomic_dec(&io_request->refcount);
  618. return NULL;
  619. }
  620. } else { /* IOCTL or driver internal request */
  621. /*
  622. * benignly racy - may have to wait for an open slot.
  623. * command slot range is scsi_ml_can_queue -
  624. * [scsi_ml_can_queue + (PQI_RESERVED_IO_SLOTS - 1)]
  625. */
  626. i = 0;
  627. while (1) {
  628. io_request = &ctrl_info->io_request_pool[ctrl_info->scsi_ml_can_queue + i];
  629. if (atomic_inc_return(&io_request->refcount) == 1)
  630. break;
  631. atomic_dec(&io_request->refcount);
  632. i = (i + 1) % PQI_RESERVED_IO_SLOTS;
  633. }
  634. }
  635. if (io_request)
  636. pqi_reinit_io_request(io_request);
  637. return io_request;
  638. }
  639. static void pqi_free_io_request(struct pqi_io_request *io_request)
  640. {
  641. atomic_dec(&io_request->refcount);
  642. }
  643. static int pqi_send_scsi_raid_request(struct pqi_ctrl_info *ctrl_info, u8 cmd,
  644. u8 *scsi3addr, void *buffer, size_t buffer_length, u16 vpd_page,
  645. struct pqi_raid_error_info *error_info)
  646. {
  647. int rc;
  648. struct pqi_raid_path_request request;
  649. enum dma_data_direction dir;
  650. rc = pqi_build_raid_path_request(ctrl_info, &request, cmd, scsi3addr,
  651. buffer, buffer_length, vpd_page, &dir);
  652. if (rc)
  653. return rc;
  654. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, error_info);
  655. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1, dir);
  656. return rc;
  657. }
  658. /* helper functions for pqi_send_scsi_raid_request */
  659. static inline int pqi_send_ctrl_raid_request(struct pqi_ctrl_info *ctrl_info,
  660. u8 cmd, void *buffer, size_t buffer_length)
  661. {
  662. return pqi_send_scsi_raid_request(ctrl_info, cmd, RAID_CTLR_LUNID,
  663. buffer, buffer_length, 0, NULL);
  664. }
  665. static inline int pqi_send_ctrl_raid_with_error(struct pqi_ctrl_info *ctrl_info,
  666. u8 cmd, void *buffer, size_t buffer_length,
  667. struct pqi_raid_error_info *error_info)
  668. {
  669. return pqi_send_scsi_raid_request(ctrl_info, cmd, RAID_CTLR_LUNID,
  670. buffer, buffer_length, 0, error_info);
  671. }
  672. static inline int pqi_identify_controller(struct pqi_ctrl_info *ctrl_info,
  673. struct bmic_identify_controller *buffer)
  674. {
  675. return pqi_send_ctrl_raid_request(ctrl_info, BMIC_IDENTIFY_CONTROLLER,
  676. buffer, sizeof(*buffer));
  677. }
  678. static inline int pqi_sense_subsystem_info(struct pqi_ctrl_info *ctrl_info,
  679. struct bmic_sense_subsystem_info *sense_info)
  680. {
  681. return pqi_send_ctrl_raid_request(ctrl_info,
  682. BMIC_SENSE_SUBSYSTEM_INFORMATION, sense_info,
  683. sizeof(*sense_info));
  684. }
  685. static inline int pqi_scsi_inquiry(struct pqi_ctrl_info *ctrl_info,
  686. u8 *scsi3addr, u16 vpd_page, void *buffer, size_t buffer_length)
  687. {
  688. return pqi_send_scsi_raid_request(ctrl_info, INQUIRY, scsi3addr,
  689. buffer, buffer_length, vpd_page, NULL);
  690. }
  691. static int pqi_identify_physical_device(struct pqi_ctrl_info *ctrl_info,
  692. struct pqi_scsi_dev *device,
  693. struct bmic_identify_physical_device *buffer, size_t buffer_length)
  694. {
  695. int rc;
  696. enum dma_data_direction dir;
  697. u16 bmic_device_index;
  698. struct pqi_raid_path_request request;
  699. rc = pqi_build_raid_path_request(ctrl_info, &request,
  700. BMIC_IDENTIFY_PHYSICAL_DEVICE, RAID_CTLR_LUNID, buffer,
  701. buffer_length, 0, &dir);
  702. if (rc)
  703. return rc;
  704. bmic_device_index = CISS_GET_DRIVE_NUMBER(device->scsi3addr);
  705. request.cdb[2] = (u8)bmic_device_index;
  706. request.cdb[9] = (u8)(bmic_device_index >> 8);
  707. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, NULL);
  708. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1, dir);
  709. return rc;
  710. }
  711. static inline u32 pqi_aio_limit_to_bytes(__le16 *limit)
  712. {
  713. u32 bytes;
  714. bytes = get_unaligned_le16(limit);
  715. if (bytes == 0)
  716. bytes = ~0;
  717. else
  718. bytes *= 1024;
  719. return bytes;
  720. }
  721. #pragma pack(1)
  722. struct bmic_sense_feature_buffer {
  723. struct bmic_sense_feature_buffer_header header;
  724. struct bmic_sense_feature_io_page_aio_subpage aio_subpage;
  725. };
  726. #pragma pack()
  727. #define MINIMUM_AIO_SUBPAGE_BUFFER_LENGTH \
  728. offsetofend(struct bmic_sense_feature_buffer, \
  729. aio_subpage.max_write_raid_1_10_3drive)
  730. #define MINIMUM_AIO_SUBPAGE_LENGTH \
  731. (offsetofend(struct bmic_sense_feature_io_page_aio_subpage, \
  732. max_write_raid_1_10_3drive) - \
  733. sizeof_field(struct bmic_sense_feature_io_page_aio_subpage, header))
  734. static int pqi_get_advanced_raid_bypass_config(struct pqi_ctrl_info *ctrl_info)
  735. {
  736. int rc;
  737. enum dma_data_direction dir;
  738. struct pqi_raid_path_request request;
  739. struct bmic_sense_feature_buffer *buffer;
  740. buffer = kmalloc(sizeof(*buffer), GFP_KERNEL);
  741. if (!buffer)
  742. return -ENOMEM;
  743. rc = pqi_build_raid_path_request(ctrl_info, &request, BMIC_SENSE_FEATURE, RAID_CTLR_LUNID,
  744. buffer, sizeof(*buffer), 0, &dir);
  745. if (rc)
  746. goto error;
  747. request.cdb[2] = BMIC_SENSE_FEATURE_IO_PAGE;
  748. request.cdb[3] = BMIC_SENSE_FEATURE_IO_PAGE_AIO_SUBPAGE;
  749. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, NULL);
  750. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1, dir);
  751. if (rc)
  752. goto error;
  753. if (buffer->header.page_code != BMIC_SENSE_FEATURE_IO_PAGE ||
  754. buffer->header.subpage_code !=
  755. BMIC_SENSE_FEATURE_IO_PAGE_AIO_SUBPAGE ||
  756. get_unaligned_le16(&buffer->header.buffer_length) <
  757. MINIMUM_AIO_SUBPAGE_BUFFER_LENGTH ||
  758. buffer->aio_subpage.header.page_code !=
  759. BMIC_SENSE_FEATURE_IO_PAGE ||
  760. buffer->aio_subpage.header.subpage_code !=
  761. BMIC_SENSE_FEATURE_IO_PAGE_AIO_SUBPAGE ||
  762. get_unaligned_le16(&buffer->aio_subpage.header.page_length) <
  763. MINIMUM_AIO_SUBPAGE_LENGTH) {
  764. goto error;
  765. }
  766. ctrl_info->max_transfer_encrypted_sas_sata =
  767. pqi_aio_limit_to_bytes(
  768. &buffer->aio_subpage.max_transfer_encrypted_sas_sata);
  769. ctrl_info->max_transfer_encrypted_nvme =
  770. pqi_aio_limit_to_bytes(
  771. &buffer->aio_subpage.max_transfer_encrypted_nvme);
  772. ctrl_info->max_write_raid_5_6 =
  773. pqi_aio_limit_to_bytes(
  774. &buffer->aio_subpage.max_write_raid_5_6);
  775. ctrl_info->max_write_raid_1_10_2drive =
  776. pqi_aio_limit_to_bytes(
  777. &buffer->aio_subpage.max_write_raid_1_10_2drive);
  778. ctrl_info->max_write_raid_1_10_3drive =
  779. pqi_aio_limit_to_bytes(
  780. &buffer->aio_subpage.max_write_raid_1_10_3drive);
  781. error:
  782. kfree(buffer);
  783. return rc;
  784. }
  785. static int pqi_flush_cache(struct pqi_ctrl_info *ctrl_info,
  786. enum bmic_flush_cache_shutdown_event shutdown_event)
  787. {
  788. int rc;
  789. struct bmic_flush_cache *flush_cache;
  790. flush_cache = kzalloc(sizeof(*flush_cache), GFP_KERNEL);
  791. if (!flush_cache)
  792. return -ENOMEM;
  793. flush_cache->shutdown_event = shutdown_event;
  794. rc = pqi_send_ctrl_raid_request(ctrl_info, SA_FLUSH_CACHE, flush_cache,
  795. sizeof(*flush_cache));
  796. kfree(flush_cache);
  797. return rc;
  798. }
  799. int pqi_csmi_smp_passthru(struct pqi_ctrl_info *ctrl_info,
  800. struct bmic_csmi_smp_passthru_buffer *buffer, size_t buffer_length,
  801. struct pqi_raid_error_info *error_info)
  802. {
  803. return pqi_send_ctrl_raid_with_error(ctrl_info, BMIC_CSMI_PASSTHRU,
  804. buffer, buffer_length, error_info);
  805. }
  806. #define PQI_FETCH_PTRAID_DATA (1 << 31)
  807. static int pqi_set_diag_rescan(struct pqi_ctrl_info *ctrl_info)
  808. {
  809. int rc;
  810. struct bmic_diag_options *diag;
  811. diag = kzalloc(sizeof(*diag), GFP_KERNEL);
  812. if (!diag)
  813. return -ENOMEM;
  814. rc = pqi_send_ctrl_raid_request(ctrl_info, BMIC_SENSE_DIAG_OPTIONS,
  815. diag, sizeof(*diag));
  816. if (rc)
  817. goto out;
  818. diag->options |= cpu_to_le32(PQI_FETCH_PTRAID_DATA);
  819. rc = pqi_send_ctrl_raid_request(ctrl_info, BMIC_SET_DIAG_OPTIONS, diag,
  820. sizeof(*diag));
  821. out:
  822. kfree(diag);
  823. return rc;
  824. }
  825. static inline int pqi_write_host_wellness(struct pqi_ctrl_info *ctrl_info,
  826. void *buffer, size_t buffer_length)
  827. {
  828. return pqi_send_ctrl_raid_request(ctrl_info, BMIC_WRITE_HOST_WELLNESS,
  829. buffer, buffer_length);
  830. }
  831. #pragma pack(1)
  832. struct bmic_host_wellness_driver_version {
  833. u8 start_tag[4];
  834. u8 driver_version_tag[2];
  835. __le16 driver_version_length;
  836. char driver_version[32];
  837. u8 dont_write_tag[2];
  838. u8 end_tag[2];
  839. };
  840. #pragma pack()
  841. static int pqi_write_driver_version_to_host_wellness(
  842. struct pqi_ctrl_info *ctrl_info)
  843. {
  844. int rc;
  845. struct bmic_host_wellness_driver_version *buffer;
  846. size_t buffer_length;
  847. buffer_length = sizeof(*buffer);
  848. buffer = kmalloc(buffer_length, GFP_KERNEL);
  849. if (!buffer)
  850. return -ENOMEM;
  851. buffer->start_tag[0] = '<';
  852. buffer->start_tag[1] = 'H';
  853. buffer->start_tag[2] = 'W';
  854. buffer->start_tag[3] = '>';
  855. buffer->driver_version_tag[0] = 'D';
  856. buffer->driver_version_tag[1] = 'V';
  857. put_unaligned_le16(sizeof(buffer->driver_version),
  858. &buffer->driver_version_length);
  859. strscpy(buffer->driver_version, "Linux " DRIVER_VERSION,
  860. sizeof(buffer->driver_version));
  861. buffer->dont_write_tag[0] = 'D';
  862. buffer->dont_write_tag[1] = 'W';
  863. buffer->end_tag[0] = 'Z';
  864. buffer->end_tag[1] = 'Z';
  865. rc = pqi_write_host_wellness(ctrl_info, buffer, buffer_length);
  866. kfree(buffer);
  867. return rc;
  868. }
  869. #pragma pack(1)
  870. struct bmic_host_wellness_time {
  871. u8 start_tag[4];
  872. u8 time_tag[2];
  873. __le16 time_length;
  874. u8 time[8];
  875. u8 dont_write_tag[2];
  876. u8 end_tag[2];
  877. };
  878. #pragma pack()
  879. static int pqi_write_current_time_to_host_wellness(
  880. struct pqi_ctrl_info *ctrl_info)
  881. {
  882. int rc;
  883. struct bmic_host_wellness_time *buffer;
  884. size_t buffer_length;
  885. time64_t local_time;
  886. unsigned int year;
  887. struct tm tm;
  888. buffer_length = sizeof(*buffer);
  889. buffer = kmalloc(buffer_length, GFP_KERNEL);
  890. if (!buffer)
  891. return -ENOMEM;
  892. buffer->start_tag[0] = '<';
  893. buffer->start_tag[1] = 'H';
  894. buffer->start_tag[2] = 'W';
  895. buffer->start_tag[3] = '>';
  896. buffer->time_tag[0] = 'T';
  897. buffer->time_tag[1] = 'D';
  898. put_unaligned_le16(sizeof(buffer->time),
  899. &buffer->time_length);
  900. local_time = ktime_get_real_seconds();
  901. time64_to_tm(local_time, -sys_tz.tz_minuteswest * 60, &tm);
  902. year = tm.tm_year + 1900;
  903. buffer->time[0] = bin2bcd(tm.tm_hour);
  904. buffer->time[1] = bin2bcd(tm.tm_min);
  905. buffer->time[2] = bin2bcd(tm.tm_sec);
  906. buffer->time[3] = 0;
  907. buffer->time[4] = bin2bcd(tm.tm_mon + 1);
  908. buffer->time[5] = bin2bcd(tm.tm_mday);
  909. buffer->time[6] = bin2bcd(year / 100);
  910. buffer->time[7] = bin2bcd(year % 100);
  911. buffer->dont_write_tag[0] = 'D';
  912. buffer->dont_write_tag[1] = 'W';
  913. buffer->end_tag[0] = 'Z';
  914. buffer->end_tag[1] = 'Z';
  915. rc = pqi_write_host_wellness(ctrl_info, buffer, buffer_length);
  916. kfree(buffer);
  917. return rc;
  918. }
  919. #define PQI_UPDATE_TIME_WORK_INTERVAL (24UL * 60 * 60 * HZ)
  920. static void pqi_update_time_worker(struct work_struct *work)
  921. {
  922. int rc;
  923. struct pqi_ctrl_info *ctrl_info;
  924. ctrl_info = container_of(to_delayed_work(work), struct pqi_ctrl_info,
  925. update_time_work);
  926. rc = pqi_write_current_time_to_host_wellness(ctrl_info);
  927. if (rc)
  928. dev_warn(&ctrl_info->pci_dev->dev,
  929. "error updating time on controller\n");
  930. schedule_delayed_work(&ctrl_info->update_time_work,
  931. PQI_UPDATE_TIME_WORK_INTERVAL);
  932. }
  933. static inline void pqi_schedule_update_time_worker(struct pqi_ctrl_info *ctrl_info)
  934. {
  935. schedule_delayed_work(&ctrl_info->update_time_work, 0);
  936. }
  937. static inline void pqi_cancel_update_time_worker(struct pqi_ctrl_info *ctrl_info)
  938. {
  939. cancel_delayed_work_sync(&ctrl_info->update_time_work);
  940. }
  941. static inline int pqi_report_luns(struct pqi_ctrl_info *ctrl_info, u8 cmd, void *buffer,
  942. size_t buffer_length)
  943. {
  944. return pqi_send_ctrl_raid_request(ctrl_info, cmd, buffer, buffer_length);
  945. }
  946. static int pqi_report_phys_logical_luns(struct pqi_ctrl_info *ctrl_info, u8 cmd, void **buffer)
  947. {
  948. int rc;
  949. size_t lun_list_length;
  950. size_t lun_data_length;
  951. size_t new_lun_list_length;
  952. void *lun_data = NULL;
  953. struct report_lun_header *report_lun_header;
  954. report_lun_header = kmalloc(sizeof(*report_lun_header), GFP_KERNEL);
  955. if (!report_lun_header) {
  956. rc = -ENOMEM;
  957. goto out;
  958. }
  959. rc = pqi_report_luns(ctrl_info, cmd, report_lun_header, sizeof(*report_lun_header));
  960. if (rc)
  961. goto out;
  962. lun_list_length = get_unaligned_be32(&report_lun_header->list_length);
  963. again:
  964. lun_data_length = sizeof(struct report_lun_header) + lun_list_length;
  965. lun_data = kmalloc(lun_data_length, GFP_KERNEL);
  966. if (!lun_data) {
  967. rc = -ENOMEM;
  968. goto out;
  969. }
  970. if (lun_list_length == 0) {
  971. memcpy(lun_data, report_lun_header, sizeof(*report_lun_header));
  972. goto out;
  973. }
  974. rc = pqi_report_luns(ctrl_info, cmd, lun_data, lun_data_length);
  975. if (rc)
  976. goto out;
  977. new_lun_list_length =
  978. get_unaligned_be32(&((struct report_lun_header *)lun_data)->list_length);
  979. if (new_lun_list_length > lun_list_length) {
  980. lun_list_length = new_lun_list_length;
  981. kfree(lun_data);
  982. goto again;
  983. }
  984. out:
  985. kfree(report_lun_header);
  986. if (rc) {
  987. kfree(lun_data);
  988. lun_data = NULL;
  989. }
  990. *buffer = lun_data;
  991. return rc;
  992. }
  993. static inline int pqi_report_phys_luns(struct pqi_ctrl_info *ctrl_info, void **buffer)
  994. {
  995. int rc;
  996. unsigned int i;
  997. u8 rpl_response_format;
  998. u32 num_physicals;
  999. void *rpl_list;
  1000. struct report_lun_header *rpl_header;
  1001. struct report_phys_lun_8byte_wwid_list *rpl_8byte_wwid_list;
  1002. struct report_phys_lun_16byte_wwid_list *rpl_16byte_wwid_list;
  1003. rc = pqi_report_phys_logical_luns(ctrl_info, CISS_REPORT_PHYS, &rpl_list);
  1004. if (rc)
  1005. return rc;
  1006. if (ctrl_info->rpl_extended_format_4_5_supported) {
  1007. rpl_header = rpl_list;
  1008. rpl_response_format = rpl_header->flags & CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_MASK;
  1009. if (rpl_response_format == CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_4) {
  1010. *buffer = rpl_list;
  1011. return 0;
  1012. } else if (rpl_response_format != CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_2) {
  1013. dev_err(&ctrl_info->pci_dev->dev,
  1014. "RPL returned unsupported data format %u\n",
  1015. rpl_response_format);
  1016. return -EINVAL;
  1017. } else {
  1018. dev_warn(&ctrl_info->pci_dev->dev,
  1019. "RPL returned extended format 2 instead of 4\n");
  1020. }
  1021. }
  1022. rpl_8byte_wwid_list = rpl_list;
  1023. num_physicals = get_unaligned_be32(&rpl_8byte_wwid_list->header.list_length) / sizeof(rpl_8byte_wwid_list->lun_entries[0]);
  1024. rpl_16byte_wwid_list = kmalloc(struct_size(rpl_16byte_wwid_list, lun_entries,
  1025. num_physicals), GFP_KERNEL);
  1026. if (!rpl_16byte_wwid_list)
  1027. return -ENOMEM;
  1028. put_unaligned_be32(num_physicals * sizeof(struct report_phys_lun_16byte_wwid),
  1029. &rpl_16byte_wwid_list->header.list_length);
  1030. rpl_16byte_wwid_list->header.flags = rpl_8byte_wwid_list->header.flags;
  1031. for (i = 0; i < num_physicals; i++) {
  1032. memcpy(&rpl_16byte_wwid_list->lun_entries[i].lunid, &rpl_8byte_wwid_list->lun_entries[i].lunid, sizeof(rpl_8byte_wwid_list->lun_entries[i].lunid));
  1033. memcpy(&rpl_16byte_wwid_list->lun_entries[i].wwid[0], &rpl_8byte_wwid_list->lun_entries[i].wwid, sizeof(rpl_8byte_wwid_list->lun_entries[i].wwid));
  1034. memset(&rpl_16byte_wwid_list->lun_entries[i].wwid[8], 0, 8);
  1035. rpl_16byte_wwid_list->lun_entries[i].device_type = rpl_8byte_wwid_list->lun_entries[i].device_type;
  1036. rpl_16byte_wwid_list->lun_entries[i].device_flags = rpl_8byte_wwid_list->lun_entries[i].device_flags;
  1037. rpl_16byte_wwid_list->lun_entries[i].lun_count = rpl_8byte_wwid_list->lun_entries[i].lun_count;
  1038. rpl_16byte_wwid_list->lun_entries[i].redundant_paths = rpl_8byte_wwid_list->lun_entries[i].redundant_paths;
  1039. rpl_16byte_wwid_list->lun_entries[i].aio_handle = rpl_8byte_wwid_list->lun_entries[i].aio_handle;
  1040. }
  1041. kfree(rpl_8byte_wwid_list);
  1042. *buffer = rpl_16byte_wwid_list;
  1043. return 0;
  1044. }
  1045. static inline int pqi_report_logical_luns(struct pqi_ctrl_info *ctrl_info, void **buffer)
  1046. {
  1047. return pqi_report_phys_logical_luns(ctrl_info, CISS_REPORT_LOG, buffer);
  1048. }
  1049. static int pqi_get_device_lists(struct pqi_ctrl_info *ctrl_info,
  1050. struct report_phys_lun_16byte_wwid_list **physdev_list,
  1051. struct report_log_lun_list **logdev_list)
  1052. {
  1053. int rc;
  1054. size_t logdev_list_length;
  1055. size_t logdev_data_length;
  1056. struct report_log_lun_list *internal_logdev_list;
  1057. struct report_log_lun_list *logdev_data;
  1058. struct report_lun_header report_lun_header;
  1059. rc = pqi_report_phys_luns(ctrl_info, (void **)physdev_list);
  1060. if (rc)
  1061. dev_err(&ctrl_info->pci_dev->dev,
  1062. "report physical LUNs failed\n");
  1063. rc = pqi_report_logical_luns(ctrl_info, (void **)logdev_list);
  1064. if (rc)
  1065. dev_err(&ctrl_info->pci_dev->dev,
  1066. "report logical LUNs failed\n");
  1067. /*
  1068. * Tack the controller itself onto the end of the logical device list
  1069. * by adding a list entry that is all zeros.
  1070. */
  1071. logdev_data = *logdev_list;
  1072. if (logdev_data) {
  1073. logdev_list_length =
  1074. get_unaligned_be32(&logdev_data->header.list_length);
  1075. } else {
  1076. memset(&report_lun_header, 0, sizeof(report_lun_header));
  1077. logdev_data =
  1078. (struct report_log_lun_list *)&report_lun_header;
  1079. logdev_list_length = 0;
  1080. }
  1081. logdev_data_length = sizeof(struct report_lun_header) +
  1082. logdev_list_length;
  1083. internal_logdev_list = kmalloc(logdev_data_length +
  1084. sizeof(struct report_log_lun), GFP_KERNEL);
  1085. if (!internal_logdev_list) {
  1086. kfree(*logdev_list);
  1087. *logdev_list = NULL;
  1088. return -ENOMEM;
  1089. }
  1090. memcpy(internal_logdev_list, logdev_data, logdev_data_length);
  1091. memset((u8 *)internal_logdev_list + logdev_data_length, 0,
  1092. sizeof(struct report_log_lun));
  1093. put_unaligned_be32(logdev_list_length +
  1094. sizeof(struct report_log_lun),
  1095. &internal_logdev_list->header.list_length);
  1096. kfree(*logdev_list);
  1097. *logdev_list = internal_logdev_list;
  1098. return 0;
  1099. }
  1100. static inline void pqi_set_bus_target_lun(struct pqi_scsi_dev *device,
  1101. int bus, int target, int lun)
  1102. {
  1103. device->bus = bus;
  1104. device->target = target;
  1105. device->lun = lun;
  1106. }
  1107. static void pqi_assign_bus_target_lun(struct pqi_scsi_dev *device)
  1108. {
  1109. u8 *scsi3addr;
  1110. u32 lunid;
  1111. int bus;
  1112. int target;
  1113. int lun;
  1114. scsi3addr = device->scsi3addr;
  1115. lunid = get_unaligned_le32(scsi3addr);
  1116. if (pqi_is_hba_lunid(scsi3addr)) {
  1117. /* The specified device is the controller. */
  1118. pqi_set_bus_target_lun(device, PQI_HBA_BUS, 0, lunid & 0x3fff);
  1119. device->target_lun_valid = true;
  1120. return;
  1121. }
  1122. if (pqi_is_logical_device(device)) {
  1123. if (device->is_external_raid_device) {
  1124. bus = PQI_EXTERNAL_RAID_VOLUME_BUS;
  1125. target = (lunid >> 16) & 0x3fff;
  1126. lun = lunid & 0xff;
  1127. } else {
  1128. bus = PQI_RAID_VOLUME_BUS;
  1129. target = 0;
  1130. lun = lunid & 0x3fff;
  1131. }
  1132. pqi_set_bus_target_lun(device, bus, target, lun);
  1133. device->target_lun_valid = true;
  1134. return;
  1135. }
  1136. /*
  1137. * Defer target and LUN assignment for non-controller physical devices
  1138. * because the SAS transport layer will make these assignments later.
  1139. */
  1140. pqi_set_bus_target_lun(device, PQI_PHYSICAL_DEVICE_BUS, 0, 0);
  1141. }
  1142. static void pqi_get_raid_level(struct pqi_ctrl_info *ctrl_info,
  1143. struct pqi_scsi_dev *device)
  1144. {
  1145. int rc;
  1146. u8 raid_level;
  1147. u8 *buffer;
  1148. raid_level = SA_RAID_UNKNOWN;
  1149. buffer = kmalloc(64, GFP_KERNEL);
  1150. if (buffer) {
  1151. rc = pqi_scsi_inquiry(ctrl_info, device->scsi3addr,
  1152. VPD_PAGE | CISS_VPD_LV_DEVICE_GEOMETRY, buffer, 64);
  1153. if (rc == 0) {
  1154. raid_level = buffer[8];
  1155. if (raid_level > SA_RAID_MAX)
  1156. raid_level = SA_RAID_UNKNOWN;
  1157. }
  1158. kfree(buffer);
  1159. }
  1160. device->raid_level = raid_level;
  1161. }
  1162. static int pqi_validate_raid_map(struct pqi_ctrl_info *ctrl_info,
  1163. struct pqi_scsi_dev *device, struct raid_map *raid_map)
  1164. {
  1165. char *err_msg;
  1166. u32 raid_map_size;
  1167. u32 r5or6_blocks_per_row;
  1168. raid_map_size = get_unaligned_le32(&raid_map->structure_size);
  1169. if (raid_map_size < offsetof(struct raid_map, disk_data)) {
  1170. err_msg = "RAID map too small";
  1171. goto bad_raid_map;
  1172. }
  1173. if (device->raid_level == SA_RAID_1) {
  1174. if (get_unaligned_le16(&raid_map->layout_map_count) != 2) {
  1175. err_msg = "invalid RAID-1 map";
  1176. goto bad_raid_map;
  1177. }
  1178. } else if (device->raid_level == SA_RAID_TRIPLE) {
  1179. if (get_unaligned_le16(&raid_map->layout_map_count) != 3) {
  1180. err_msg = "invalid RAID-1(Triple) map";
  1181. goto bad_raid_map;
  1182. }
  1183. } else if ((device->raid_level == SA_RAID_5 ||
  1184. device->raid_level == SA_RAID_6) &&
  1185. get_unaligned_le16(&raid_map->layout_map_count) > 1) {
  1186. /* RAID 50/60 */
  1187. r5or6_blocks_per_row =
  1188. get_unaligned_le16(&raid_map->strip_size) *
  1189. get_unaligned_le16(&raid_map->data_disks_per_row);
  1190. if (r5or6_blocks_per_row == 0) {
  1191. err_msg = "invalid RAID-5 or RAID-6 map";
  1192. goto bad_raid_map;
  1193. }
  1194. }
  1195. return 0;
  1196. bad_raid_map:
  1197. dev_warn(&ctrl_info->pci_dev->dev,
  1198. "logical device %08x%08x %s\n",
  1199. *((u32 *)&device->scsi3addr),
  1200. *((u32 *)&device->scsi3addr[4]), err_msg);
  1201. return -EINVAL;
  1202. }
  1203. static int pqi_get_raid_map(struct pqi_ctrl_info *ctrl_info,
  1204. struct pqi_scsi_dev *device)
  1205. {
  1206. int rc;
  1207. u32 raid_map_size;
  1208. struct raid_map *raid_map;
  1209. raid_map = kmalloc(sizeof(*raid_map), GFP_KERNEL);
  1210. if (!raid_map)
  1211. return -ENOMEM;
  1212. rc = pqi_send_scsi_raid_request(ctrl_info, CISS_GET_RAID_MAP,
  1213. device->scsi3addr, raid_map, sizeof(*raid_map), 0, NULL);
  1214. if (rc)
  1215. goto error;
  1216. raid_map_size = get_unaligned_le32(&raid_map->structure_size);
  1217. if (raid_map_size > sizeof(*raid_map)) {
  1218. kfree(raid_map);
  1219. raid_map = kmalloc(raid_map_size, GFP_KERNEL);
  1220. if (!raid_map)
  1221. return -ENOMEM;
  1222. rc = pqi_send_scsi_raid_request(ctrl_info, CISS_GET_RAID_MAP,
  1223. device->scsi3addr, raid_map, raid_map_size, 0, NULL);
  1224. if (rc)
  1225. goto error;
  1226. if (get_unaligned_le32(&raid_map->structure_size)
  1227. != raid_map_size) {
  1228. dev_warn(&ctrl_info->pci_dev->dev,
  1229. "requested %u bytes, received %u bytes\n",
  1230. raid_map_size,
  1231. get_unaligned_le32(&raid_map->structure_size));
  1232. rc = -EINVAL;
  1233. goto error;
  1234. }
  1235. }
  1236. rc = pqi_validate_raid_map(ctrl_info, device, raid_map);
  1237. if (rc)
  1238. goto error;
  1239. device->raid_io_stats = alloc_percpu(struct pqi_raid_io_stats);
  1240. if (!device->raid_io_stats) {
  1241. rc = -ENOMEM;
  1242. goto error;
  1243. }
  1244. device->raid_map = raid_map;
  1245. return 0;
  1246. error:
  1247. kfree(raid_map);
  1248. return rc;
  1249. }
  1250. static void pqi_set_max_transfer_encrypted(struct pqi_ctrl_info *ctrl_info,
  1251. struct pqi_scsi_dev *device)
  1252. {
  1253. if (!ctrl_info->lv_drive_type_mix_valid) {
  1254. device->max_transfer_encrypted = ~0;
  1255. return;
  1256. }
  1257. switch (LV_GET_DRIVE_TYPE_MIX(device->scsi3addr)) {
  1258. case LV_DRIVE_TYPE_MIX_SAS_HDD_ONLY:
  1259. case LV_DRIVE_TYPE_MIX_SATA_HDD_ONLY:
  1260. case LV_DRIVE_TYPE_MIX_SAS_OR_SATA_SSD_ONLY:
  1261. case LV_DRIVE_TYPE_MIX_SAS_SSD_ONLY:
  1262. case LV_DRIVE_TYPE_MIX_SATA_SSD_ONLY:
  1263. case LV_DRIVE_TYPE_MIX_SAS_ONLY:
  1264. case LV_DRIVE_TYPE_MIX_SATA_ONLY:
  1265. device->max_transfer_encrypted =
  1266. ctrl_info->max_transfer_encrypted_sas_sata;
  1267. break;
  1268. case LV_DRIVE_TYPE_MIX_NVME_ONLY:
  1269. device->max_transfer_encrypted =
  1270. ctrl_info->max_transfer_encrypted_nvme;
  1271. break;
  1272. case LV_DRIVE_TYPE_MIX_UNKNOWN:
  1273. case LV_DRIVE_TYPE_MIX_NO_RESTRICTION:
  1274. default:
  1275. device->max_transfer_encrypted =
  1276. min(ctrl_info->max_transfer_encrypted_sas_sata,
  1277. ctrl_info->max_transfer_encrypted_nvme);
  1278. break;
  1279. }
  1280. }
  1281. static void pqi_get_raid_bypass_status(struct pqi_ctrl_info *ctrl_info,
  1282. struct pqi_scsi_dev *device)
  1283. {
  1284. int rc;
  1285. u8 *buffer;
  1286. u8 bypass_status;
  1287. buffer = kmalloc(64, GFP_KERNEL);
  1288. if (!buffer)
  1289. return;
  1290. rc = pqi_scsi_inquiry(ctrl_info, device->scsi3addr,
  1291. VPD_PAGE | CISS_VPD_LV_BYPASS_STATUS, buffer, 64);
  1292. if (rc)
  1293. goto out;
  1294. #define RAID_BYPASS_STATUS 4
  1295. #define RAID_BYPASS_CONFIGURED 0x1
  1296. #define RAID_BYPASS_ENABLED 0x2
  1297. bypass_status = buffer[RAID_BYPASS_STATUS];
  1298. device->raid_bypass_configured =
  1299. (bypass_status & RAID_BYPASS_CONFIGURED) != 0;
  1300. if (device->raid_bypass_configured &&
  1301. (bypass_status & RAID_BYPASS_ENABLED) &&
  1302. pqi_get_raid_map(ctrl_info, device) == 0) {
  1303. device->raid_bypass_enabled = true;
  1304. if (get_unaligned_le16(&device->raid_map->flags) &
  1305. RAID_MAP_ENCRYPTION_ENABLED)
  1306. pqi_set_max_transfer_encrypted(ctrl_info, device);
  1307. }
  1308. out:
  1309. kfree(buffer);
  1310. }
  1311. /*
  1312. * Use vendor-specific VPD to determine online/offline status of a volume.
  1313. */
  1314. static void pqi_get_volume_status(struct pqi_ctrl_info *ctrl_info,
  1315. struct pqi_scsi_dev *device)
  1316. {
  1317. int rc;
  1318. size_t page_length;
  1319. u8 volume_status = CISS_LV_STATUS_UNAVAILABLE;
  1320. bool volume_offline = true;
  1321. u32 volume_flags;
  1322. struct ciss_vpd_logical_volume_status *vpd;
  1323. vpd = kmalloc(sizeof(*vpd), GFP_KERNEL);
  1324. if (!vpd)
  1325. goto no_buffer;
  1326. rc = pqi_scsi_inquiry(ctrl_info, device->scsi3addr,
  1327. VPD_PAGE | CISS_VPD_LV_STATUS, vpd, sizeof(*vpd));
  1328. if (rc)
  1329. goto out;
  1330. if (vpd->page_code != CISS_VPD_LV_STATUS)
  1331. goto out;
  1332. page_length = offsetof(struct ciss_vpd_logical_volume_status,
  1333. volume_status) + vpd->page_length;
  1334. if (page_length < sizeof(*vpd))
  1335. goto out;
  1336. volume_status = vpd->volume_status;
  1337. volume_flags = get_unaligned_be32(&vpd->flags);
  1338. volume_offline = (volume_flags & CISS_LV_FLAGS_NO_HOST_IO) != 0;
  1339. out:
  1340. kfree(vpd);
  1341. no_buffer:
  1342. device->volume_status = volume_status;
  1343. device->volume_offline = volume_offline;
  1344. }
  1345. #define PQI_DEVICE_NCQ_PRIO_SUPPORTED 0x01
  1346. #define PQI_DEVICE_PHY_MAP_SUPPORTED 0x10
  1347. #define PQI_DEVICE_ERASE_IN_PROGRESS 0x10
  1348. static int pqi_get_physical_device_info(struct pqi_ctrl_info *ctrl_info,
  1349. struct pqi_scsi_dev *device,
  1350. struct bmic_identify_physical_device *id_phys)
  1351. {
  1352. int rc;
  1353. memset(id_phys, 0, sizeof(*id_phys));
  1354. rc = pqi_identify_physical_device(ctrl_info, device,
  1355. id_phys, sizeof(*id_phys));
  1356. if (rc) {
  1357. device->queue_depth = PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH;
  1358. return rc;
  1359. }
  1360. scsi_sanitize_inquiry_string(&id_phys->model[0], 8);
  1361. scsi_sanitize_inquiry_string(&id_phys->model[8], 16);
  1362. memcpy(device->vendor, &id_phys->model[0], sizeof(device->vendor));
  1363. memcpy(device->model, &id_phys->model[8], sizeof(device->model));
  1364. device->box_index = id_phys->box_index;
  1365. device->phys_box_on_bus = id_phys->phys_box_on_bus;
  1366. device->phy_connected_dev_type = id_phys->phy_connected_dev_type[0];
  1367. device->queue_depth =
  1368. get_unaligned_le16(&id_phys->current_queue_depth_limit);
  1369. device->active_path_index = id_phys->active_path_number;
  1370. device->path_map = id_phys->redundant_path_present_map;
  1371. memcpy(&device->box,
  1372. &id_phys->alternate_paths_phys_box_on_port,
  1373. sizeof(device->box));
  1374. memcpy(&device->phys_connector,
  1375. &id_phys->alternate_paths_phys_connector,
  1376. sizeof(device->phys_connector));
  1377. device->bay = id_phys->phys_bay_in_box;
  1378. device->lun_count = id_phys->multi_lun_device_lun_count;
  1379. if ((id_phys->even_more_flags & PQI_DEVICE_PHY_MAP_SUPPORTED) &&
  1380. id_phys->phy_count)
  1381. device->phy_id =
  1382. id_phys->phy_to_phy_map[device->active_path_index];
  1383. else
  1384. device->phy_id = 0xFF;
  1385. device->ncq_prio_support =
  1386. ((get_unaligned_le32(&id_phys->misc_drive_flags) >> 16) &
  1387. PQI_DEVICE_NCQ_PRIO_SUPPORTED);
  1388. device->erase_in_progress = !!(get_unaligned_le16(&id_phys->extra_physical_drive_flags) & PQI_DEVICE_ERASE_IN_PROGRESS);
  1389. return 0;
  1390. }
  1391. static int pqi_get_logical_device_info(struct pqi_ctrl_info *ctrl_info,
  1392. struct pqi_scsi_dev *device)
  1393. {
  1394. int rc;
  1395. u8 *buffer;
  1396. buffer = kmalloc(64, GFP_KERNEL);
  1397. if (!buffer)
  1398. return -ENOMEM;
  1399. /* Send an inquiry to the device to see what it is. */
  1400. rc = pqi_scsi_inquiry(ctrl_info, device->scsi3addr, 0, buffer, 64);
  1401. if (rc)
  1402. goto out;
  1403. scsi_sanitize_inquiry_string(&buffer[8], 8);
  1404. scsi_sanitize_inquiry_string(&buffer[16], 16);
  1405. device->devtype = buffer[0] & 0x1f;
  1406. memcpy(device->vendor, &buffer[8], sizeof(device->vendor));
  1407. memcpy(device->model, &buffer[16], sizeof(device->model));
  1408. if (device->devtype == TYPE_DISK) {
  1409. if (device->is_external_raid_device) {
  1410. device->raid_level = SA_RAID_UNKNOWN;
  1411. device->volume_status = CISS_LV_OK;
  1412. device->volume_offline = false;
  1413. } else {
  1414. pqi_get_raid_level(ctrl_info, device);
  1415. pqi_get_raid_bypass_status(ctrl_info, device);
  1416. pqi_get_volume_status(ctrl_info, device);
  1417. }
  1418. }
  1419. out:
  1420. kfree(buffer);
  1421. return rc;
  1422. }
  1423. /*
  1424. * Prevent adding drive to OS for some corner cases such as a drive
  1425. * undergoing a sanitize (erase) operation. Some OSes will continue to poll
  1426. * the drive until the sanitize completes, which can take hours,
  1427. * resulting in long bootup delays. Commands such as TUR, READ_CAP
  1428. * are allowed, but READ/WRITE cause check condition. So the OS
  1429. * cannot check/read the partition table.
  1430. * Note: devices that have completed sanitize must be re-enabled
  1431. * using the management utility.
  1432. */
  1433. static inline bool pqi_keep_device_offline(struct pqi_scsi_dev *device)
  1434. {
  1435. return device->erase_in_progress;
  1436. }
  1437. static int pqi_get_device_info_phys_logical(struct pqi_ctrl_info *ctrl_info,
  1438. struct pqi_scsi_dev *device,
  1439. struct bmic_identify_physical_device *id_phys)
  1440. {
  1441. int rc;
  1442. if (device->is_expander_smp_device)
  1443. return 0;
  1444. if (pqi_is_logical_device(device))
  1445. rc = pqi_get_logical_device_info(ctrl_info, device);
  1446. else
  1447. rc = pqi_get_physical_device_info(ctrl_info, device, id_phys);
  1448. return rc;
  1449. }
  1450. static int pqi_get_device_info(struct pqi_ctrl_info *ctrl_info,
  1451. struct pqi_scsi_dev *device,
  1452. struct bmic_identify_physical_device *id_phys)
  1453. {
  1454. int rc;
  1455. rc = pqi_get_device_info_phys_logical(ctrl_info, device, id_phys);
  1456. if (rc == 0 && device->lun_count == 0)
  1457. device->lun_count = 1;
  1458. return rc;
  1459. }
  1460. static void pqi_show_volume_status(struct pqi_ctrl_info *ctrl_info,
  1461. struct pqi_scsi_dev *device)
  1462. {
  1463. char *status;
  1464. static const char unknown_state_str[] =
  1465. "Volume is in an unknown state (%u)";
  1466. char unknown_state_buffer[sizeof(unknown_state_str) + 10];
  1467. switch (device->volume_status) {
  1468. case CISS_LV_OK:
  1469. status = "Volume online";
  1470. break;
  1471. case CISS_LV_FAILED:
  1472. status = "Volume failed";
  1473. break;
  1474. case CISS_LV_NOT_CONFIGURED:
  1475. status = "Volume not configured";
  1476. break;
  1477. case CISS_LV_DEGRADED:
  1478. status = "Volume degraded";
  1479. break;
  1480. case CISS_LV_READY_FOR_RECOVERY:
  1481. status = "Volume ready for recovery operation";
  1482. break;
  1483. case CISS_LV_UNDERGOING_RECOVERY:
  1484. status = "Volume undergoing recovery";
  1485. break;
  1486. case CISS_LV_WRONG_PHYSICAL_DRIVE_REPLACED:
  1487. status = "Wrong physical drive was replaced";
  1488. break;
  1489. case CISS_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM:
  1490. status = "A physical drive not properly connected";
  1491. break;
  1492. case CISS_LV_HARDWARE_OVERHEATING:
  1493. status = "Hardware is overheating";
  1494. break;
  1495. case CISS_LV_HARDWARE_HAS_OVERHEATED:
  1496. status = "Hardware has overheated";
  1497. break;
  1498. case CISS_LV_UNDERGOING_EXPANSION:
  1499. status = "Volume undergoing expansion";
  1500. break;
  1501. case CISS_LV_NOT_AVAILABLE:
  1502. status = "Volume waiting for transforming volume";
  1503. break;
  1504. case CISS_LV_QUEUED_FOR_EXPANSION:
  1505. status = "Volume queued for expansion";
  1506. break;
  1507. case CISS_LV_DISABLED_SCSI_ID_CONFLICT:
  1508. status = "Volume disabled due to SCSI ID conflict";
  1509. break;
  1510. case CISS_LV_EJECTED:
  1511. status = "Volume has been ejected";
  1512. break;
  1513. case CISS_LV_UNDERGOING_ERASE:
  1514. status = "Volume undergoing background erase";
  1515. break;
  1516. case CISS_LV_READY_FOR_PREDICTIVE_SPARE_REBUILD:
  1517. status = "Volume ready for predictive spare rebuild";
  1518. break;
  1519. case CISS_LV_UNDERGOING_RPI:
  1520. status = "Volume undergoing rapid parity initialization";
  1521. break;
  1522. case CISS_LV_PENDING_RPI:
  1523. status = "Volume queued for rapid parity initialization";
  1524. break;
  1525. case CISS_LV_ENCRYPTED_NO_KEY:
  1526. status = "Encrypted volume inaccessible - key not present";
  1527. break;
  1528. case CISS_LV_UNDERGOING_ENCRYPTION:
  1529. status = "Volume undergoing encryption process";
  1530. break;
  1531. case CISS_LV_UNDERGOING_ENCRYPTION_REKEYING:
  1532. status = "Volume undergoing encryption re-keying process";
  1533. break;
  1534. case CISS_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
  1535. status = "Volume encrypted but encryption is disabled";
  1536. break;
  1537. case CISS_LV_PENDING_ENCRYPTION:
  1538. status = "Volume pending migration to encrypted state";
  1539. break;
  1540. case CISS_LV_PENDING_ENCRYPTION_REKEYING:
  1541. status = "Volume pending encryption rekeying";
  1542. break;
  1543. case CISS_LV_NOT_SUPPORTED:
  1544. status = "Volume not supported on this controller";
  1545. break;
  1546. case CISS_LV_STATUS_UNAVAILABLE:
  1547. status = "Volume status not available";
  1548. break;
  1549. default:
  1550. snprintf(unknown_state_buffer, sizeof(unknown_state_buffer),
  1551. unknown_state_str, device->volume_status);
  1552. status = unknown_state_buffer;
  1553. break;
  1554. }
  1555. dev_info(&ctrl_info->pci_dev->dev,
  1556. "scsi %d:%d:%d:%d %s\n",
  1557. ctrl_info->scsi_host->host_no,
  1558. device->bus, device->target, device->lun, status);
  1559. }
  1560. static void pqi_rescan_worker(struct work_struct *work)
  1561. {
  1562. struct pqi_ctrl_info *ctrl_info;
  1563. ctrl_info = container_of(to_delayed_work(work), struct pqi_ctrl_info,
  1564. rescan_work);
  1565. pqi_scan_scsi_devices(ctrl_info);
  1566. }
  1567. static int pqi_add_device(struct pqi_ctrl_info *ctrl_info,
  1568. struct pqi_scsi_dev *device)
  1569. {
  1570. int rc;
  1571. if (pqi_is_logical_device(device))
  1572. rc = scsi_add_device(ctrl_info->scsi_host, device->bus,
  1573. device->target, device->lun);
  1574. else
  1575. rc = pqi_add_sas_device(ctrl_info->sas_host, device);
  1576. return rc;
  1577. }
  1578. #define PQI_REMOVE_DEVICE_PENDING_IO_TIMEOUT_MSECS (20 * 1000)
  1579. static inline void pqi_remove_device(struct pqi_ctrl_info *ctrl_info, struct pqi_scsi_dev *device)
  1580. {
  1581. int rc;
  1582. int lun;
  1583. for (lun = 0; lun < device->lun_count; lun++) {
  1584. rc = pqi_device_wait_for_pending_io(ctrl_info, device, lun,
  1585. PQI_REMOVE_DEVICE_PENDING_IO_TIMEOUT_MSECS);
  1586. if (rc)
  1587. dev_err(&ctrl_info->pci_dev->dev,
  1588. "scsi %d:%d:%d:%d removing device with %d outstanding command(s)\n",
  1589. ctrl_info->scsi_host->host_no, device->bus,
  1590. device->target, lun,
  1591. atomic_read(&device->scsi_cmds_outstanding[lun]));
  1592. }
  1593. if (pqi_is_logical_device(device))
  1594. scsi_remove_device(device->sdev);
  1595. else
  1596. pqi_remove_sas_device(device);
  1597. pqi_device_remove_start(device);
  1598. }
  1599. /* Assumes the SCSI device list lock is held. */
  1600. static struct pqi_scsi_dev *pqi_find_scsi_dev(struct pqi_ctrl_info *ctrl_info,
  1601. int bus, int target, int lun)
  1602. {
  1603. struct pqi_scsi_dev *device;
  1604. list_for_each_entry(device, &ctrl_info->scsi_device_list, scsi_device_list_entry)
  1605. if (device->bus == bus && device->target == target && device->lun == lun)
  1606. return device;
  1607. return NULL;
  1608. }
  1609. static inline bool pqi_device_equal(struct pqi_scsi_dev *dev1, struct pqi_scsi_dev *dev2)
  1610. {
  1611. if (dev1->is_physical_device != dev2->is_physical_device)
  1612. return false;
  1613. if (dev1->is_physical_device)
  1614. return memcmp(dev1->wwid, dev2->wwid, sizeof(dev1->wwid)) == 0;
  1615. return memcmp(dev1->volume_id, dev2->volume_id, sizeof(dev1->volume_id)) == 0;
  1616. }
  1617. enum pqi_find_result {
  1618. DEVICE_NOT_FOUND,
  1619. DEVICE_CHANGED,
  1620. DEVICE_SAME,
  1621. };
  1622. static enum pqi_find_result pqi_scsi_find_entry(struct pqi_ctrl_info *ctrl_info,
  1623. struct pqi_scsi_dev *device_to_find, struct pqi_scsi_dev **matching_device)
  1624. {
  1625. struct pqi_scsi_dev *device;
  1626. list_for_each_entry(device, &ctrl_info->scsi_device_list, scsi_device_list_entry) {
  1627. if (pqi_scsi3addr_equal(device_to_find->scsi3addr, device->scsi3addr)) {
  1628. *matching_device = device;
  1629. if (pqi_device_equal(device_to_find, device)) {
  1630. if (device_to_find->volume_offline)
  1631. return DEVICE_CHANGED;
  1632. return DEVICE_SAME;
  1633. }
  1634. return DEVICE_CHANGED;
  1635. }
  1636. }
  1637. return DEVICE_NOT_FOUND;
  1638. }
  1639. static inline const char *pqi_device_type(struct pqi_scsi_dev *device)
  1640. {
  1641. if (device->is_expander_smp_device)
  1642. return "Enclosure SMP ";
  1643. return scsi_device_type(device->devtype);
  1644. }
  1645. #define PQI_DEV_INFO_BUFFER_LENGTH 128
  1646. static void pqi_dev_info(struct pqi_ctrl_info *ctrl_info,
  1647. char *action, struct pqi_scsi_dev *device)
  1648. {
  1649. ssize_t count;
  1650. char buffer[PQI_DEV_INFO_BUFFER_LENGTH];
  1651. count = scnprintf(buffer, PQI_DEV_INFO_BUFFER_LENGTH,
  1652. "%d:%d:", ctrl_info->scsi_host->host_no, device->bus);
  1653. if (device->target_lun_valid)
  1654. count += scnprintf(buffer + count,
  1655. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1656. "%d:%d",
  1657. device->target,
  1658. device->lun);
  1659. else
  1660. count += scnprintf(buffer + count,
  1661. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1662. "-:-");
  1663. if (pqi_is_logical_device(device))
  1664. count += scnprintf(buffer + count,
  1665. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1666. " %08x%08x",
  1667. *((u32 *)&device->scsi3addr),
  1668. *((u32 *)&device->scsi3addr[4]));
  1669. else
  1670. count += scnprintf(buffer + count,
  1671. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1672. " %016llx%016llx",
  1673. get_unaligned_be64(&device->wwid[0]),
  1674. get_unaligned_be64(&device->wwid[8]));
  1675. count += scnprintf(buffer + count, PQI_DEV_INFO_BUFFER_LENGTH - count,
  1676. " %s %.8s %.16s ",
  1677. pqi_device_type(device),
  1678. device->vendor,
  1679. device->model);
  1680. if (pqi_is_logical_device(device)) {
  1681. if (device->devtype == TYPE_DISK)
  1682. count += scnprintf(buffer + count,
  1683. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1684. "SSDSmartPathCap%c En%c %-12s",
  1685. device->raid_bypass_configured ? '+' : '-',
  1686. device->raid_bypass_enabled ? '+' : '-',
  1687. pqi_raid_level_to_string(device->raid_level));
  1688. } else {
  1689. count += scnprintf(buffer + count,
  1690. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1691. "AIO%c", device->aio_enabled ? '+' : '-');
  1692. if (device->devtype == TYPE_DISK ||
  1693. device->devtype == TYPE_ZBC)
  1694. count += scnprintf(buffer + count,
  1695. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1696. " qd=%-6d", device->queue_depth);
  1697. }
  1698. dev_info(&ctrl_info->pci_dev->dev, "%s %s\n", action, buffer);
  1699. }
  1700. static bool pqi_raid_maps_equal(struct raid_map *raid_map1, struct raid_map *raid_map2)
  1701. {
  1702. u32 raid_map1_size;
  1703. u32 raid_map2_size;
  1704. if (raid_map1 == NULL || raid_map2 == NULL)
  1705. return raid_map1 == raid_map2;
  1706. raid_map1_size = get_unaligned_le32(&raid_map1->structure_size);
  1707. raid_map2_size = get_unaligned_le32(&raid_map2->structure_size);
  1708. if (raid_map1_size != raid_map2_size)
  1709. return false;
  1710. return memcmp(raid_map1, raid_map2, raid_map1_size) == 0;
  1711. }
  1712. /* Assumes the SCSI device list lock is held. */
  1713. static void pqi_scsi_update_device(struct pqi_ctrl_info *ctrl_info,
  1714. struct pqi_scsi_dev *existing_device, struct pqi_scsi_dev *new_device)
  1715. {
  1716. existing_device->device_type = new_device->device_type;
  1717. existing_device->bus = new_device->bus;
  1718. if (new_device->target_lun_valid) {
  1719. existing_device->target = new_device->target;
  1720. existing_device->lun = new_device->lun;
  1721. existing_device->target_lun_valid = true;
  1722. }
  1723. /* By definition, the scsi3addr and wwid fields are already the same. */
  1724. existing_device->is_physical_device = new_device->is_physical_device;
  1725. memcpy(existing_device->vendor, new_device->vendor, sizeof(existing_device->vendor));
  1726. memcpy(existing_device->model, new_device->model, sizeof(existing_device->model));
  1727. existing_device->sas_address = new_device->sas_address;
  1728. existing_device->queue_depth = new_device->queue_depth;
  1729. existing_device->device_offline = false;
  1730. existing_device->lun_count = new_device->lun_count;
  1731. if (pqi_is_logical_device(existing_device)) {
  1732. existing_device->is_external_raid_device = new_device->is_external_raid_device;
  1733. if (existing_device->devtype == TYPE_DISK) {
  1734. existing_device->raid_level = new_device->raid_level;
  1735. existing_device->volume_status = new_device->volume_status;
  1736. memset(existing_device->next_bypass_group, 0, sizeof(existing_device->next_bypass_group));
  1737. if (!pqi_raid_maps_equal(existing_device->raid_map, new_device->raid_map)) {
  1738. kfree(existing_device->raid_map);
  1739. existing_device->raid_map = new_device->raid_map;
  1740. /* To prevent this from being freed later. */
  1741. new_device->raid_map = NULL;
  1742. }
  1743. if (new_device->raid_bypass_enabled && existing_device->raid_io_stats == NULL) {
  1744. existing_device->raid_io_stats = new_device->raid_io_stats;
  1745. new_device->raid_io_stats = NULL;
  1746. }
  1747. existing_device->raid_bypass_configured = new_device->raid_bypass_configured;
  1748. existing_device->raid_bypass_enabled = new_device->raid_bypass_enabled;
  1749. }
  1750. } else {
  1751. existing_device->aio_enabled = new_device->aio_enabled;
  1752. existing_device->aio_handle = new_device->aio_handle;
  1753. existing_device->is_expander_smp_device = new_device->is_expander_smp_device;
  1754. existing_device->active_path_index = new_device->active_path_index;
  1755. existing_device->phy_id = new_device->phy_id;
  1756. existing_device->path_map = new_device->path_map;
  1757. existing_device->bay = new_device->bay;
  1758. existing_device->box_index = new_device->box_index;
  1759. existing_device->phys_box_on_bus = new_device->phys_box_on_bus;
  1760. existing_device->phy_connected_dev_type = new_device->phy_connected_dev_type;
  1761. memcpy(existing_device->box, new_device->box, sizeof(existing_device->box));
  1762. memcpy(existing_device->phys_connector, new_device->phys_connector, sizeof(existing_device->phys_connector));
  1763. }
  1764. }
  1765. static inline void pqi_free_device(struct pqi_scsi_dev *device)
  1766. {
  1767. if (device) {
  1768. free_percpu(device->raid_io_stats);
  1769. kfree(device->raid_map);
  1770. kfree(device);
  1771. }
  1772. }
  1773. /*
  1774. * Called when exposing a new device to the OS fails in order to re-adjust
  1775. * our internal SCSI device list to match the SCSI ML's view.
  1776. */
  1777. static inline void pqi_fixup_botched_add(struct pqi_ctrl_info *ctrl_info,
  1778. struct pqi_scsi_dev *device)
  1779. {
  1780. unsigned long flags;
  1781. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  1782. list_del(&device->scsi_device_list_entry);
  1783. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  1784. /* Allow the device structure to be freed later. */
  1785. device->keep_device = false;
  1786. }
  1787. static inline bool pqi_is_device_added(struct pqi_scsi_dev *device)
  1788. {
  1789. if (device->is_expander_smp_device)
  1790. return device->sas_port != NULL;
  1791. return device->sdev != NULL;
  1792. }
  1793. static inline void pqi_init_device_tmf_work(struct pqi_scsi_dev *device)
  1794. {
  1795. unsigned int lun;
  1796. struct pqi_tmf_work *tmf_work;
  1797. for (lun = 0, tmf_work = device->tmf_work; lun < PQI_MAX_LUNS_PER_DEVICE; lun++, tmf_work++)
  1798. INIT_WORK(&tmf_work->work_struct, pqi_tmf_worker);
  1799. }
  1800. static inline bool pqi_volume_rescan_needed(struct pqi_scsi_dev *device)
  1801. {
  1802. if (pqi_device_in_remove(device))
  1803. return false;
  1804. if (device->sdev == NULL)
  1805. return false;
  1806. if (!scsi_device_online(device->sdev))
  1807. return false;
  1808. return device->rescan;
  1809. }
  1810. static void pqi_update_device_list(struct pqi_ctrl_info *ctrl_info,
  1811. struct pqi_scsi_dev *new_device_list[], unsigned int num_new_devices)
  1812. {
  1813. int rc;
  1814. unsigned int i;
  1815. unsigned long flags;
  1816. enum pqi_find_result find_result;
  1817. struct pqi_scsi_dev *device;
  1818. struct pqi_scsi_dev *next;
  1819. struct pqi_scsi_dev *matching_device;
  1820. LIST_HEAD(add_list);
  1821. LIST_HEAD(delete_list);
  1822. /*
  1823. * The idea here is to do as little work as possible while holding the
  1824. * spinlock. That's why we go to great pains to defer anything other
  1825. * than updating the internal device list until after we release the
  1826. * spinlock.
  1827. */
  1828. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  1829. /* Assume that all devices in the existing list have gone away. */
  1830. list_for_each_entry(device, &ctrl_info->scsi_device_list, scsi_device_list_entry)
  1831. device->device_gone = true;
  1832. for (i = 0; i < num_new_devices; i++) {
  1833. device = new_device_list[i];
  1834. find_result = pqi_scsi_find_entry(ctrl_info, device,
  1835. &matching_device);
  1836. switch (find_result) {
  1837. case DEVICE_SAME:
  1838. /*
  1839. * The newly found device is already in the existing
  1840. * device list.
  1841. */
  1842. device->new_device = false;
  1843. matching_device->device_gone = false;
  1844. pqi_scsi_update_device(ctrl_info, matching_device, device);
  1845. break;
  1846. case DEVICE_NOT_FOUND:
  1847. /*
  1848. * The newly found device is NOT in the existing device
  1849. * list.
  1850. */
  1851. device->new_device = true;
  1852. break;
  1853. case DEVICE_CHANGED:
  1854. /*
  1855. * The original device has gone away and we need to add
  1856. * the new device.
  1857. */
  1858. device->new_device = true;
  1859. break;
  1860. }
  1861. }
  1862. /* Process all devices that have gone away. */
  1863. list_for_each_entry_safe(device, next, &ctrl_info->scsi_device_list,
  1864. scsi_device_list_entry) {
  1865. if (device->device_gone) {
  1866. list_del(&device->scsi_device_list_entry);
  1867. list_add_tail(&device->delete_list_entry, &delete_list);
  1868. }
  1869. }
  1870. /* Process all new devices. */
  1871. for (i = 0; i < num_new_devices; i++) {
  1872. device = new_device_list[i];
  1873. if (!device->new_device)
  1874. continue;
  1875. if (device->volume_offline)
  1876. continue;
  1877. list_add_tail(&device->scsi_device_list_entry,
  1878. &ctrl_info->scsi_device_list);
  1879. list_add_tail(&device->add_list_entry, &add_list);
  1880. /* To prevent this device structure from being freed later. */
  1881. device->keep_device = true;
  1882. pqi_init_device_tmf_work(device);
  1883. }
  1884. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  1885. /*
  1886. * If OFA is in progress and there are devices that need to be deleted,
  1887. * allow any pending reset operations to continue and unblock any SCSI
  1888. * requests before removal.
  1889. */
  1890. if (pqi_ofa_in_progress(ctrl_info)) {
  1891. list_for_each_entry_safe(device, next, &delete_list, delete_list_entry)
  1892. if (pqi_is_device_added(device))
  1893. pqi_device_remove_start(device);
  1894. pqi_ctrl_unblock_device_reset(ctrl_info);
  1895. pqi_scsi_unblock_requests(ctrl_info);
  1896. }
  1897. /* Remove all devices that have gone away. */
  1898. list_for_each_entry_safe(device, next, &delete_list, delete_list_entry) {
  1899. if (device->volume_offline) {
  1900. pqi_dev_info(ctrl_info, "offline", device);
  1901. pqi_show_volume_status(ctrl_info, device);
  1902. } else {
  1903. pqi_dev_info(ctrl_info, "removed", device);
  1904. }
  1905. if (pqi_is_device_added(device))
  1906. pqi_remove_device(ctrl_info, device);
  1907. list_del(&device->delete_list_entry);
  1908. pqi_free_device(device);
  1909. }
  1910. /*
  1911. * Notify the SML of any existing device changes such as;
  1912. * queue depth, device size.
  1913. */
  1914. list_for_each_entry(device, &ctrl_info->scsi_device_list, scsi_device_list_entry) {
  1915. /*
  1916. * Check for queue depth change.
  1917. */
  1918. if (device->sdev && device->queue_depth != device->advertised_queue_depth) {
  1919. device->advertised_queue_depth = device->queue_depth;
  1920. scsi_change_queue_depth(device->sdev, device->advertised_queue_depth);
  1921. }
  1922. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  1923. /*
  1924. * Check for changes in the device, such as size.
  1925. */
  1926. if (pqi_volume_rescan_needed(device)) {
  1927. device->rescan = false;
  1928. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  1929. scsi_rescan_device(device->sdev);
  1930. } else {
  1931. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  1932. }
  1933. }
  1934. /* Expose any new devices. */
  1935. list_for_each_entry_safe(device, next, &add_list, add_list_entry) {
  1936. if (!pqi_is_device_added(device)) {
  1937. rc = pqi_add_device(ctrl_info, device);
  1938. if (rc == 0) {
  1939. pqi_dev_info(ctrl_info, "added", device);
  1940. } else {
  1941. dev_warn(&ctrl_info->pci_dev->dev,
  1942. "scsi %d:%d:%d:%d addition failed, device not added\n",
  1943. ctrl_info->scsi_host->host_no,
  1944. device->bus, device->target,
  1945. device->lun);
  1946. pqi_fixup_botched_add(ctrl_info, device);
  1947. }
  1948. }
  1949. }
  1950. }
  1951. static inline bool pqi_is_supported_device(struct pqi_scsi_dev *device)
  1952. {
  1953. /*
  1954. * Only support the HBA controller itself as a RAID
  1955. * controller. If it's a RAID controller other than
  1956. * the HBA itself (an external RAID controller, for
  1957. * example), we don't support it.
  1958. */
  1959. if (device->device_type == SA_DEVICE_TYPE_CONTROLLER &&
  1960. !pqi_is_hba_lunid(device->scsi3addr))
  1961. return false;
  1962. return true;
  1963. }
  1964. static inline bool pqi_skip_device(u8 *scsi3addr)
  1965. {
  1966. /* Ignore all masked devices. */
  1967. if (MASKED_DEVICE(scsi3addr))
  1968. return true;
  1969. return false;
  1970. }
  1971. static inline void pqi_mask_device(u8 *scsi3addr)
  1972. {
  1973. scsi3addr[3] |= 0xc0;
  1974. }
  1975. static inline bool pqi_expose_device(struct pqi_scsi_dev *device)
  1976. {
  1977. return !device->is_physical_device || !pqi_skip_device(device->scsi3addr);
  1978. }
  1979. static int pqi_update_scsi_devices(struct pqi_ctrl_info *ctrl_info)
  1980. {
  1981. int i;
  1982. int rc;
  1983. LIST_HEAD(new_device_list_head);
  1984. struct report_phys_lun_16byte_wwid_list *physdev_list = NULL;
  1985. struct report_log_lun_list *logdev_list = NULL;
  1986. struct report_phys_lun_16byte_wwid *phys_lun;
  1987. struct report_log_lun *log_lun;
  1988. struct bmic_identify_physical_device *id_phys = NULL;
  1989. u32 num_physicals;
  1990. u32 num_logicals;
  1991. struct pqi_scsi_dev **new_device_list = NULL;
  1992. struct pqi_scsi_dev *device;
  1993. struct pqi_scsi_dev *next;
  1994. unsigned int num_new_devices;
  1995. unsigned int num_valid_devices;
  1996. bool is_physical_device;
  1997. u8 *scsi3addr;
  1998. unsigned int physical_index;
  1999. unsigned int logical_index;
  2000. static char *out_of_memory_msg =
  2001. "failed to allocate memory, device discovery stopped";
  2002. rc = pqi_get_device_lists(ctrl_info, &physdev_list, &logdev_list);
  2003. if (rc)
  2004. goto out;
  2005. if (physdev_list)
  2006. num_physicals =
  2007. get_unaligned_be32(&physdev_list->header.list_length)
  2008. / sizeof(physdev_list->lun_entries[0]);
  2009. else
  2010. num_physicals = 0;
  2011. if (logdev_list)
  2012. num_logicals =
  2013. get_unaligned_be32(&logdev_list->header.list_length)
  2014. / sizeof(logdev_list->lun_entries[0]);
  2015. else
  2016. num_logicals = 0;
  2017. if (num_physicals) {
  2018. /*
  2019. * We need this buffer for calls to pqi_get_physical_disk_info()
  2020. * below. We allocate it here instead of inside
  2021. * pqi_get_physical_disk_info() because it's a fairly large
  2022. * buffer.
  2023. */
  2024. id_phys = kmalloc(sizeof(*id_phys), GFP_KERNEL);
  2025. if (!id_phys) {
  2026. dev_warn(&ctrl_info->pci_dev->dev, "%s\n",
  2027. out_of_memory_msg);
  2028. rc = -ENOMEM;
  2029. goto out;
  2030. }
  2031. if (pqi_hide_vsep) {
  2032. for (i = num_physicals - 1; i >= 0; i--) {
  2033. phys_lun = &physdev_list->lun_entries[i];
  2034. if (CISS_GET_DRIVE_NUMBER(phys_lun->lunid) == PQI_VSEP_CISS_BTL) {
  2035. pqi_mask_device(phys_lun->lunid);
  2036. break;
  2037. }
  2038. }
  2039. }
  2040. }
  2041. if (num_logicals &&
  2042. (logdev_list->header.flags & CISS_REPORT_LOG_FLAG_DRIVE_TYPE_MIX))
  2043. ctrl_info->lv_drive_type_mix_valid = true;
  2044. num_new_devices = num_physicals + num_logicals;
  2045. new_device_list = kmalloc_array(num_new_devices,
  2046. sizeof(*new_device_list),
  2047. GFP_KERNEL);
  2048. if (!new_device_list) {
  2049. dev_warn(&ctrl_info->pci_dev->dev, "%s\n", out_of_memory_msg);
  2050. rc = -ENOMEM;
  2051. goto out;
  2052. }
  2053. for (i = 0; i < num_new_devices; i++) {
  2054. device = kzalloc(sizeof(*device), GFP_KERNEL);
  2055. if (!device) {
  2056. dev_warn(&ctrl_info->pci_dev->dev, "%s\n",
  2057. out_of_memory_msg);
  2058. rc = -ENOMEM;
  2059. goto out;
  2060. }
  2061. list_add_tail(&device->new_device_list_entry,
  2062. &new_device_list_head);
  2063. }
  2064. device = NULL;
  2065. num_valid_devices = 0;
  2066. physical_index = 0;
  2067. logical_index = 0;
  2068. for (i = 0; i < num_new_devices; i++) {
  2069. if ((!pqi_expose_ld_first && i < num_physicals) ||
  2070. (pqi_expose_ld_first && i >= num_logicals)) {
  2071. is_physical_device = true;
  2072. phys_lun = &physdev_list->lun_entries[physical_index++];
  2073. log_lun = NULL;
  2074. scsi3addr = phys_lun->lunid;
  2075. } else {
  2076. is_physical_device = false;
  2077. phys_lun = NULL;
  2078. log_lun = &logdev_list->lun_entries[logical_index++];
  2079. scsi3addr = log_lun->lunid;
  2080. }
  2081. if (is_physical_device && pqi_skip_device(scsi3addr))
  2082. continue;
  2083. if (device)
  2084. device = list_next_entry(device, new_device_list_entry);
  2085. else
  2086. device = list_first_entry(&new_device_list_head,
  2087. struct pqi_scsi_dev, new_device_list_entry);
  2088. memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
  2089. device->is_physical_device = is_physical_device;
  2090. if (is_physical_device) {
  2091. device->device_type = phys_lun->device_type;
  2092. if (device->device_type == SA_DEVICE_TYPE_EXPANDER_SMP)
  2093. device->is_expander_smp_device = true;
  2094. } else {
  2095. device->is_external_raid_device =
  2096. pqi_is_external_raid_addr(scsi3addr);
  2097. }
  2098. if (!pqi_is_supported_device(device))
  2099. continue;
  2100. /* Gather information about the device. */
  2101. rc = pqi_get_device_info(ctrl_info, device, id_phys);
  2102. if (rc == -ENOMEM) {
  2103. dev_warn(&ctrl_info->pci_dev->dev, "%s\n",
  2104. out_of_memory_msg);
  2105. goto out;
  2106. }
  2107. if (rc) {
  2108. if (device->is_physical_device)
  2109. dev_warn(&ctrl_info->pci_dev->dev,
  2110. "obtaining device info failed, skipping physical device %016llx%016llx\n",
  2111. get_unaligned_be64(&phys_lun->wwid[0]),
  2112. get_unaligned_be64(&phys_lun->wwid[8]));
  2113. else
  2114. dev_warn(&ctrl_info->pci_dev->dev,
  2115. "obtaining device info failed, skipping logical device %08x%08x\n",
  2116. *((u32 *)&device->scsi3addr),
  2117. *((u32 *)&device->scsi3addr[4]));
  2118. rc = 0;
  2119. continue;
  2120. }
  2121. /* Do not present disks that the OS cannot fully probe. */
  2122. if (pqi_keep_device_offline(device))
  2123. continue;
  2124. pqi_assign_bus_target_lun(device);
  2125. if (device->is_physical_device) {
  2126. memcpy(device->wwid, phys_lun->wwid, sizeof(device->wwid));
  2127. if ((phys_lun->device_flags &
  2128. CISS_REPORT_PHYS_DEV_FLAG_AIO_ENABLED) &&
  2129. phys_lun->aio_handle) {
  2130. device->aio_enabled = true;
  2131. device->aio_handle =
  2132. phys_lun->aio_handle;
  2133. }
  2134. } else {
  2135. memcpy(device->volume_id, log_lun->volume_id,
  2136. sizeof(device->volume_id));
  2137. }
  2138. device->sas_address = get_unaligned_be64(&device->wwid[0]);
  2139. new_device_list[num_valid_devices++] = device;
  2140. }
  2141. pqi_update_device_list(ctrl_info, new_device_list, num_valid_devices);
  2142. out:
  2143. list_for_each_entry_safe(device, next, &new_device_list_head,
  2144. new_device_list_entry) {
  2145. if (device->keep_device)
  2146. continue;
  2147. list_del(&device->new_device_list_entry);
  2148. pqi_free_device(device);
  2149. }
  2150. kfree(new_device_list);
  2151. kfree(physdev_list);
  2152. kfree(logdev_list);
  2153. kfree(id_phys);
  2154. return rc;
  2155. }
  2156. static int pqi_scan_scsi_devices(struct pqi_ctrl_info *ctrl_info)
  2157. {
  2158. int rc;
  2159. int mutex_acquired;
  2160. if (pqi_ctrl_offline(ctrl_info))
  2161. return -ENXIO;
  2162. mutex_acquired = mutex_trylock(&ctrl_info->scan_mutex);
  2163. if (!mutex_acquired) {
  2164. if (pqi_ctrl_scan_blocked(ctrl_info))
  2165. return -EBUSY;
  2166. pqi_schedule_rescan_worker_delayed(ctrl_info);
  2167. return -EINPROGRESS;
  2168. }
  2169. rc = pqi_update_scsi_devices(ctrl_info);
  2170. if (rc && !pqi_ctrl_scan_blocked(ctrl_info))
  2171. pqi_schedule_rescan_worker_delayed(ctrl_info);
  2172. mutex_unlock(&ctrl_info->scan_mutex);
  2173. return rc;
  2174. }
  2175. static void pqi_scan_start(struct Scsi_Host *shost)
  2176. {
  2177. struct pqi_ctrl_info *ctrl_info;
  2178. ctrl_info = shost_to_hba(shost);
  2179. pqi_scan_scsi_devices(ctrl_info);
  2180. }
  2181. /* Returns TRUE if scan is finished. */
  2182. static int pqi_scan_finished(struct Scsi_Host *shost,
  2183. unsigned long elapsed_time)
  2184. {
  2185. struct pqi_ctrl_info *ctrl_info;
  2186. ctrl_info = shost_priv(shost);
  2187. return !mutex_is_locked(&ctrl_info->scan_mutex);
  2188. }
  2189. static inline void pqi_set_encryption_info(struct pqi_encryption_info *encryption_info,
  2190. struct raid_map *raid_map, u64 first_block)
  2191. {
  2192. u32 volume_blk_size;
  2193. /*
  2194. * Set the encryption tweak values based on logical block address.
  2195. * If the block size is 512, the tweak value is equal to the LBA.
  2196. * For other block sizes, tweak value is (LBA * block size) / 512.
  2197. */
  2198. volume_blk_size = get_unaligned_le32(&raid_map->volume_blk_size);
  2199. if (volume_blk_size != 512)
  2200. first_block = (first_block * volume_blk_size) / 512;
  2201. encryption_info->data_encryption_key_index =
  2202. get_unaligned_le16(&raid_map->data_encryption_key_index);
  2203. encryption_info->encrypt_tweak_lower = lower_32_bits(first_block);
  2204. encryption_info->encrypt_tweak_upper = upper_32_bits(first_block);
  2205. }
  2206. /*
  2207. * Attempt to perform RAID bypass mapping for a logical volume I/O.
  2208. */
  2209. static bool pqi_aio_raid_level_supported(struct pqi_ctrl_info *ctrl_info,
  2210. struct pqi_scsi_dev_raid_map_data *rmd)
  2211. {
  2212. bool is_supported = true;
  2213. switch (rmd->raid_level) {
  2214. case SA_RAID_0:
  2215. break;
  2216. case SA_RAID_1:
  2217. if (rmd->is_write && (!ctrl_info->enable_r1_writes ||
  2218. rmd->data_length > ctrl_info->max_write_raid_1_10_2drive))
  2219. is_supported = false;
  2220. break;
  2221. case SA_RAID_TRIPLE:
  2222. if (rmd->is_write && (!ctrl_info->enable_r1_writes ||
  2223. rmd->data_length > ctrl_info->max_write_raid_1_10_3drive))
  2224. is_supported = false;
  2225. break;
  2226. case SA_RAID_5:
  2227. if (rmd->is_write && (!ctrl_info->enable_r5_writes ||
  2228. rmd->data_length > ctrl_info->max_write_raid_5_6))
  2229. is_supported = false;
  2230. break;
  2231. case SA_RAID_6:
  2232. if (rmd->is_write && (!ctrl_info->enable_r6_writes ||
  2233. rmd->data_length > ctrl_info->max_write_raid_5_6))
  2234. is_supported = false;
  2235. break;
  2236. default:
  2237. is_supported = false;
  2238. break;
  2239. }
  2240. return is_supported;
  2241. }
  2242. #define PQI_RAID_BYPASS_INELIGIBLE 1
  2243. static int pqi_get_aio_lba_and_block_count(struct scsi_cmnd *scmd,
  2244. struct pqi_scsi_dev_raid_map_data *rmd)
  2245. {
  2246. /* Check for valid opcode, get LBA and block count. */
  2247. switch (scmd->cmnd[0]) {
  2248. case WRITE_6:
  2249. rmd->is_write = true;
  2250. fallthrough;
  2251. case READ_6:
  2252. rmd->first_block = (u64)(((scmd->cmnd[1] & 0x1f) << 16) |
  2253. (scmd->cmnd[2] << 8) | scmd->cmnd[3]);
  2254. rmd->block_cnt = (u32)scmd->cmnd[4];
  2255. if (rmd->block_cnt == 0)
  2256. rmd->block_cnt = 256;
  2257. break;
  2258. case WRITE_10:
  2259. rmd->is_write = true;
  2260. fallthrough;
  2261. case READ_10:
  2262. rmd->first_block = (u64)get_unaligned_be32(&scmd->cmnd[2]);
  2263. rmd->block_cnt = (u32)get_unaligned_be16(&scmd->cmnd[7]);
  2264. break;
  2265. case WRITE_12:
  2266. rmd->is_write = true;
  2267. fallthrough;
  2268. case READ_12:
  2269. rmd->first_block = (u64)get_unaligned_be32(&scmd->cmnd[2]);
  2270. rmd->block_cnt = get_unaligned_be32(&scmd->cmnd[6]);
  2271. break;
  2272. case WRITE_16:
  2273. rmd->is_write = true;
  2274. fallthrough;
  2275. case READ_16:
  2276. rmd->first_block = get_unaligned_be64(&scmd->cmnd[2]);
  2277. rmd->block_cnt = get_unaligned_be32(&scmd->cmnd[10]);
  2278. break;
  2279. default:
  2280. /* Process via normal I/O path. */
  2281. return PQI_RAID_BYPASS_INELIGIBLE;
  2282. }
  2283. put_unaligned_le32(scsi_bufflen(scmd), &rmd->data_length);
  2284. return 0;
  2285. }
  2286. static int pci_get_aio_common_raid_map_values(struct pqi_ctrl_info *ctrl_info,
  2287. struct pqi_scsi_dev_raid_map_data *rmd, struct raid_map *raid_map)
  2288. {
  2289. #if BITS_PER_LONG == 32
  2290. u64 tmpdiv;
  2291. #endif
  2292. rmd->last_block = rmd->first_block + rmd->block_cnt - 1;
  2293. /* Check for invalid block or wraparound. */
  2294. if (rmd->last_block >=
  2295. get_unaligned_le64(&raid_map->volume_blk_cnt) ||
  2296. rmd->last_block < rmd->first_block)
  2297. return PQI_RAID_BYPASS_INELIGIBLE;
  2298. rmd->data_disks_per_row =
  2299. get_unaligned_le16(&raid_map->data_disks_per_row);
  2300. rmd->strip_size = get_unaligned_le16(&raid_map->strip_size);
  2301. rmd->layout_map_count = get_unaligned_le16(&raid_map->layout_map_count);
  2302. /* Calculate stripe information for the request. */
  2303. rmd->blocks_per_row = rmd->data_disks_per_row * rmd->strip_size;
  2304. if (rmd->blocks_per_row == 0) /* Used as a divisor in many calculations */
  2305. return PQI_RAID_BYPASS_INELIGIBLE;
  2306. #if BITS_PER_LONG == 32
  2307. tmpdiv = rmd->first_block;
  2308. do_div(tmpdiv, rmd->blocks_per_row);
  2309. rmd->first_row = tmpdiv;
  2310. tmpdiv = rmd->last_block;
  2311. do_div(tmpdiv, rmd->blocks_per_row);
  2312. rmd->last_row = tmpdiv;
  2313. rmd->first_row_offset = (u32)(rmd->first_block - (rmd->first_row * rmd->blocks_per_row));
  2314. rmd->last_row_offset = (u32)(rmd->last_block - (rmd->last_row * rmd->blocks_per_row));
  2315. tmpdiv = rmd->first_row_offset;
  2316. do_div(tmpdiv, rmd->strip_size);
  2317. rmd->first_column = tmpdiv;
  2318. tmpdiv = rmd->last_row_offset;
  2319. do_div(tmpdiv, rmd->strip_size);
  2320. rmd->last_column = tmpdiv;
  2321. #else
  2322. rmd->first_row = rmd->first_block / rmd->blocks_per_row;
  2323. rmd->last_row = rmd->last_block / rmd->blocks_per_row;
  2324. rmd->first_row_offset = (u32)(rmd->first_block -
  2325. (rmd->first_row * rmd->blocks_per_row));
  2326. rmd->last_row_offset = (u32)(rmd->last_block - (rmd->last_row *
  2327. rmd->blocks_per_row));
  2328. rmd->first_column = rmd->first_row_offset / rmd->strip_size;
  2329. rmd->last_column = rmd->last_row_offset / rmd->strip_size;
  2330. #endif
  2331. /* If this isn't a single row/column then give to the controller. */
  2332. if (rmd->first_row != rmd->last_row ||
  2333. rmd->first_column != rmd->last_column)
  2334. return PQI_RAID_BYPASS_INELIGIBLE;
  2335. /* Proceeding with driver mapping. */
  2336. rmd->total_disks_per_row = rmd->data_disks_per_row +
  2337. get_unaligned_le16(&raid_map->metadata_disks_per_row);
  2338. rmd->map_row = ((u32)(rmd->first_row >>
  2339. raid_map->parity_rotation_shift)) %
  2340. get_unaligned_le16(&raid_map->row_cnt);
  2341. rmd->map_index = (rmd->map_row * rmd->total_disks_per_row) +
  2342. rmd->first_column;
  2343. return 0;
  2344. }
  2345. static int pqi_calc_aio_r5_or_r6(struct pqi_scsi_dev_raid_map_data *rmd,
  2346. struct raid_map *raid_map)
  2347. {
  2348. #if BITS_PER_LONG == 32
  2349. u64 tmpdiv;
  2350. #endif
  2351. if (rmd->blocks_per_row == 0) /* Used as a divisor in many calculations */
  2352. return PQI_RAID_BYPASS_INELIGIBLE;
  2353. /* RAID 50/60 */
  2354. /* Verify first and last block are in same RAID group. */
  2355. rmd->stripesize = rmd->blocks_per_row * rmd->layout_map_count;
  2356. #if BITS_PER_LONG == 32
  2357. tmpdiv = rmd->first_block;
  2358. rmd->first_group = do_div(tmpdiv, rmd->stripesize);
  2359. tmpdiv = rmd->first_group;
  2360. do_div(tmpdiv, rmd->blocks_per_row);
  2361. rmd->first_group = tmpdiv;
  2362. tmpdiv = rmd->last_block;
  2363. rmd->last_group = do_div(tmpdiv, rmd->stripesize);
  2364. tmpdiv = rmd->last_group;
  2365. do_div(tmpdiv, rmd->blocks_per_row);
  2366. rmd->last_group = tmpdiv;
  2367. #else
  2368. rmd->first_group = (rmd->first_block % rmd->stripesize) / rmd->blocks_per_row;
  2369. rmd->last_group = (rmd->last_block % rmd->stripesize) / rmd->blocks_per_row;
  2370. #endif
  2371. if (rmd->first_group != rmd->last_group)
  2372. return PQI_RAID_BYPASS_INELIGIBLE;
  2373. /* Verify request is in a single row of RAID 5/6. */
  2374. #if BITS_PER_LONG == 32
  2375. tmpdiv = rmd->first_block;
  2376. do_div(tmpdiv, rmd->stripesize);
  2377. rmd->first_row = tmpdiv;
  2378. rmd->r5or6_first_row = tmpdiv;
  2379. tmpdiv = rmd->last_block;
  2380. do_div(tmpdiv, rmd->stripesize);
  2381. rmd->r5or6_last_row = tmpdiv;
  2382. #else
  2383. rmd->first_row = rmd->r5or6_first_row =
  2384. rmd->first_block / rmd->stripesize;
  2385. rmd->r5or6_last_row = rmd->last_block / rmd->stripesize;
  2386. #endif
  2387. if (rmd->r5or6_first_row != rmd->r5or6_last_row)
  2388. return PQI_RAID_BYPASS_INELIGIBLE;
  2389. /* Verify request is in a single column. */
  2390. #if BITS_PER_LONG == 32
  2391. tmpdiv = rmd->first_block;
  2392. rmd->first_row_offset = do_div(tmpdiv, rmd->stripesize);
  2393. tmpdiv = rmd->first_row_offset;
  2394. rmd->first_row_offset = (u32)do_div(tmpdiv, rmd->blocks_per_row);
  2395. rmd->r5or6_first_row_offset = rmd->first_row_offset;
  2396. tmpdiv = rmd->last_block;
  2397. rmd->r5or6_last_row_offset = do_div(tmpdiv, rmd->stripesize);
  2398. tmpdiv = rmd->r5or6_last_row_offset;
  2399. rmd->r5or6_last_row_offset = do_div(tmpdiv, rmd->blocks_per_row);
  2400. tmpdiv = rmd->r5or6_first_row_offset;
  2401. do_div(tmpdiv, rmd->strip_size);
  2402. rmd->first_column = rmd->r5or6_first_column = tmpdiv;
  2403. tmpdiv = rmd->r5or6_last_row_offset;
  2404. do_div(tmpdiv, rmd->strip_size);
  2405. rmd->r5or6_last_column = tmpdiv;
  2406. #else
  2407. rmd->first_row_offset = rmd->r5or6_first_row_offset =
  2408. (u32)((rmd->first_block % rmd->stripesize) %
  2409. rmd->blocks_per_row);
  2410. rmd->r5or6_last_row_offset =
  2411. (u32)((rmd->last_block % rmd->stripesize) %
  2412. rmd->blocks_per_row);
  2413. rmd->first_column =
  2414. rmd->r5or6_first_row_offset / rmd->strip_size;
  2415. rmd->r5or6_first_column = rmd->first_column;
  2416. rmd->r5or6_last_column = rmd->r5or6_last_row_offset / rmd->strip_size;
  2417. #endif
  2418. if (rmd->r5or6_first_column != rmd->r5or6_last_column)
  2419. return PQI_RAID_BYPASS_INELIGIBLE;
  2420. /* Request is eligible. */
  2421. rmd->map_row =
  2422. ((u32)(rmd->first_row >> raid_map->parity_rotation_shift)) %
  2423. get_unaligned_le16(&raid_map->row_cnt);
  2424. rmd->map_index = (rmd->first_group *
  2425. (get_unaligned_le16(&raid_map->row_cnt) *
  2426. rmd->total_disks_per_row)) +
  2427. (rmd->map_row * rmd->total_disks_per_row) + rmd->first_column;
  2428. if (rmd->is_write) {
  2429. u32 index;
  2430. /*
  2431. * p_parity_it_nexus and q_parity_it_nexus are pointers to the
  2432. * parity entries inside the device's raid_map.
  2433. *
  2434. * A device's RAID map is bounded by: number of RAID disks squared.
  2435. *
  2436. * The devices RAID map size is checked during device
  2437. * initialization.
  2438. */
  2439. index = DIV_ROUND_UP(rmd->map_index + 1, rmd->total_disks_per_row);
  2440. index *= rmd->total_disks_per_row;
  2441. index -= get_unaligned_le16(&raid_map->metadata_disks_per_row);
  2442. rmd->p_parity_it_nexus = raid_map->disk_data[index].aio_handle;
  2443. if (rmd->raid_level == SA_RAID_6) {
  2444. rmd->q_parity_it_nexus = raid_map->disk_data[index + 1].aio_handle;
  2445. rmd->xor_mult = raid_map->disk_data[rmd->map_index].xor_mult[1];
  2446. }
  2447. #if BITS_PER_LONG == 32
  2448. tmpdiv = rmd->first_block;
  2449. do_div(tmpdiv, rmd->blocks_per_row);
  2450. rmd->row = tmpdiv;
  2451. #else
  2452. rmd->row = rmd->first_block / rmd->blocks_per_row;
  2453. #endif
  2454. }
  2455. return 0;
  2456. }
  2457. static void pqi_set_aio_cdb(struct pqi_scsi_dev_raid_map_data *rmd)
  2458. {
  2459. /* Build the new CDB for the physical disk I/O. */
  2460. if (rmd->disk_block > 0xffffffff) {
  2461. rmd->cdb[0] = rmd->is_write ? WRITE_16 : READ_16;
  2462. rmd->cdb[1] = 0;
  2463. put_unaligned_be64(rmd->disk_block, &rmd->cdb[2]);
  2464. put_unaligned_be32(rmd->disk_block_cnt, &rmd->cdb[10]);
  2465. rmd->cdb[14] = 0;
  2466. rmd->cdb[15] = 0;
  2467. rmd->cdb_length = 16;
  2468. } else {
  2469. rmd->cdb[0] = rmd->is_write ? WRITE_10 : READ_10;
  2470. rmd->cdb[1] = 0;
  2471. put_unaligned_be32((u32)rmd->disk_block, &rmd->cdb[2]);
  2472. rmd->cdb[6] = 0;
  2473. put_unaligned_be16((u16)rmd->disk_block_cnt, &rmd->cdb[7]);
  2474. rmd->cdb[9] = 0;
  2475. rmd->cdb_length = 10;
  2476. }
  2477. }
  2478. static void pqi_calc_aio_r1_nexus(struct raid_map *raid_map,
  2479. struct pqi_scsi_dev_raid_map_data *rmd)
  2480. {
  2481. u32 index;
  2482. u32 group;
  2483. group = rmd->map_index / rmd->data_disks_per_row;
  2484. index = rmd->map_index - (group * rmd->data_disks_per_row);
  2485. rmd->it_nexus[0] = raid_map->disk_data[index].aio_handle;
  2486. index += rmd->data_disks_per_row;
  2487. rmd->it_nexus[1] = raid_map->disk_data[index].aio_handle;
  2488. if (rmd->layout_map_count > 2) {
  2489. index += rmd->data_disks_per_row;
  2490. rmd->it_nexus[2] = raid_map->disk_data[index].aio_handle;
  2491. }
  2492. rmd->num_it_nexus_entries = rmd->layout_map_count;
  2493. }
  2494. static int pqi_raid_bypass_submit_scsi_cmd(struct pqi_ctrl_info *ctrl_info,
  2495. struct pqi_scsi_dev *device, struct scsi_cmnd *scmd,
  2496. struct pqi_queue_group *queue_group)
  2497. {
  2498. int rc;
  2499. struct raid_map *raid_map;
  2500. u32 group;
  2501. u32 next_bypass_group;
  2502. struct pqi_encryption_info *encryption_info_ptr;
  2503. struct pqi_encryption_info encryption_info;
  2504. struct pqi_scsi_dev_raid_map_data rmd = { 0 };
  2505. rc = pqi_get_aio_lba_and_block_count(scmd, &rmd);
  2506. if (rc)
  2507. return PQI_RAID_BYPASS_INELIGIBLE;
  2508. rmd.raid_level = device->raid_level;
  2509. if (!pqi_aio_raid_level_supported(ctrl_info, &rmd))
  2510. return PQI_RAID_BYPASS_INELIGIBLE;
  2511. if (unlikely(rmd.block_cnt == 0))
  2512. return PQI_RAID_BYPASS_INELIGIBLE;
  2513. raid_map = device->raid_map;
  2514. rc = pci_get_aio_common_raid_map_values(ctrl_info, &rmd, raid_map);
  2515. if (rc)
  2516. return PQI_RAID_BYPASS_INELIGIBLE;
  2517. if (device->raid_level == SA_RAID_1 ||
  2518. device->raid_level == SA_RAID_TRIPLE) {
  2519. if (rmd.is_write) {
  2520. pqi_calc_aio_r1_nexus(raid_map, &rmd);
  2521. } else {
  2522. group = device->next_bypass_group[rmd.map_index];
  2523. next_bypass_group = group + 1;
  2524. if (next_bypass_group >= rmd.layout_map_count)
  2525. next_bypass_group = 0;
  2526. device->next_bypass_group[rmd.map_index] = next_bypass_group;
  2527. rmd.map_index += group * rmd.data_disks_per_row;
  2528. }
  2529. } else if ((device->raid_level == SA_RAID_5 ||
  2530. device->raid_level == SA_RAID_6) &&
  2531. (rmd.layout_map_count > 1 || rmd.is_write)) {
  2532. rc = pqi_calc_aio_r5_or_r6(&rmd, raid_map);
  2533. if (rc)
  2534. return PQI_RAID_BYPASS_INELIGIBLE;
  2535. }
  2536. if (unlikely(rmd.map_index >= RAID_MAP_MAX_ENTRIES))
  2537. return PQI_RAID_BYPASS_INELIGIBLE;
  2538. rmd.aio_handle = raid_map->disk_data[rmd.map_index].aio_handle;
  2539. rmd.disk_block = get_unaligned_le64(&raid_map->disk_starting_blk) +
  2540. rmd.first_row * rmd.strip_size +
  2541. (rmd.first_row_offset - rmd.first_column * rmd.strip_size);
  2542. rmd.disk_block_cnt = rmd.block_cnt;
  2543. /* Handle differing logical/physical block sizes. */
  2544. if (raid_map->phys_blk_shift) {
  2545. rmd.disk_block <<= raid_map->phys_blk_shift;
  2546. rmd.disk_block_cnt <<= raid_map->phys_blk_shift;
  2547. }
  2548. if (unlikely(rmd.disk_block_cnt > 0xffff))
  2549. return PQI_RAID_BYPASS_INELIGIBLE;
  2550. pqi_set_aio_cdb(&rmd);
  2551. if (get_unaligned_le16(&raid_map->flags) & RAID_MAP_ENCRYPTION_ENABLED) {
  2552. if (rmd.data_length > device->max_transfer_encrypted)
  2553. return PQI_RAID_BYPASS_INELIGIBLE;
  2554. pqi_set_encryption_info(&encryption_info, raid_map, rmd.first_block);
  2555. encryption_info_ptr = &encryption_info;
  2556. } else {
  2557. encryption_info_ptr = NULL;
  2558. }
  2559. if (rmd.is_write) {
  2560. switch (device->raid_level) {
  2561. case SA_RAID_1:
  2562. case SA_RAID_TRIPLE:
  2563. return pqi_aio_submit_r1_write_io(ctrl_info, scmd, queue_group,
  2564. encryption_info_ptr, device, &rmd);
  2565. case SA_RAID_5:
  2566. case SA_RAID_6:
  2567. return pqi_aio_submit_r56_write_io(ctrl_info, scmd, queue_group,
  2568. encryption_info_ptr, device, &rmd);
  2569. }
  2570. }
  2571. return pqi_aio_submit_io(ctrl_info, scmd, rmd.aio_handle,
  2572. rmd.cdb, rmd.cdb_length, queue_group,
  2573. encryption_info_ptr, true, false);
  2574. }
  2575. #define PQI_STATUS_IDLE 0x0
  2576. #define PQI_CREATE_ADMIN_QUEUE_PAIR 1
  2577. #define PQI_DELETE_ADMIN_QUEUE_PAIR 2
  2578. #define PQI_DEVICE_STATE_POWER_ON_AND_RESET 0x0
  2579. #define PQI_DEVICE_STATE_STATUS_AVAILABLE 0x1
  2580. #define PQI_DEVICE_STATE_ALL_REGISTERS_READY 0x2
  2581. #define PQI_DEVICE_STATE_ADMIN_QUEUE_PAIR_READY 0x3
  2582. #define PQI_DEVICE_STATE_ERROR 0x4
  2583. #define PQI_MODE_READY_TIMEOUT_SECS 30
  2584. #define PQI_MODE_READY_POLL_INTERVAL_MSECS 1
  2585. static int pqi_wait_for_pqi_mode_ready(struct pqi_ctrl_info *ctrl_info)
  2586. {
  2587. struct pqi_device_registers __iomem *pqi_registers;
  2588. unsigned long timeout;
  2589. u64 signature;
  2590. u8 status;
  2591. pqi_registers = ctrl_info->pqi_registers;
  2592. timeout = (PQI_MODE_READY_TIMEOUT_SECS * HZ) + jiffies;
  2593. while (1) {
  2594. signature = readq(&pqi_registers->signature);
  2595. if (memcmp(&signature, PQI_DEVICE_SIGNATURE,
  2596. sizeof(signature)) == 0)
  2597. break;
  2598. if (time_after(jiffies, timeout)) {
  2599. dev_err(&ctrl_info->pci_dev->dev,
  2600. "timed out waiting for PQI signature\n");
  2601. return -ETIMEDOUT;
  2602. }
  2603. msleep(PQI_MODE_READY_POLL_INTERVAL_MSECS);
  2604. }
  2605. while (1) {
  2606. status = readb(&pqi_registers->function_and_status_code);
  2607. if (status == PQI_STATUS_IDLE)
  2608. break;
  2609. if (time_after(jiffies, timeout)) {
  2610. dev_err(&ctrl_info->pci_dev->dev,
  2611. "timed out waiting for PQI IDLE\n");
  2612. return -ETIMEDOUT;
  2613. }
  2614. msleep(PQI_MODE_READY_POLL_INTERVAL_MSECS);
  2615. }
  2616. while (1) {
  2617. if (readl(&pqi_registers->device_status) ==
  2618. PQI_DEVICE_STATE_ALL_REGISTERS_READY)
  2619. break;
  2620. if (time_after(jiffies, timeout)) {
  2621. dev_err(&ctrl_info->pci_dev->dev,
  2622. "timed out waiting for PQI all registers ready\n");
  2623. return -ETIMEDOUT;
  2624. }
  2625. msleep(PQI_MODE_READY_POLL_INTERVAL_MSECS);
  2626. }
  2627. return 0;
  2628. }
  2629. static inline void pqi_aio_path_disabled(struct pqi_io_request *io_request)
  2630. {
  2631. struct pqi_scsi_dev *device;
  2632. device = io_request->scmd->device->hostdata;
  2633. device->raid_bypass_enabled = false;
  2634. device->aio_enabled = false;
  2635. }
  2636. static inline void pqi_take_device_offline(struct scsi_device *sdev, char *path)
  2637. {
  2638. struct pqi_ctrl_info *ctrl_info;
  2639. struct pqi_scsi_dev *device;
  2640. device = sdev->hostdata;
  2641. if (device->device_offline)
  2642. return;
  2643. device->device_offline = true;
  2644. ctrl_info = shost_to_hba(sdev->host);
  2645. pqi_schedule_rescan_worker(ctrl_info);
  2646. dev_err(&ctrl_info->pci_dev->dev, "re-scanning %s scsi %d:%d:%d:%d\n",
  2647. path, ctrl_info->scsi_host->host_no, device->bus,
  2648. device->target, device->lun);
  2649. }
  2650. static void pqi_process_raid_io_error(struct pqi_io_request *io_request)
  2651. {
  2652. u8 scsi_status;
  2653. u8 host_byte;
  2654. struct scsi_cmnd *scmd;
  2655. struct pqi_raid_error_info *error_info;
  2656. size_t sense_data_length;
  2657. int residual_count;
  2658. int xfer_count;
  2659. struct scsi_sense_hdr sshdr;
  2660. scmd = io_request->scmd;
  2661. if (!scmd)
  2662. return;
  2663. error_info = io_request->error_info;
  2664. scsi_status = error_info->status;
  2665. host_byte = DID_OK;
  2666. switch (error_info->data_out_result) {
  2667. case PQI_DATA_IN_OUT_GOOD:
  2668. break;
  2669. case PQI_DATA_IN_OUT_UNDERFLOW:
  2670. xfer_count =
  2671. get_unaligned_le32(&error_info->data_out_transferred);
  2672. residual_count = scsi_bufflen(scmd) - xfer_count;
  2673. scsi_set_resid(scmd, residual_count);
  2674. if (xfer_count < scmd->underflow)
  2675. host_byte = DID_SOFT_ERROR;
  2676. break;
  2677. case PQI_DATA_IN_OUT_UNSOLICITED_ABORT:
  2678. case PQI_DATA_IN_OUT_ABORTED:
  2679. host_byte = DID_ABORT;
  2680. break;
  2681. case PQI_DATA_IN_OUT_TIMEOUT:
  2682. host_byte = DID_TIME_OUT;
  2683. break;
  2684. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW:
  2685. case PQI_DATA_IN_OUT_PROTOCOL_ERROR:
  2686. case PQI_DATA_IN_OUT_BUFFER_ERROR:
  2687. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA:
  2688. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE:
  2689. case PQI_DATA_IN_OUT_ERROR:
  2690. case PQI_DATA_IN_OUT_HARDWARE_ERROR:
  2691. case PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR:
  2692. case PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT:
  2693. case PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED:
  2694. case PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED:
  2695. case PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED:
  2696. case PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST:
  2697. case PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION:
  2698. case PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED:
  2699. case PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ:
  2700. default:
  2701. host_byte = DID_ERROR;
  2702. break;
  2703. }
  2704. sense_data_length = get_unaligned_le16(&error_info->sense_data_length);
  2705. if (sense_data_length == 0)
  2706. sense_data_length =
  2707. get_unaligned_le16(&error_info->response_data_length);
  2708. if (sense_data_length) {
  2709. if (sense_data_length > sizeof(error_info->data))
  2710. sense_data_length = sizeof(error_info->data);
  2711. if (scsi_status == SAM_STAT_CHECK_CONDITION &&
  2712. scsi_normalize_sense(error_info->data,
  2713. sense_data_length, &sshdr) &&
  2714. sshdr.sense_key == HARDWARE_ERROR &&
  2715. sshdr.asc == 0x3e) {
  2716. struct pqi_ctrl_info *ctrl_info = shost_to_hba(scmd->device->host);
  2717. struct pqi_scsi_dev *device = scmd->device->hostdata;
  2718. switch (sshdr.ascq) {
  2719. case 0x1: /* LOGICAL UNIT FAILURE */
  2720. if (printk_ratelimit())
  2721. scmd_printk(KERN_ERR, scmd, "received 'logical unit failure' from controller for scsi %d:%d:%d:%d\n",
  2722. ctrl_info->scsi_host->host_no, device->bus, device->target, device->lun);
  2723. pqi_take_device_offline(scmd->device, "RAID");
  2724. host_byte = DID_NO_CONNECT;
  2725. break;
  2726. default: /* See http://www.t10.org/lists/asc-num.htm#ASC_3E */
  2727. if (printk_ratelimit())
  2728. scmd_printk(KERN_ERR, scmd, "received unhandled error %d from controller for scsi %d:%d:%d:%d\n",
  2729. sshdr.ascq, ctrl_info->scsi_host->host_no, device->bus, device->target, device->lun);
  2730. break;
  2731. }
  2732. }
  2733. if (sense_data_length > SCSI_SENSE_BUFFERSIZE)
  2734. sense_data_length = SCSI_SENSE_BUFFERSIZE;
  2735. memcpy(scmd->sense_buffer, error_info->data,
  2736. sense_data_length);
  2737. }
  2738. if (pqi_cmd_priv(scmd)->this_residual &&
  2739. !pqi_is_logical_device(scmd->device->hostdata) &&
  2740. scsi_status == SAM_STAT_CHECK_CONDITION &&
  2741. host_byte == DID_OK &&
  2742. sense_data_length &&
  2743. scsi_normalize_sense(error_info->data, sense_data_length, &sshdr) &&
  2744. sshdr.sense_key == ILLEGAL_REQUEST &&
  2745. sshdr.asc == 0x26 &&
  2746. sshdr.ascq == 0x0) {
  2747. host_byte = DID_NO_CONNECT;
  2748. pqi_take_device_offline(scmd->device, "AIO");
  2749. scsi_build_sense_buffer(0, scmd->sense_buffer, HARDWARE_ERROR, 0x3e, 0x1);
  2750. }
  2751. scmd->result = scsi_status;
  2752. set_host_byte(scmd, host_byte);
  2753. }
  2754. static void pqi_process_aio_io_error(struct pqi_io_request *io_request)
  2755. {
  2756. u8 scsi_status;
  2757. u8 host_byte;
  2758. struct scsi_cmnd *scmd;
  2759. struct pqi_aio_error_info *error_info;
  2760. size_t sense_data_length;
  2761. int residual_count;
  2762. int xfer_count;
  2763. bool device_offline;
  2764. scmd = io_request->scmd;
  2765. error_info = io_request->error_info;
  2766. host_byte = DID_OK;
  2767. sense_data_length = 0;
  2768. device_offline = false;
  2769. switch (error_info->service_response) {
  2770. case PQI_AIO_SERV_RESPONSE_COMPLETE:
  2771. scsi_status = error_info->status;
  2772. break;
  2773. case PQI_AIO_SERV_RESPONSE_FAILURE:
  2774. switch (error_info->status) {
  2775. case PQI_AIO_STATUS_IO_ABORTED:
  2776. scsi_status = SAM_STAT_TASK_ABORTED;
  2777. break;
  2778. case PQI_AIO_STATUS_UNDERRUN:
  2779. scsi_status = SAM_STAT_GOOD;
  2780. residual_count = get_unaligned_le32(
  2781. &error_info->residual_count);
  2782. scsi_set_resid(scmd, residual_count);
  2783. xfer_count = scsi_bufflen(scmd) - residual_count;
  2784. if (xfer_count < scmd->underflow)
  2785. host_byte = DID_SOFT_ERROR;
  2786. break;
  2787. case PQI_AIO_STATUS_OVERRUN:
  2788. scsi_status = SAM_STAT_GOOD;
  2789. break;
  2790. case PQI_AIO_STATUS_AIO_PATH_DISABLED:
  2791. pqi_aio_path_disabled(io_request);
  2792. scsi_status = SAM_STAT_GOOD;
  2793. io_request->status = -EAGAIN;
  2794. break;
  2795. case PQI_AIO_STATUS_NO_PATH_TO_DEVICE:
  2796. case PQI_AIO_STATUS_INVALID_DEVICE:
  2797. if (!io_request->raid_bypass) {
  2798. device_offline = true;
  2799. pqi_take_device_offline(scmd->device, "AIO");
  2800. host_byte = DID_NO_CONNECT;
  2801. }
  2802. scsi_status = SAM_STAT_CHECK_CONDITION;
  2803. break;
  2804. case PQI_AIO_STATUS_IO_ERROR:
  2805. default:
  2806. scsi_status = SAM_STAT_CHECK_CONDITION;
  2807. break;
  2808. }
  2809. break;
  2810. case PQI_AIO_SERV_RESPONSE_TMF_COMPLETE:
  2811. case PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED:
  2812. scsi_status = SAM_STAT_GOOD;
  2813. break;
  2814. case PQI_AIO_SERV_RESPONSE_TMF_REJECTED:
  2815. case PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN:
  2816. default:
  2817. scsi_status = SAM_STAT_CHECK_CONDITION;
  2818. break;
  2819. }
  2820. if (error_info->data_present) {
  2821. sense_data_length =
  2822. get_unaligned_le16(&error_info->data_length);
  2823. if (sense_data_length) {
  2824. if (sense_data_length > sizeof(error_info->data))
  2825. sense_data_length = sizeof(error_info->data);
  2826. if (sense_data_length > SCSI_SENSE_BUFFERSIZE)
  2827. sense_data_length = SCSI_SENSE_BUFFERSIZE;
  2828. memcpy(scmd->sense_buffer, error_info->data,
  2829. sense_data_length);
  2830. }
  2831. }
  2832. if (device_offline && sense_data_length == 0)
  2833. scsi_build_sense(scmd, 0, HARDWARE_ERROR, 0x3e, 0x1);
  2834. scmd->result = scsi_status;
  2835. set_host_byte(scmd, host_byte);
  2836. }
  2837. static void pqi_process_io_error(unsigned int iu_type,
  2838. struct pqi_io_request *io_request)
  2839. {
  2840. switch (iu_type) {
  2841. case PQI_RESPONSE_IU_RAID_PATH_IO_ERROR:
  2842. pqi_process_raid_io_error(io_request);
  2843. break;
  2844. case PQI_RESPONSE_IU_AIO_PATH_IO_ERROR:
  2845. pqi_process_aio_io_error(io_request);
  2846. break;
  2847. }
  2848. }
  2849. static int pqi_interpret_task_management_response(struct pqi_ctrl_info *ctrl_info,
  2850. struct pqi_task_management_response *response)
  2851. {
  2852. int rc;
  2853. switch (response->response_code) {
  2854. case SOP_TMF_COMPLETE:
  2855. case SOP_TMF_FUNCTION_SUCCEEDED:
  2856. rc = 0;
  2857. break;
  2858. case SOP_TMF_REJECTED:
  2859. rc = -EAGAIN;
  2860. break;
  2861. case SOP_TMF_INCORRECT_LOGICAL_UNIT:
  2862. rc = -ENODEV;
  2863. break;
  2864. default:
  2865. rc = -EIO;
  2866. break;
  2867. }
  2868. if (rc)
  2869. dev_err(&ctrl_info->pci_dev->dev,
  2870. "Task Management Function error: %d (response code: %u)\n", rc, response->response_code);
  2871. return rc;
  2872. }
  2873. static inline void pqi_invalid_response(struct pqi_ctrl_info *ctrl_info,
  2874. enum pqi_ctrl_shutdown_reason ctrl_shutdown_reason)
  2875. {
  2876. pqi_take_ctrl_offline(ctrl_info, ctrl_shutdown_reason);
  2877. }
  2878. static int pqi_process_io_intr(struct pqi_ctrl_info *ctrl_info, struct pqi_queue_group *queue_group)
  2879. {
  2880. int num_responses;
  2881. pqi_index_t oq_pi;
  2882. pqi_index_t oq_ci;
  2883. struct pqi_io_request *io_request;
  2884. struct pqi_io_response *response;
  2885. u16 request_id;
  2886. num_responses = 0;
  2887. oq_ci = queue_group->oq_ci_copy;
  2888. while (1) {
  2889. oq_pi = readl(queue_group->oq_pi);
  2890. if (oq_pi >= ctrl_info->num_elements_per_oq) {
  2891. pqi_invalid_response(ctrl_info, PQI_IO_PI_OUT_OF_RANGE);
  2892. dev_err(&ctrl_info->pci_dev->dev,
  2893. "I/O interrupt: producer index (%u) out of range (0-%u): consumer index: %u\n",
  2894. oq_pi, ctrl_info->num_elements_per_oq - 1, oq_ci);
  2895. return -1;
  2896. }
  2897. if (oq_pi == oq_ci)
  2898. break;
  2899. num_responses++;
  2900. response = queue_group->oq_element_array +
  2901. (oq_ci * PQI_OPERATIONAL_OQ_ELEMENT_LENGTH);
  2902. request_id = get_unaligned_le16(&response->request_id);
  2903. if (request_id >= ctrl_info->max_io_slots) {
  2904. pqi_invalid_response(ctrl_info, PQI_INVALID_REQ_ID);
  2905. dev_err(&ctrl_info->pci_dev->dev,
  2906. "request ID in response (%u) out of range (0-%u): producer index: %u consumer index: %u\n",
  2907. request_id, ctrl_info->max_io_slots - 1, oq_pi, oq_ci);
  2908. return -1;
  2909. }
  2910. io_request = &ctrl_info->io_request_pool[request_id];
  2911. if (atomic_read(&io_request->refcount) == 0) {
  2912. pqi_invalid_response(ctrl_info, PQI_UNMATCHED_REQ_ID);
  2913. dev_err(&ctrl_info->pci_dev->dev,
  2914. "request ID in response (%u) does not match an outstanding I/O request: producer index: %u consumer index: %u\n",
  2915. request_id, oq_pi, oq_ci);
  2916. return -1;
  2917. }
  2918. switch (response->header.iu_type) {
  2919. case PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS:
  2920. case PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS:
  2921. if (io_request->scmd)
  2922. io_request->scmd->result = 0;
  2923. fallthrough;
  2924. case PQI_RESPONSE_IU_GENERAL_MANAGEMENT:
  2925. break;
  2926. case PQI_RESPONSE_IU_VENDOR_GENERAL:
  2927. io_request->status =
  2928. get_unaligned_le16(
  2929. &((struct pqi_vendor_general_response *)response)->status);
  2930. break;
  2931. case PQI_RESPONSE_IU_TASK_MANAGEMENT:
  2932. io_request->status = pqi_interpret_task_management_response(ctrl_info,
  2933. (void *)response);
  2934. break;
  2935. case PQI_RESPONSE_IU_AIO_PATH_DISABLED:
  2936. pqi_aio_path_disabled(io_request);
  2937. io_request->status = -EAGAIN;
  2938. break;
  2939. case PQI_RESPONSE_IU_RAID_PATH_IO_ERROR:
  2940. case PQI_RESPONSE_IU_AIO_PATH_IO_ERROR:
  2941. io_request->error_info = ctrl_info->error_buffer +
  2942. (get_unaligned_le16(&response->error_index) *
  2943. PQI_ERROR_BUFFER_ELEMENT_LENGTH);
  2944. pqi_process_io_error(response->header.iu_type, io_request);
  2945. break;
  2946. default:
  2947. pqi_invalid_response(ctrl_info, PQI_UNEXPECTED_IU_TYPE);
  2948. dev_err(&ctrl_info->pci_dev->dev,
  2949. "unexpected IU type: 0x%x: producer index: %u consumer index: %u\n",
  2950. response->header.iu_type, oq_pi, oq_ci);
  2951. return -1;
  2952. }
  2953. io_request->io_complete_callback(io_request, io_request->context);
  2954. /*
  2955. * Note that the I/O request structure CANNOT BE TOUCHED after
  2956. * returning from the I/O completion callback!
  2957. */
  2958. oq_ci = (oq_ci + 1) % ctrl_info->num_elements_per_oq;
  2959. }
  2960. if (num_responses) {
  2961. queue_group->oq_ci_copy = oq_ci;
  2962. writel(oq_ci, queue_group->oq_ci);
  2963. }
  2964. return num_responses;
  2965. }
  2966. static inline unsigned int pqi_num_elements_free(unsigned int pi,
  2967. unsigned int ci, unsigned int elements_in_queue)
  2968. {
  2969. unsigned int num_elements_used;
  2970. if (pi >= ci)
  2971. num_elements_used = pi - ci;
  2972. else
  2973. num_elements_used = elements_in_queue - ci + pi;
  2974. return elements_in_queue - num_elements_used - 1;
  2975. }
  2976. static void pqi_send_event_ack(struct pqi_ctrl_info *ctrl_info,
  2977. struct pqi_event_acknowledge_request *iu, size_t iu_length)
  2978. {
  2979. pqi_index_t iq_pi;
  2980. pqi_index_t iq_ci;
  2981. unsigned long flags;
  2982. void *next_element;
  2983. struct pqi_queue_group *queue_group;
  2984. queue_group = &ctrl_info->queue_groups[PQI_DEFAULT_QUEUE_GROUP];
  2985. put_unaligned_le16(queue_group->oq_id, &iu->header.response_queue_id);
  2986. while (1) {
  2987. spin_lock_irqsave(&queue_group->submit_lock[RAID_PATH], flags);
  2988. iq_pi = queue_group->iq_pi_copy[RAID_PATH];
  2989. iq_ci = readl(queue_group->iq_ci[RAID_PATH]);
  2990. if (pqi_num_elements_free(iq_pi, iq_ci,
  2991. ctrl_info->num_elements_per_iq))
  2992. break;
  2993. spin_unlock_irqrestore(
  2994. &queue_group->submit_lock[RAID_PATH], flags);
  2995. if (pqi_ctrl_offline(ctrl_info))
  2996. return;
  2997. }
  2998. next_element = queue_group->iq_element_array[RAID_PATH] +
  2999. (iq_pi * PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  3000. memcpy(next_element, iu, iu_length);
  3001. iq_pi = (iq_pi + 1) % ctrl_info->num_elements_per_iq;
  3002. queue_group->iq_pi_copy[RAID_PATH] = iq_pi;
  3003. /*
  3004. * This write notifies the controller that an IU is available to be
  3005. * processed.
  3006. */
  3007. writel(iq_pi, queue_group->iq_pi[RAID_PATH]);
  3008. spin_unlock_irqrestore(&queue_group->submit_lock[RAID_PATH], flags);
  3009. }
  3010. static void pqi_acknowledge_event(struct pqi_ctrl_info *ctrl_info,
  3011. struct pqi_event *event)
  3012. {
  3013. struct pqi_event_acknowledge_request request;
  3014. memset(&request, 0, sizeof(request));
  3015. request.header.iu_type = PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT;
  3016. put_unaligned_le16(sizeof(request) - PQI_REQUEST_HEADER_LENGTH,
  3017. &request.header.iu_length);
  3018. request.event_type = event->event_type;
  3019. put_unaligned_le16(event->event_id, &request.event_id);
  3020. put_unaligned_le32(event->additional_event_id, &request.additional_event_id);
  3021. pqi_send_event_ack(ctrl_info, &request, sizeof(request));
  3022. }
  3023. #define PQI_SOFT_RESET_STATUS_TIMEOUT_SECS 30
  3024. #define PQI_SOFT_RESET_STATUS_POLL_INTERVAL_SECS 1
  3025. static enum pqi_soft_reset_status pqi_poll_for_soft_reset_status(
  3026. struct pqi_ctrl_info *ctrl_info)
  3027. {
  3028. u8 status;
  3029. unsigned long timeout;
  3030. timeout = (PQI_SOFT_RESET_STATUS_TIMEOUT_SECS * HZ) + jiffies;
  3031. while (1) {
  3032. status = pqi_read_soft_reset_status(ctrl_info);
  3033. if (status & PQI_SOFT_RESET_INITIATE)
  3034. return RESET_INITIATE_DRIVER;
  3035. if (status & PQI_SOFT_RESET_ABORT)
  3036. return RESET_ABORT;
  3037. if (!sis_is_firmware_running(ctrl_info))
  3038. return RESET_NORESPONSE;
  3039. if (time_after(jiffies, timeout)) {
  3040. dev_warn(&ctrl_info->pci_dev->dev,
  3041. "timed out waiting for soft reset status\n");
  3042. return RESET_TIMEDOUT;
  3043. }
  3044. ssleep(PQI_SOFT_RESET_STATUS_POLL_INTERVAL_SECS);
  3045. }
  3046. }
  3047. static void pqi_process_soft_reset(struct pqi_ctrl_info *ctrl_info)
  3048. {
  3049. int rc;
  3050. unsigned int delay_secs;
  3051. enum pqi_soft_reset_status reset_status;
  3052. if (ctrl_info->soft_reset_handshake_supported)
  3053. reset_status = pqi_poll_for_soft_reset_status(ctrl_info);
  3054. else
  3055. reset_status = RESET_INITIATE_FIRMWARE;
  3056. delay_secs = PQI_POST_RESET_DELAY_SECS;
  3057. switch (reset_status) {
  3058. case RESET_TIMEDOUT:
  3059. delay_secs = PQI_POST_OFA_RESET_DELAY_UPON_TIMEOUT_SECS;
  3060. fallthrough;
  3061. case RESET_INITIATE_DRIVER:
  3062. dev_info(&ctrl_info->pci_dev->dev,
  3063. "Online Firmware Activation: resetting controller\n");
  3064. sis_soft_reset(ctrl_info);
  3065. fallthrough;
  3066. case RESET_INITIATE_FIRMWARE:
  3067. ctrl_info->pqi_mode_enabled = false;
  3068. pqi_save_ctrl_mode(ctrl_info, SIS_MODE);
  3069. rc = pqi_ofa_ctrl_restart(ctrl_info, delay_secs);
  3070. pqi_host_free_buffer(ctrl_info, &ctrl_info->ofa_memory);
  3071. pqi_ctrl_ofa_done(ctrl_info);
  3072. dev_info(&ctrl_info->pci_dev->dev,
  3073. "Online Firmware Activation: %s\n",
  3074. rc == 0 ? "SUCCESS" : "FAILED");
  3075. break;
  3076. case RESET_ABORT:
  3077. dev_info(&ctrl_info->pci_dev->dev,
  3078. "Online Firmware Activation ABORTED\n");
  3079. if (ctrl_info->soft_reset_handshake_supported)
  3080. pqi_clear_soft_reset_status(ctrl_info);
  3081. pqi_host_free_buffer(ctrl_info, &ctrl_info->ofa_memory);
  3082. pqi_ctrl_ofa_done(ctrl_info);
  3083. pqi_ofa_ctrl_unquiesce(ctrl_info);
  3084. break;
  3085. case RESET_NORESPONSE:
  3086. fallthrough;
  3087. default:
  3088. dev_err(&ctrl_info->pci_dev->dev,
  3089. "unexpected Online Firmware Activation reset status: 0x%x\n",
  3090. reset_status);
  3091. pqi_host_free_buffer(ctrl_info, &ctrl_info->ofa_memory);
  3092. pqi_ctrl_ofa_done(ctrl_info);
  3093. pqi_ofa_ctrl_unquiesce(ctrl_info);
  3094. pqi_take_ctrl_offline(ctrl_info, PQI_OFA_RESPONSE_TIMEOUT);
  3095. break;
  3096. }
  3097. }
  3098. static void pqi_ofa_memory_alloc_worker(struct work_struct *work)
  3099. {
  3100. struct pqi_ctrl_info *ctrl_info;
  3101. ctrl_info = container_of(work, struct pqi_ctrl_info, ofa_memory_alloc_work);
  3102. pqi_ctrl_ofa_start(ctrl_info);
  3103. pqi_host_setup_buffer(ctrl_info, &ctrl_info->ofa_memory, ctrl_info->ofa_bytes_requested, ctrl_info->ofa_bytes_requested);
  3104. pqi_host_memory_update(ctrl_info, &ctrl_info->ofa_memory, PQI_VENDOR_GENERAL_OFA_MEMORY_UPDATE);
  3105. }
  3106. static void pqi_ofa_quiesce_worker(struct work_struct *work)
  3107. {
  3108. struct pqi_ctrl_info *ctrl_info;
  3109. struct pqi_event *event;
  3110. ctrl_info = container_of(work, struct pqi_ctrl_info, ofa_quiesce_work);
  3111. event = &ctrl_info->events[pqi_event_type_to_event_index(PQI_EVENT_TYPE_OFA)];
  3112. pqi_ofa_ctrl_quiesce(ctrl_info);
  3113. pqi_acknowledge_event(ctrl_info, event);
  3114. pqi_process_soft_reset(ctrl_info);
  3115. }
  3116. static bool pqi_ofa_process_event(struct pqi_ctrl_info *ctrl_info,
  3117. struct pqi_event *event)
  3118. {
  3119. bool ack_event;
  3120. ack_event = true;
  3121. switch (event->event_id) {
  3122. case PQI_EVENT_OFA_MEMORY_ALLOCATION:
  3123. dev_info(&ctrl_info->pci_dev->dev,
  3124. "received Online Firmware Activation memory allocation request\n");
  3125. schedule_work(&ctrl_info->ofa_memory_alloc_work);
  3126. break;
  3127. case PQI_EVENT_OFA_QUIESCE:
  3128. dev_info(&ctrl_info->pci_dev->dev,
  3129. "received Online Firmware Activation quiesce request\n");
  3130. schedule_work(&ctrl_info->ofa_quiesce_work);
  3131. ack_event = false;
  3132. break;
  3133. case PQI_EVENT_OFA_CANCELED:
  3134. dev_info(&ctrl_info->pci_dev->dev,
  3135. "received Online Firmware Activation cancel request: reason: %u\n",
  3136. ctrl_info->ofa_cancel_reason);
  3137. pqi_host_free_buffer(ctrl_info, &ctrl_info->ofa_memory);
  3138. pqi_ctrl_ofa_done(ctrl_info);
  3139. break;
  3140. default:
  3141. dev_err(&ctrl_info->pci_dev->dev,
  3142. "received unknown Online Firmware Activation request: event ID: %u\n",
  3143. event->event_id);
  3144. break;
  3145. }
  3146. return ack_event;
  3147. }
  3148. static void pqi_mark_volumes_for_rescan(struct pqi_ctrl_info *ctrl_info)
  3149. {
  3150. unsigned long flags;
  3151. struct pqi_scsi_dev *device;
  3152. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  3153. list_for_each_entry(device, &ctrl_info->scsi_device_list, scsi_device_list_entry) {
  3154. if (pqi_is_logical_device(device) && device->devtype == TYPE_DISK)
  3155. device->rescan = true;
  3156. }
  3157. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  3158. }
  3159. static void pqi_disable_raid_bypass(struct pqi_ctrl_info *ctrl_info)
  3160. {
  3161. unsigned long flags;
  3162. struct pqi_scsi_dev *device;
  3163. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  3164. list_for_each_entry(device, &ctrl_info->scsi_device_list, scsi_device_list_entry)
  3165. if (device->raid_bypass_enabled)
  3166. device->raid_bypass_enabled = false;
  3167. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  3168. }
  3169. static void pqi_event_worker(struct work_struct *work)
  3170. {
  3171. unsigned int i;
  3172. bool rescan_needed;
  3173. struct pqi_ctrl_info *ctrl_info;
  3174. struct pqi_event *event;
  3175. bool ack_event;
  3176. ctrl_info = container_of(work, struct pqi_ctrl_info, event_work);
  3177. pqi_ctrl_busy(ctrl_info);
  3178. pqi_wait_if_ctrl_blocked(ctrl_info);
  3179. if (pqi_ctrl_offline(ctrl_info))
  3180. goto out;
  3181. rescan_needed = false;
  3182. event = ctrl_info->events;
  3183. for (i = 0; i < PQI_NUM_SUPPORTED_EVENTS; i++) {
  3184. if (event->pending) {
  3185. event->pending = false;
  3186. if (event->event_type == PQI_EVENT_TYPE_OFA) {
  3187. ack_event = pqi_ofa_process_event(ctrl_info, event);
  3188. } else {
  3189. ack_event = true;
  3190. rescan_needed = true;
  3191. if (event->event_type == PQI_EVENT_TYPE_LOGICAL_DEVICE)
  3192. pqi_mark_volumes_for_rescan(ctrl_info);
  3193. else if (event->event_type == PQI_EVENT_TYPE_AIO_STATE_CHANGE)
  3194. pqi_disable_raid_bypass(ctrl_info);
  3195. }
  3196. if (ack_event)
  3197. pqi_acknowledge_event(ctrl_info, event);
  3198. }
  3199. event++;
  3200. }
  3201. #define PQI_RESCAN_WORK_FOR_EVENT_DELAY (5 * HZ)
  3202. if (rescan_needed)
  3203. pqi_schedule_rescan_worker_with_delay(ctrl_info,
  3204. PQI_RESCAN_WORK_FOR_EVENT_DELAY);
  3205. out:
  3206. pqi_ctrl_unbusy(ctrl_info);
  3207. }
  3208. #define PQI_HEARTBEAT_TIMER_INTERVAL (10 * HZ)
  3209. static void pqi_heartbeat_timer_handler(struct timer_list *t)
  3210. {
  3211. int num_interrupts;
  3212. u32 heartbeat_count;
  3213. struct pqi_ctrl_info *ctrl_info = from_timer(ctrl_info, t, heartbeat_timer);
  3214. pqi_check_ctrl_health(ctrl_info);
  3215. if (pqi_ctrl_offline(ctrl_info))
  3216. return;
  3217. num_interrupts = atomic_read(&ctrl_info->num_interrupts);
  3218. heartbeat_count = pqi_read_heartbeat_counter(ctrl_info);
  3219. if (num_interrupts == ctrl_info->previous_num_interrupts) {
  3220. if (heartbeat_count == ctrl_info->previous_heartbeat_count) {
  3221. dev_err(&ctrl_info->pci_dev->dev,
  3222. "no heartbeat detected - last heartbeat count: %u\n",
  3223. heartbeat_count);
  3224. pqi_take_ctrl_offline(ctrl_info, PQI_NO_HEARTBEAT);
  3225. return;
  3226. }
  3227. } else {
  3228. ctrl_info->previous_num_interrupts = num_interrupts;
  3229. }
  3230. ctrl_info->previous_heartbeat_count = heartbeat_count;
  3231. mod_timer(&ctrl_info->heartbeat_timer,
  3232. jiffies + PQI_HEARTBEAT_TIMER_INTERVAL);
  3233. }
  3234. static void pqi_start_heartbeat_timer(struct pqi_ctrl_info *ctrl_info)
  3235. {
  3236. if (!ctrl_info->heartbeat_counter)
  3237. return;
  3238. ctrl_info->previous_num_interrupts =
  3239. atomic_read(&ctrl_info->num_interrupts);
  3240. ctrl_info->previous_heartbeat_count =
  3241. pqi_read_heartbeat_counter(ctrl_info);
  3242. ctrl_info->heartbeat_timer.expires =
  3243. jiffies + PQI_HEARTBEAT_TIMER_INTERVAL;
  3244. add_timer(&ctrl_info->heartbeat_timer);
  3245. }
  3246. static inline void pqi_stop_heartbeat_timer(struct pqi_ctrl_info *ctrl_info)
  3247. {
  3248. del_timer_sync(&ctrl_info->heartbeat_timer);
  3249. }
  3250. static void pqi_ofa_capture_event_payload(struct pqi_ctrl_info *ctrl_info,
  3251. struct pqi_event *event, struct pqi_event_response *response)
  3252. {
  3253. switch (event->event_id) {
  3254. case PQI_EVENT_OFA_MEMORY_ALLOCATION:
  3255. ctrl_info->ofa_bytes_requested =
  3256. get_unaligned_le32(&response->data.ofa_memory_allocation.bytes_requested);
  3257. break;
  3258. case PQI_EVENT_OFA_CANCELED:
  3259. ctrl_info->ofa_cancel_reason =
  3260. get_unaligned_le16(&response->data.ofa_cancelled.reason);
  3261. break;
  3262. }
  3263. }
  3264. static int pqi_process_event_intr(struct pqi_ctrl_info *ctrl_info)
  3265. {
  3266. int num_events;
  3267. pqi_index_t oq_pi;
  3268. pqi_index_t oq_ci;
  3269. struct pqi_event_queue *event_queue;
  3270. struct pqi_event_response *response;
  3271. struct pqi_event *event;
  3272. int event_index;
  3273. event_queue = &ctrl_info->event_queue;
  3274. num_events = 0;
  3275. oq_ci = event_queue->oq_ci_copy;
  3276. while (1) {
  3277. oq_pi = readl(event_queue->oq_pi);
  3278. if (oq_pi >= PQI_NUM_EVENT_QUEUE_ELEMENTS) {
  3279. pqi_invalid_response(ctrl_info, PQI_EVENT_PI_OUT_OF_RANGE);
  3280. dev_err(&ctrl_info->pci_dev->dev,
  3281. "event interrupt: producer index (%u) out of range (0-%u): consumer index: %u\n",
  3282. oq_pi, PQI_NUM_EVENT_QUEUE_ELEMENTS - 1, oq_ci);
  3283. return -1;
  3284. }
  3285. if (oq_pi == oq_ci)
  3286. break;
  3287. num_events++;
  3288. response = event_queue->oq_element_array + (oq_ci * PQI_EVENT_OQ_ELEMENT_LENGTH);
  3289. event_index = pqi_event_type_to_event_index(response->event_type);
  3290. if (event_index >= 0 && response->request_acknowledge) {
  3291. event = &ctrl_info->events[event_index];
  3292. event->pending = true;
  3293. event->event_type = response->event_type;
  3294. event->event_id = get_unaligned_le16(&response->event_id);
  3295. event->additional_event_id =
  3296. get_unaligned_le32(&response->additional_event_id);
  3297. if (event->event_type == PQI_EVENT_TYPE_OFA)
  3298. pqi_ofa_capture_event_payload(ctrl_info, event, response);
  3299. }
  3300. oq_ci = (oq_ci + 1) % PQI_NUM_EVENT_QUEUE_ELEMENTS;
  3301. }
  3302. if (num_events) {
  3303. event_queue->oq_ci_copy = oq_ci;
  3304. writel(oq_ci, event_queue->oq_ci);
  3305. schedule_work(&ctrl_info->event_work);
  3306. }
  3307. return num_events;
  3308. }
  3309. #define PQI_LEGACY_INTX_MASK 0x1
  3310. static inline void pqi_configure_legacy_intx(struct pqi_ctrl_info *ctrl_info, bool enable_intx)
  3311. {
  3312. u32 intx_mask;
  3313. struct pqi_device_registers __iomem *pqi_registers;
  3314. volatile void __iomem *register_addr;
  3315. pqi_registers = ctrl_info->pqi_registers;
  3316. if (enable_intx)
  3317. register_addr = &pqi_registers->legacy_intx_mask_clear;
  3318. else
  3319. register_addr = &pqi_registers->legacy_intx_mask_set;
  3320. intx_mask = readl(register_addr);
  3321. intx_mask |= PQI_LEGACY_INTX_MASK;
  3322. writel(intx_mask, register_addr);
  3323. }
  3324. static void pqi_change_irq_mode(struct pqi_ctrl_info *ctrl_info,
  3325. enum pqi_irq_mode new_mode)
  3326. {
  3327. switch (ctrl_info->irq_mode) {
  3328. case IRQ_MODE_MSIX:
  3329. switch (new_mode) {
  3330. case IRQ_MODE_MSIX:
  3331. break;
  3332. case IRQ_MODE_INTX:
  3333. pqi_configure_legacy_intx(ctrl_info, true);
  3334. sis_enable_intx(ctrl_info);
  3335. break;
  3336. case IRQ_MODE_NONE:
  3337. break;
  3338. }
  3339. break;
  3340. case IRQ_MODE_INTX:
  3341. switch (new_mode) {
  3342. case IRQ_MODE_MSIX:
  3343. pqi_configure_legacy_intx(ctrl_info, false);
  3344. sis_enable_msix(ctrl_info);
  3345. break;
  3346. case IRQ_MODE_INTX:
  3347. break;
  3348. case IRQ_MODE_NONE:
  3349. pqi_configure_legacy_intx(ctrl_info, false);
  3350. break;
  3351. }
  3352. break;
  3353. case IRQ_MODE_NONE:
  3354. switch (new_mode) {
  3355. case IRQ_MODE_MSIX:
  3356. sis_enable_msix(ctrl_info);
  3357. break;
  3358. case IRQ_MODE_INTX:
  3359. pqi_configure_legacy_intx(ctrl_info, true);
  3360. sis_enable_intx(ctrl_info);
  3361. break;
  3362. case IRQ_MODE_NONE:
  3363. break;
  3364. }
  3365. break;
  3366. }
  3367. ctrl_info->irq_mode = new_mode;
  3368. }
  3369. #define PQI_LEGACY_INTX_PENDING 0x1
  3370. static inline bool pqi_is_valid_irq(struct pqi_ctrl_info *ctrl_info)
  3371. {
  3372. bool valid_irq;
  3373. u32 intx_status;
  3374. switch (ctrl_info->irq_mode) {
  3375. case IRQ_MODE_MSIX:
  3376. valid_irq = true;
  3377. break;
  3378. case IRQ_MODE_INTX:
  3379. intx_status = readl(&ctrl_info->pqi_registers->legacy_intx_status);
  3380. if (intx_status & PQI_LEGACY_INTX_PENDING)
  3381. valid_irq = true;
  3382. else
  3383. valid_irq = false;
  3384. break;
  3385. case IRQ_MODE_NONE:
  3386. default:
  3387. valid_irq = false;
  3388. break;
  3389. }
  3390. return valid_irq;
  3391. }
  3392. static irqreturn_t pqi_irq_handler(int irq, void *data)
  3393. {
  3394. struct pqi_ctrl_info *ctrl_info;
  3395. struct pqi_queue_group *queue_group;
  3396. int num_io_responses_handled;
  3397. int num_events_handled;
  3398. queue_group = data;
  3399. ctrl_info = queue_group->ctrl_info;
  3400. if (!pqi_is_valid_irq(ctrl_info))
  3401. return IRQ_NONE;
  3402. num_io_responses_handled = pqi_process_io_intr(ctrl_info, queue_group);
  3403. if (num_io_responses_handled < 0)
  3404. goto out;
  3405. if (irq == ctrl_info->event_irq) {
  3406. num_events_handled = pqi_process_event_intr(ctrl_info);
  3407. if (num_events_handled < 0)
  3408. goto out;
  3409. } else {
  3410. num_events_handled = 0;
  3411. }
  3412. if (num_io_responses_handled + num_events_handled > 0)
  3413. atomic_inc(&ctrl_info->num_interrupts);
  3414. pqi_start_io(ctrl_info, queue_group, RAID_PATH, NULL);
  3415. pqi_start_io(ctrl_info, queue_group, AIO_PATH, NULL);
  3416. out:
  3417. return IRQ_HANDLED;
  3418. }
  3419. static int pqi_request_irqs(struct pqi_ctrl_info *ctrl_info)
  3420. {
  3421. struct pci_dev *pci_dev = ctrl_info->pci_dev;
  3422. int i;
  3423. int rc;
  3424. ctrl_info->event_irq = pci_irq_vector(pci_dev, 0);
  3425. for (i = 0; i < ctrl_info->num_msix_vectors_enabled; i++) {
  3426. rc = request_irq(pci_irq_vector(pci_dev, i), pqi_irq_handler, 0,
  3427. DRIVER_NAME_SHORT, &ctrl_info->queue_groups[i]);
  3428. if (rc) {
  3429. dev_err(&pci_dev->dev,
  3430. "irq %u init failed with error %d\n",
  3431. pci_irq_vector(pci_dev, i), rc);
  3432. return rc;
  3433. }
  3434. ctrl_info->num_msix_vectors_initialized++;
  3435. }
  3436. return 0;
  3437. }
  3438. static void pqi_free_irqs(struct pqi_ctrl_info *ctrl_info)
  3439. {
  3440. int i;
  3441. for (i = 0; i < ctrl_info->num_msix_vectors_initialized; i++)
  3442. free_irq(pci_irq_vector(ctrl_info->pci_dev, i),
  3443. &ctrl_info->queue_groups[i]);
  3444. ctrl_info->num_msix_vectors_initialized = 0;
  3445. }
  3446. static int pqi_enable_msix_interrupts(struct pqi_ctrl_info *ctrl_info)
  3447. {
  3448. int num_vectors_enabled;
  3449. unsigned int flags = PCI_IRQ_MSIX;
  3450. if (!pqi_disable_managed_interrupts)
  3451. flags |= PCI_IRQ_AFFINITY;
  3452. num_vectors_enabled = pci_alloc_irq_vectors(ctrl_info->pci_dev,
  3453. PQI_MIN_MSIX_VECTORS, ctrl_info->num_queue_groups,
  3454. flags);
  3455. if (num_vectors_enabled < 0) {
  3456. dev_err(&ctrl_info->pci_dev->dev,
  3457. "MSI-X init failed with error %d\n",
  3458. num_vectors_enabled);
  3459. return num_vectors_enabled;
  3460. }
  3461. ctrl_info->num_msix_vectors_enabled = num_vectors_enabled;
  3462. ctrl_info->irq_mode = IRQ_MODE_MSIX;
  3463. return 0;
  3464. }
  3465. static void pqi_disable_msix_interrupts(struct pqi_ctrl_info *ctrl_info)
  3466. {
  3467. if (ctrl_info->num_msix_vectors_enabled) {
  3468. pci_free_irq_vectors(ctrl_info->pci_dev);
  3469. ctrl_info->num_msix_vectors_enabled = 0;
  3470. }
  3471. }
  3472. static int pqi_alloc_operational_queues(struct pqi_ctrl_info *ctrl_info)
  3473. {
  3474. unsigned int i;
  3475. size_t alloc_length;
  3476. size_t element_array_length_per_iq;
  3477. size_t element_array_length_per_oq;
  3478. void *element_array;
  3479. void __iomem *next_queue_index;
  3480. void *aligned_pointer;
  3481. unsigned int num_inbound_queues;
  3482. unsigned int num_outbound_queues;
  3483. unsigned int num_queue_indexes;
  3484. struct pqi_queue_group *queue_group;
  3485. element_array_length_per_iq =
  3486. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH *
  3487. ctrl_info->num_elements_per_iq;
  3488. element_array_length_per_oq =
  3489. PQI_OPERATIONAL_OQ_ELEMENT_LENGTH *
  3490. ctrl_info->num_elements_per_oq;
  3491. num_inbound_queues = ctrl_info->num_queue_groups * 2;
  3492. num_outbound_queues = ctrl_info->num_queue_groups;
  3493. num_queue_indexes = (ctrl_info->num_queue_groups * 3) + 1;
  3494. aligned_pointer = NULL;
  3495. for (i = 0; i < num_inbound_queues; i++) {
  3496. aligned_pointer = PTR_ALIGN(aligned_pointer,
  3497. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3498. aligned_pointer += element_array_length_per_iq;
  3499. }
  3500. for (i = 0; i < num_outbound_queues; i++) {
  3501. aligned_pointer = PTR_ALIGN(aligned_pointer,
  3502. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3503. aligned_pointer += element_array_length_per_oq;
  3504. }
  3505. aligned_pointer = PTR_ALIGN(aligned_pointer,
  3506. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3507. aligned_pointer += PQI_NUM_EVENT_QUEUE_ELEMENTS *
  3508. PQI_EVENT_OQ_ELEMENT_LENGTH;
  3509. for (i = 0; i < num_queue_indexes; i++) {
  3510. aligned_pointer = PTR_ALIGN(aligned_pointer,
  3511. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  3512. aligned_pointer += sizeof(pqi_index_t);
  3513. }
  3514. alloc_length = (size_t)aligned_pointer +
  3515. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT;
  3516. alloc_length += PQI_EXTRA_SGL_MEMORY;
  3517. ctrl_info->queue_memory_base =
  3518. dma_alloc_coherent(&ctrl_info->pci_dev->dev, alloc_length,
  3519. &ctrl_info->queue_memory_base_dma_handle,
  3520. GFP_KERNEL);
  3521. if (!ctrl_info->queue_memory_base)
  3522. return -ENOMEM;
  3523. ctrl_info->queue_memory_length = alloc_length;
  3524. element_array = PTR_ALIGN(ctrl_info->queue_memory_base,
  3525. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3526. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  3527. queue_group = &ctrl_info->queue_groups[i];
  3528. queue_group->iq_element_array[RAID_PATH] = element_array;
  3529. queue_group->iq_element_array_bus_addr[RAID_PATH] =
  3530. ctrl_info->queue_memory_base_dma_handle +
  3531. (element_array - ctrl_info->queue_memory_base);
  3532. element_array += element_array_length_per_iq;
  3533. element_array = PTR_ALIGN(element_array,
  3534. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3535. queue_group->iq_element_array[AIO_PATH] = element_array;
  3536. queue_group->iq_element_array_bus_addr[AIO_PATH] =
  3537. ctrl_info->queue_memory_base_dma_handle +
  3538. (element_array - ctrl_info->queue_memory_base);
  3539. element_array += element_array_length_per_iq;
  3540. element_array = PTR_ALIGN(element_array,
  3541. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3542. }
  3543. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  3544. queue_group = &ctrl_info->queue_groups[i];
  3545. queue_group->oq_element_array = element_array;
  3546. queue_group->oq_element_array_bus_addr =
  3547. ctrl_info->queue_memory_base_dma_handle +
  3548. (element_array - ctrl_info->queue_memory_base);
  3549. element_array += element_array_length_per_oq;
  3550. element_array = PTR_ALIGN(element_array,
  3551. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3552. }
  3553. ctrl_info->event_queue.oq_element_array = element_array;
  3554. ctrl_info->event_queue.oq_element_array_bus_addr =
  3555. ctrl_info->queue_memory_base_dma_handle +
  3556. (element_array - ctrl_info->queue_memory_base);
  3557. element_array += PQI_NUM_EVENT_QUEUE_ELEMENTS *
  3558. PQI_EVENT_OQ_ELEMENT_LENGTH;
  3559. next_queue_index = (void __iomem *)PTR_ALIGN(element_array,
  3560. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  3561. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  3562. queue_group = &ctrl_info->queue_groups[i];
  3563. queue_group->iq_ci[RAID_PATH] = next_queue_index;
  3564. queue_group->iq_ci_bus_addr[RAID_PATH] =
  3565. ctrl_info->queue_memory_base_dma_handle +
  3566. (next_queue_index -
  3567. (void __iomem *)ctrl_info->queue_memory_base);
  3568. next_queue_index += sizeof(pqi_index_t);
  3569. next_queue_index = PTR_ALIGN(next_queue_index,
  3570. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  3571. queue_group->iq_ci[AIO_PATH] = next_queue_index;
  3572. queue_group->iq_ci_bus_addr[AIO_PATH] =
  3573. ctrl_info->queue_memory_base_dma_handle +
  3574. (next_queue_index -
  3575. (void __iomem *)ctrl_info->queue_memory_base);
  3576. next_queue_index += sizeof(pqi_index_t);
  3577. next_queue_index = PTR_ALIGN(next_queue_index,
  3578. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  3579. queue_group->oq_pi = next_queue_index;
  3580. queue_group->oq_pi_bus_addr =
  3581. ctrl_info->queue_memory_base_dma_handle +
  3582. (next_queue_index -
  3583. (void __iomem *)ctrl_info->queue_memory_base);
  3584. next_queue_index += sizeof(pqi_index_t);
  3585. next_queue_index = PTR_ALIGN(next_queue_index,
  3586. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  3587. }
  3588. ctrl_info->event_queue.oq_pi = next_queue_index;
  3589. ctrl_info->event_queue.oq_pi_bus_addr =
  3590. ctrl_info->queue_memory_base_dma_handle +
  3591. (next_queue_index -
  3592. (void __iomem *)ctrl_info->queue_memory_base);
  3593. return 0;
  3594. }
  3595. static void pqi_init_operational_queues(struct pqi_ctrl_info *ctrl_info)
  3596. {
  3597. unsigned int i;
  3598. u16 next_iq_id = PQI_MIN_OPERATIONAL_QUEUE_ID;
  3599. u16 next_oq_id = PQI_MIN_OPERATIONAL_QUEUE_ID;
  3600. /*
  3601. * Initialize the backpointers to the controller structure in
  3602. * each operational queue group structure.
  3603. */
  3604. for (i = 0; i < ctrl_info->num_queue_groups; i++)
  3605. ctrl_info->queue_groups[i].ctrl_info = ctrl_info;
  3606. /*
  3607. * Assign IDs to all operational queues. Note that the IDs
  3608. * assigned to operational IQs are independent of the IDs
  3609. * assigned to operational OQs.
  3610. */
  3611. ctrl_info->event_queue.oq_id = next_oq_id++;
  3612. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  3613. ctrl_info->queue_groups[i].iq_id[RAID_PATH] = next_iq_id++;
  3614. ctrl_info->queue_groups[i].iq_id[AIO_PATH] = next_iq_id++;
  3615. ctrl_info->queue_groups[i].oq_id = next_oq_id++;
  3616. }
  3617. /*
  3618. * Assign MSI-X table entry indexes to all queues. Note that the
  3619. * interrupt for the event queue is shared with the first queue group.
  3620. */
  3621. ctrl_info->event_queue.int_msg_num = 0;
  3622. for (i = 0; i < ctrl_info->num_queue_groups; i++)
  3623. ctrl_info->queue_groups[i].int_msg_num = i;
  3624. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  3625. spin_lock_init(&ctrl_info->queue_groups[i].submit_lock[0]);
  3626. spin_lock_init(&ctrl_info->queue_groups[i].submit_lock[1]);
  3627. INIT_LIST_HEAD(&ctrl_info->queue_groups[i].request_list[0]);
  3628. INIT_LIST_HEAD(&ctrl_info->queue_groups[i].request_list[1]);
  3629. }
  3630. }
  3631. static int pqi_alloc_admin_queues(struct pqi_ctrl_info *ctrl_info)
  3632. {
  3633. size_t alloc_length;
  3634. struct pqi_admin_queues_aligned *admin_queues_aligned;
  3635. struct pqi_admin_queues *admin_queues;
  3636. alloc_length = sizeof(struct pqi_admin_queues_aligned) +
  3637. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT;
  3638. ctrl_info->admin_queue_memory_base =
  3639. dma_alloc_coherent(&ctrl_info->pci_dev->dev, alloc_length,
  3640. &ctrl_info->admin_queue_memory_base_dma_handle,
  3641. GFP_KERNEL);
  3642. if (!ctrl_info->admin_queue_memory_base)
  3643. return -ENOMEM;
  3644. ctrl_info->admin_queue_memory_length = alloc_length;
  3645. admin_queues = &ctrl_info->admin_queues;
  3646. admin_queues_aligned = PTR_ALIGN(ctrl_info->admin_queue_memory_base,
  3647. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3648. admin_queues->iq_element_array =
  3649. &admin_queues_aligned->iq_element_array;
  3650. admin_queues->oq_element_array =
  3651. &admin_queues_aligned->oq_element_array;
  3652. admin_queues->iq_ci =
  3653. (pqi_index_t __iomem *)&admin_queues_aligned->iq_ci;
  3654. admin_queues->oq_pi =
  3655. (pqi_index_t __iomem *)&admin_queues_aligned->oq_pi;
  3656. admin_queues->iq_element_array_bus_addr =
  3657. ctrl_info->admin_queue_memory_base_dma_handle +
  3658. (admin_queues->iq_element_array -
  3659. ctrl_info->admin_queue_memory_base);
  3660. admin_queues->oq_element_array_bus_addr =
  3661. ctrl_info->admin_queue_memory_base_dma_handle +
  3662. (admin_queues->oq_element_array -
  3663. ctrl_info->admin_queue_memory_base);
  3664. admin_queues->iq_ci_bus_addr =
  3665. ctrl_info->admin_queue_memory_base_dma_handle +
  3666. ((void __iomem *)admin_queues->iq_ci -
  3667. (void __iomem *)ctrl_info->admin_queue_memory_base);
  3668. admin_queues->oq_pi_bus_addr =
  3669. ctrl_info->admin_queue_memory_base_dma_handle +
  3670. ((void __iomem *)admin_queues->oq_pi -
  3671. (void __iomem *)ctrl_info->admin_queue_memory_base);
  3672. return 0;
  3673. }
  3674. #define PQI_ADMIN_QUEUE_CREATE_TIMEOUT_JIFFIES HZ
  3675. #define PQI_ADMIN_QUEUE_CREATE_POLL_INTERVAL_MSECS 1
  3676. static int pqi_create_admin_queues(struct pqi_ctrl_info *ctrl_info)
  3677. {
  3678. struct pqi_device_registers __iomem *pqi_registers;
  3679. struct pqi_admin_queues *admin_queues;
  3680. unsigned long timeout;
  3681. u8 status;
  3682. u32 reg;
  3683. pqi_registers = ctrl_info->pqi_registers;
  3684. admin_queues = &ctrl_info->admin_queues;
  3685. writeq((u64)admin_queues->iq_element_array_bus_addr,
  3686. &pqi_registers->admin_iq_element_array_addr);
  3687. writeq((u64)admin_queues->oq_element_array_bus_addr,
  3688. &pqi_registers->admin_oq_element_array_addr);
  3689. writeq((u64)admin_queues->iq_ci_bus_addr,
  3690. &pqi_registers->admin_iq_ci_addr);
  3691. writeq((u64)admin_queues->oq_pi_bus_addr,
  3692. &pqi_registers->admin_oq_pi_addr);
  3693. reg = PQI_ADMIN_IQ_NUM_ELEMENTS |
  3694. (PQI_ADMIN_OQ_NUM_ELEMENTS << 8) |
  3695. (admin_queues->int_msg_num << 16);
  3696. writel(reg, &pqi_registers->admin_iq_num_elements);
  3697. writel(PQI_CREATE_ADMIN_QUEUE_PAIR,
  3698. &pqi_registers->function_and_status_code);
  3699. timeout = PQI_ADMIN_QUEUE_CREATE_TIMEOUT_JIFFIES + jiffies;
  3700. while (1) {
  3701. msleep(PQI_ADMIN_QUEUE_CREATE_POLL_INTERVAL_MSECS);
  3702. status = readb(&pqi_registers->function_and_status_code);
  3703. if (status == PQI_STATUS_IDLE)
  3704. break;
  3705. if (time_after(jiffies, timeout))
  3706. return -ETIMEDOUT;
  3707. }
  3708. /*
  3709. * The offset registers are not initialized to the correct
  3710. * offsets until *after* the create admin queue pair command
  3711. * completes successfully.
  3712. */
  3713. admin_queues->iq_pi = ctrl_info->iomem_base +
  3714. PQI_DEVICE_REGISTERS_OFFSET +
  3715. readq(&pqi_registers->admin_iq_pi_offset);
  3716. admin_queues->oq_ci = ctrl_info->iomem_base +
  3717. PQI_DEVICE_REGISTERS_OFFSET +
  3718. readq(&pqi_registers->admin_oq_ci_offset);
  3719. return 0;
  3720. }
  3721. static void pqi_submit_admin_request(struct pqi_ctrl_info *ctrl_info,
  3722. struct pqi_general_admin_request *request)
  3723. {
  3724. struct pqi_admin_queues *admin_queues;
  3725. void *next_element;
  3726. pqi_index_t iq_pi;
  3727. admin_queues = &ctrl_info->admin_queues;
  3728. iq_pi = admin_queues->iq_pi_copy;
  3729. next_element = admin_queues->iq_element_array +
  3730. (iq_pi * PQI_ADMIN_IQ_ELEMENT_LENGTH);
  3731. memcpy(next_element, request, sizeof(*request));
  3732. iq_pi = (iq_pi + 1) % PQI_ADMIN_IQ_NUM_ELEMENTS;
  3733. admin_queues->iq_pi_copy = iq_pi;
  3734. /*
  3735. * This write notifies the controller that an IU is available to be
  3736. * processed.
  3737. */
  3738. writel(iq_pi, admin_queues->iq_pi);
  3739. }
  3740. #define PQI_ADMIN_REQUEST_TIMEOUT_SECS 60
  3741. static int pqi_poll_for_admin_response(struct pqi_ctrl_info *ctrl_info,
  3742. struct pqi_general_admin_response *response)
  3743. {
  3744. struct pqi_admin_queues *admin_queues;
  3745. pqi_index_t oq_pi;
  3746. pqi_index_t oq_ci;
  3747. unsigned long timeout;
  3748. admin_queues = &ctrl_info->admin_queues;
  3749. oq_ci = admin_queues->oq_ci_copy;
  3750. timeout = (PQI_ADMIN_REQUEST_TIMEOUT_SECS * HZ) + jiffies;
  3751. while (1) {
  3752. oq_pi = readl(admin_queues->oq_pi);
  3753. if (oq_pi != oq_ci)
  3754. break;
  3755. if (time_after(jiffies, timeout)) {
  3756. dev_err(&ctrl_info->pci_dev->dev,
  3757. "timed out waiting for admin response\n");
  3758. return -ETIMEDOUT;
  3759. }
  3760. if (!sis_is_firmware_running(ctrl_info))
  3761. return -ENXIO;
  3762. usleep_range(1000, 2000);
  3763. }
  3764. memcpy(response, admin_queues->oq_element_array +
  3765. (oq_ci * PQI_ADMIN_OQ_ELEMENT_LENGTH), sizeof(*response));
  3766. oq_ci = (oq_ci + 1) % PQI_ADMIN_OQ_NUM_ELEMENTS;
  3767. admin_queues->oq_ci_copy = oq_ci;
  3768. writel(oq_ci, admin_queues->oq_ci);
  3769. return 0;
  3770. }
  3771. static void pqi_start_io(struct pqi_ctrl_info *ctrl_info,
  3772. struct pqi_queue_group *queue_group, enum pqi_io_path path,
  3773. struct pqi_io_request *io_request)
  3774. {
  3775. struct pqi_io_request *next;
  3776. void *next_element;
  3777. pqi_index_t iq_pi;
  3778. pqi_index_t iq_ci;
  3779. size_t iu_length;
  3780. unsigned long flags;
  3781. unsigned int num_elements_needed;
  3782. unsigned int num_elements_to_end_of_queue;
  3783. size_t copy_count;
  3784. struct pqi_iu_header *request;
  3785. spin_lock_irqsave(&queue_group->submit_lock[path], flags);
  3786. if (io_request) {
  3787. io_request->queue_group = queue_group;
  3788. list_add_tail(&io_request->request_list_entry,
  3789. &queue_group->request_list[path]);
  3790. }
  3791. iq_pi = queue_group->iq_pi_copy[path];
  3792. list_for_each_entry_safe(io_request, next,
  3793. &queue_group->request_list[path], request_list_entry) {
  3794. request = io_request->iu;
  3795. iu_length = get_unaligned_le16(&request->iu_length) +
  3796. PQI_REQUEST_HEADER_LENGTH;
  3797. num_elements_needed =
  3798. DIV_ROUND_UP(iu_length,
  3799. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  3800. iq_ci = readl(queue_group->iq_ci[path]);
  3801. if (num_elements_needed > pqi_num_elements_free(iq_pi, iq_ci,
  3802. ctrl_info->num_elements_per_iq))
  3803. break;
  3804. put_unaligned_le16(queue_group->oq_id,
  3805. &request->response_queue_id);
  3806. next_element = queue_group->iq_element_array[path] +
  3807. (iq_pi * PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  3808. num_elements_to_end_of_queue =
  3809. ctrl_info->num_elements_per_iq - iq_pi;
  3810. if (num_elements_needed <= num_elements_to_end_of_queue) {
  3811. memcpy(next_element, request, iu_length);
  3812. } else {
  3813. copy_count = num_elements_to_end_of_queue *
  3814. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH;
  3815. memcpy(next_element, request, copy_count);
  3816. memcpy(queue_group->iq_element_array[path],
  3817. (u8 *)request + copy_count,
  3818. iu_length - copy_count);
  3819. }
  3820. iq_pi = (iq_pi + num_elements_needed) %
  3821. ctrl_info->num_elements_per_iq;
  3822. list_del(&io_request->request_list_entry);
  3823. }
  3824. if (iq_pi != queue_group->iq_pi_copy[path]) {
  3825. queue_group->iq_pi_copy[path] = iq_pi;
  3826. /*
  3827. * This write notifies the controller that one or more IUs are
  3828. * available to be processed.
  3829. */
  3830. writel(iq_pi, queue_group->iq_pi[path]);
  3831. }
  3832. spin_unlock_irqrestore(&queue_group->submit_lock[path], flags);
  3833. }
  3834. #define PQI_WAIT_FOR_COMPLETION_IO_TIMEOUT_SECS 10
  3835. static int pqi_wait_for_completion_io(struct pqi_ctrl_info *ctrl_info,
  3836. struct completion *wait)
  3837. {
  3838. int rc;
  3839. while (1) {
  3840. if (wait_for_completion_io_timeout(wait,
  3841. PQI_WAIT_FOR_COMPLETION_IO_TIMEOUT_SECS * HZ)) {
  3842. rc = 0;
  3843. break;
  3844. }
  3845. pqi_check_ctrl_health(ctrl_info);
  3846. if (pqi_ctrl_offline(ctrl_info)) {
  3847. rc = -ENXIO;
  3848. break;
  3849. }
  3850. }
  3851. return rc;
  3852. }
  3853. static void pqi_raid_synchronous_complete(struct pqi_io_request *io_request,
  3854. void *context)
  3855. {
  3856. struct completion *waiting = context;
  3857. complete(waiting);
  3858. }
  3859. static int pqi_process_raid_io_error_synchronous(
  3860. struct pqi_raid_error_info *error_info)
  3861. {
  3862. int rc = -EIO;
  3863. switch (error_info->data_out_result) {
  3864. case PQI_DATA_IN_OUT_GOOD:
  3865. if (error_info->status == SAM_STAT_GOOD)
  3866. rc = 0;
  3867. break;
  3868. case PQI_DATA_IN_OUT_UNDERFLOW:
  3869. if (error_info->status == SAM_STAT_GOOD ||
  3870. error_info->status == SAM_STAT_CHECK_CONDITION)
  3871. rc = 0;
  3872. break;
  3873. case PQI_DATA_IN_OUT_ABORTED:
  3874. rc = PQI_CMD_STATUS_ABORTED;
  3875. break;
  3876. }
  3877. return rc;
  3878. }
  3879. static inline bool pqi_is_blockable_request(struct pqi_iu_header *request)
  3880. {
  3881. return (request->driver_flags & PQI_DRIVER_NONBLOCKABLE_REQUEST) == 0;
  3882. }
  3883. static int pqi_submit_raid_request_synchronous(struct pqi_ctrl_info *ctrl_info,
  3884. struct pqi_iu_header *request, unsigned int flags,
  3885. struct pqi_raid_error_info *error_info)
  3886. {
  3887. int rc = 0;
  3888. struct pqi_io_request *io_request;
  3889. size_t iu_length;
  3890. DECLARE_COMPLETION_ONSTACK(wait);
  3891. if (flags & PQI_SYNC_FLAGS_INTERRUPTABLE) {
  3892. if (down_interruptible(&ctrl_info->sync_request_sem))
  3893. return -ERESTARTSYS;
  3894. } else {
  3895. down(&ctrl_info->sync_request_sem);
  3896. }
  3897. pqi_ctrl_busy(ctrl_info);
  3898. /*
  3899. * Wait for other admin queue updates such as;
  3900. * config table changes, OFA memory updates, ...
  3901. */
  3902. if (pqi_is_blockable_request(request))
  3903. pqi_wait_if_ctrl_blocked(ctrl_info);
  3904. if (pqi_ctrl_offline(ctrl_info)) {
  3905. rc = -ENXIO;
  3906. goto out;
  3907. }
  3908. io_request = pqi_alloc_io_request(ctrl_info, NULL);
  3909. put_unaligned_le16(io_request->index,
  3910. &(((struct pqi_raid_path_request *)request)->request_id));
  3911. if (request->iu_type == PQI_REQUEST_IU_RAID_PATH_IO)
  3912. ((struct pqi_raid_path_request *)request)->error_index =
  3913. ((struct pqi_raid_path_request *)request)->request_id;
  3914. iu_length = get_unaligned_le16(&request->iu_length) +
  3915. PQI_REQUEST_HEADER_LENGTH;
  3916. memcpy(io_request->iu, request, iu_length);
  3917. io_request->io_complete_callback = pqi_raid_synchronous_complete;
  3918. io_request->context = &wait;
  3919. pqi_start_io(ctrl_info, &ctrl_info->queue_groups[PQI_DEFAULT_QUEUE_GROUP], RAID_PATH,
  3920. io_request);
  3921. pqi_wait_for_completion_io(ctrl_info, &wait);
  3922. if (error_info) {
  3923. if (io_request->error_info)
  3924. memcpy(error_info, io_request->error_info, sizeof(*error_info));
  3925. else
  3926. memset(error_info, 0, sizeof(*error_info));
  3927. } else if (rc == 0 && io_request->error_info) {
  3928. rc = pqi_process_raid_io_error_synchronous(io_request->error_info);
  3929. }
  3930. pqi_free_io_request(io_request);
  3931. out:
  3932. pqi_ctrl_unbusy(ctrl_info);
  3933. up(&ctrl_info->sync_request_sem);
  3934. return rc;
  3935. }
  3936. static int pqi_validate_admin_response(
  3937. struct pqi_general_admin_response *response, u8 expected_function_code)
  3938. {
  3939. if (response->header.iu_type != PQI_RESPONSE_IU_GENERAL_ADMIN)
  3940. return -EINVAL;
  3941. if (get_unaligned_le16(&response->header.iu_length) !=
  3942. PQI_GENERAL_ADMIN_IU_LENGTH)
  3943. return -EINVAL;
  3944. if (response->function_code != expected_function_code)
  3945. return -EINVAL;
  3946. if (response->status != PQI_GENERAL_ADMIN_STATUS_SUCCESS)
  3947. return -EINVAL;
  3948. return 0;
  3949. }
  3950. static int pqi_submit_admin_request_synchronous(
  3951. struct pqi_ctrl_info *ctrl_info,
  3952. struct pqi_general_admin_request *request,
  3953. struct pqi_general_admin_response *response)
  3954. {
  3955. int rc;
  3956. pqi_submit_admin_request(ctrl_info, request);
  3957. rc = pqi_poll_for_admin_response(ctrl_info, response);
  3958. if (rc == 0)
  3959. rc = pqi_validate_admin_response(response, request->function_code);
  3960. return rc;
  3961. }
  3962. static int pqi_report_device_capability(struct pqi_ctrl_info *ctrl_info)
  3963. {
  3964. int rc;
  3965. struct pqi_general_admin_request request;
  3966. struct pqi_general_admin_response response;
  3967. struct pqi_device_capability *capability;
  3968. struct pqi_iu_layer_descriptor *sop_iu_layer_descriptor;
  3969. capability = kmalloc(sizeof(*capability), GFP_KERNEL);
  3970. if (!capability)
  3971. return -ENOMEM;
  3972. memset(&request, 0, sizeof(request));
  3973. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  3974. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  3975. &request.header.iu_length);
  3976. request.function_code =
  3977. PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY;
  3978. put_unaligned_le32(sizeof(*capability),
  3979. &request.data.report_device_capability.buffer_length);
  3980. rc = pqi_map_single(ctrl_info->pci_dev,
  3981. &request.data.report_device_capability.sg_descriptor,
  3982. capability, sizeof(*capability),
  3983. DMA_FROM_DEVICE);
  3984. if (rc)
  3985. goto out;
  3986. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request, &response);
  3987. pqi_pci_unmap(ctrl_info->pci_dev,
  3988. &request.data.report_device_capability.sg_descriptor, 1,
  3989. DMA_FROM_DEVICE);
  3990. if (rc)
  3991. goto out;
  3992. if (response.status != PQI_GENERAL_ADMIN_STATUS_SUCCESS) {
  3993. rc = -EIO;
  3994. goto out;
  3995. }
  3996. ctrl_info->max_inbound_queues =
  3997. get_unaligned_le16(&capability->max_inbound_queues);
  3998. ctrl_info->max_elements_per_iq =
  3999. get_unaligned_le16(&capability->max_elements_per_iq);
  4000. ctrl_info->max_iq_element_length =
  4001. get_unaligned_le16(&capability->max_iq_element_length)
  4002. * 16;
  4003. ctrl_info->max_outbound_queues =
  4004. get_unaligned_le16(&capability->max_outbound_queues);
  4005. ctrl_info->max_elements_per_oq =
  4006. get_unaligned_le16(&capability->max_elements_per_oq);
  4007. ctrl_info->max_oq_element_length =
  4008. get_unaligned_le16(&capability->max_oq_element_length)
  4009. * 16;
  4010. sop_iu_layer_descriptor =
  4011. &capability->iu_layer_descriptors[PQI_PROTOCOL_SOP];
  4012. ctrl_info->max_inbound_iu_length_per_firmware =
  4013. get_unaligned_le16(
  4014. &sop_iu_layer_descriptor->max_inbound_iu_length);
  4015. ctrl_info->inbound_spanning_supported =
  4016. sop_iu_layer_descriptor->inbound_spanning_supported;
  4017. ctrl_info->outbound_spanning_supported =
  4018. sop_iu_layer_descriptor->outbound_spanning_supported;
  4019. out:
  4020. kfree(capability);
  4021. return rc;
  4022. }
  4023. static int pqi_validate_device_capability(struct pqi_ctrl_info *ctrl_info)
  4024. {
  4025. if (ctrl_info->max_iq_element_length <
  4026. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH) {
  4027. dev_err(&ctrl_info->pci_dev->dev,
  4028. "max. inbound queue element length of %d is less than the required length of %d\n",
  4029. ctrl_info->max_iq_element_length,
  4030. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  4031. return -EINVAL;
  4032. }
  4033. if (ctrl_info->max_oq_element_length <
  4034. PQI_OPERATIONAL_OQ_ELEMENT_LENGTH) {
  4035. dev_err(&ctrl_info->pci_dev->dev,
  4036. "max. outbound queue element length of %d is less than the required length of %d\n",
  4037. ctrl_info->max_oq_element_length,
  4038. PQI_OPERATIONAL_OQ_ELEMENT_LENGTH);
  4039. return -EINVAL;
  4040. }
  4041. if (ctrl_info->max_inbound_iu_length_per_firmware <
  4042. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH) {
  4043. dev_err(&ctrl_info->pci_dev->dev,
  4044. "max. inbound IU length of %u is less than the min. required length of %d\n",
  4045. ctrl_info->max_inbound_iu_length_per_firmware,
  4046. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  4047. return -EINVAL;
  4048. }
  4049. if (!ctrl_info->inbound_spanning_supported) {
  4050. dev_err(&ctrl_info->pci_dev->dev,
  4051. "the controller does not support inbound spanning\n");
  4052. return -EINVAL;
  4053. }
  4054. if (ctrl_info->outbound_spanning_supported) {
  4055. dev_err(&ctrl_info->pci_dev->dev,
  4056. "the controller supports outbound spanning but this driver does not\n");
  4057. return -EINVAL;
  4058. }
  4059. return 0;
  4060. }
  4061. static int pqi_create_event_queue(struct pqi_ctrl_info *ctrl_info)
  4062. {
  4063. int rc;
  4064. struct pqi_event_queue *event_queue;
  4065. struct pqi_general_admin_request request;
  4066. struct pqi_general_admin_response response;
  4067. event_queue = &ctrl_info->event_queue;
  4068. /*
  4069. * Create OQ (Outbound Queue - device to host queue) to dedicate
  4070. * to events.
  4071. */
  4072. memset(&request, 0, sizeof(request));
  4073. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  4074. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  4075. &request.header.iu_length);
  4076. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ;
  4077. put_unaligned_le16(event_queue->oq_id,
  4078. &request.data.create_operational_oq.queue_id);
  4079. put_unaligned_le64((u64)event_queue->oq_element_array_bus_addr,
  4080. &request.data.create_operational_oq.element_array_addr);
  4081. put_unaligned_le64((u64)event_queue->oq_pi_bus_addr,
  4082. &request.data.create_operational_oq.pi_addr);
  4083. put_unaligned_le16(PQI_NUM_EVENT_QUEUE_ELEMENTS,
  4084. &request.data.create_operational_oq.num_elements);
  4085. put_unaligned_le16(PQI_EVENT_OQ_ELEMENT_LENGTH / 16,
  4086. &request.data.create_operational_oq.element_length);
  4087. request.data.create_operational_oq.queue_protocol = PQI_PROTOCOL_SOP;
  4088. put_unaligned_le16(event_queue->int_msg_num,
  4089. &request.data.create_operational_oq.int_msg_num);
  4090. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  4091. &response);
  4092. if (rc)
  4093. return rc;
  4094. event_queue->oq_ci = ctrl_info->iomem_base +
  4095. PQI_DEVICE_REGISTERS_OFFSET +
  4096. get_unaligned_le64(
  4097. &response.data.create_operational_oq.oq_ci_offset);
  4098. return 0;
  4099. }
  4100. static int pqi_create_queue_group(struct pqi_ctrl_info *ctrl_info,
  4101. unsigned int group_number)
  4102. {
  4103. int rc;
  4104. struct pqi_queue_group *queue_group;
  4105. struct pqi_general_admin_request request;
  4106. struct pqi_general_admin_response response;
  4107. queue_group = &ctrl_info->queue_groups[group_number];
  4108. /*
  4109. * Create IQ (Inbound Queue - host to device queue) for
  4110. * RAID path.
  4111. */
  4112. memset(&request, 0, sizeof(request));
  4113. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  4114. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  4115. &request.header.iu_length);
  4116. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ;
  4117. put_unaligned_le16(queue_group->iq_id[RAID_PATH],
  4118. &request.data.create_operational_iq.queue_id);
  4119. put_unaligned_le64(
  4120. (u64)queue_group->iq_element_array_bus_addr[RAID_PATH],
  4121. &request.data.create_operational_iq.element_array_addr);
  4122. put_unaligned_le64((u64)queue_group->iq_ci_bus_addr[RAID_PATH],
  4123. &request.data.create_operational_iq.ci_addr);
  4124. put_unaligned_le16(ctrl_info->num_elements_per_iq,
  4125. &request.data.create_operational_iq.num_elements);
  4126. put_unaligned_le16(PQI_OPERATIONAL_IQ_ELEMENT_LENGTH / 16,
  4127. &request.data.create_operational_iq.element_length);
  4128. request.data.create_operational_iq.queue_protocol = PQI_PROTOCOL_SOP;
  4129. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  4130. &response);
  4131. if (rc) {
  4132. dev_err(&ctrl_info->pci_dev->dev,
  4133. "error creating inbound RAID queue\n");
  4134. return rc;
  4135. }
  4136. queue_group->iq_pi[RAID_PATH] = ctrl_info->iomem_base +
  4137. PQI_DEVICE_REGISTERS_OFFSET +
  4138. get_unaligned_le64(
  4139. &response.data.create_operational_iq.iq_pi_offset);
  4140. /*
  4141. * Create IQ (Inbound Queue - host to device queue) for
  4142. * Advanced I/O (AIO) path.
  4143. */
  4144. memset(&request, 0, sizeof(request));
  4145. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  4146. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  4147. &request.header.iu_length);
  4148. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ;
  4149. put_unaligned_le16(queue_group->iq_id[AIO_PATH],
  4150. &request.data.create_operational_iq.queue_id);
  4151. put_unaligned_le64((u64)queue_group->
  4152. iq_element_array_bus_addr[AIO_PATH],
  4153. &request.data.create_operational_iq.element_array_addr);
  4154. put_unaligned_le64((u64)queue_group->iq_ci_bus_addr[AIO_PATH],
  4155. &request.data.create_operational_iq.ci_addr);
  4156. put_unaligned_le16(ctrl_info->num_elements_per_iq,
  4157. &request.data.create_operational_iq.num_elements);
  4158. put_unaligned_le16(PQI_OPERATIONAL_IQ_ELEMENT_LENGTH / 16,
  4159. &request.data.create_operational_iq.element_length);
  4160. request.data.create_operational_iq.queue_protocol = PQI_PROTOCOL_SOP;
  4161. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  4162. &response);
  4163. if (rc) {
  4164. dev_err(&ctrl_info->pci_dev->dev,
  4165. "error creating inbound AIO queue\n");
  4166. return rc;
  4167. }
  4168. queue_group->iq_pi[AIO_PATH] = ctrl_info->iomem_base +
  4169. PQI_DEVICE_REGISTERS_OFFSET +
  4170. get_unaligned_le64(
  4171. &response.data.create_operational_iq.iq_pi_offset);
  4172. /*
  4173. * Designate the 2nd IQ as the AIO path. By default, all IQs are
  4174. * assumed to be for RAID path I/O unless we change the queue's
  4175. * property.
  4176. */
  4177. memset(&request, 0, sizeof(request));
  4178. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  4179. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  4180. &request.header.iu_length);
  4181. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CHANGE_IQ_PROPERTY;
  4182. put_unaligned_le16(queue_group->iq_id[AIO_PATH],
  4183. &request.data.change_operational_iq_properties.queue_id);
  4184. put_unaligned_le32(PQI_IQ_PROPERTY_IS_AIO_QUEUE,
  4185. &request.data.change_operational_iq_properties.vendor_specific);
  4186. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  4187. &response);
  4188. if (rc) {
  4189. dev_err(&ctrl_info->pci_dev->dev,
  4190. "error changing queue property\n");
  4191. return rc;
  4192. }
  4193. /*
  4194. * Create OQ (Outbound Queue - device to host queue).
  4195. */
  4196. memset(&request, 0, sizeof(request));
  4197. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  4198. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  4199. &request.header.iu_length);
  4200. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ;
  4201. put_unaligned_le16(queue_group->oq_id,
  4202. &request.data.create_operational_oq.queue_id);
  4203. put_unaligned_le64((u64)queue_group->oq_element_array_bus_addr,
  4204. &request.data.create_operational_oq.element_array_addr);
  4205. put_unaligned_le64((u64)queue_group->oq_pi_bus_addr,
  4206. &request.data.create_operational_oq.pi_addr);
  4207. put_unaligned_le16(ctrl_info->num_elements_per_oq,
  4208. &request.data.create_operational_oq.num_elements);
  4209. put_unaligned_le16(PQI_OPERATIONAL_OQ_ELEMENT_LENGTH / 16,
  4210. &request.data.create_operational_oq.element_length);
  4211. request.data.create_operational_oq.queue_protocol = PQI_PROTOCOL_SOP;
  4212. put_unaligned_le16(queue_group->int_msg_num,
  4213. &request.data.create_operational_oq.int_msg_num);
  4214. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  4215. &response);
  4216. if (rc) {
  4217. dev_err(&ctrl_info->pci_dev->dev,
  4218. "error creating outbound queue\n");
  4219. return rc;
  4220. }
  4221. queue_group->oq_ci = ctrl_info->iomem_base +
  4222. PQI_DEVICE_REGISTERS_OFFSET +
  4223. get_unaligned_le64(
  4224. &response.data.create_operational_oq.oq_ci_offset);
  4225. return 0;
  4226. }
  4227. static int pqi_create_queues(struct pqi_ctrl_info *ctrl_info)
  4228. {
  4229. int rc;
  4230. unsigned int i;
  4231. rc = pqi_create_event_queue(ctrl_info);
  4232. if (rc) {
  4233. dev_err(&ctrl_info->pci_dev->dev,
  4234. "error creating event queue\n");
  4235. return rc;
  4236. }
  4237. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  4238. rc = pqi_create_queue_group(ctrl_info, i);
  4239. if (rc) {
  4240. dev_err(&ctrl_info->pci_dev->dev,
  4241. "error creating queue group number %u/%u\n",
  4242. i, ctrl_info->num_queue_groups);
  4243. return rc;
  4244. }
  4245. }
  4246. return 0;
  4247. }
  4248. #define PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH \
  4249. struct_size_t(struct pqi_event_config, descriptors, PQI_MAX_EVENT_DESCRIPTORS)
  4250. static int pqi_configure_events(struct pqi_ctrl_info *ctrl_info,
  4251. bool enable_events)
  4252. {
  4253. int rc;
  4254. unsigned int i;
  4255. struct pqi_event_config *event_config;
  4256. struct pqi_event_descriptor *event_descriptor;
  4257. struct pqi_general_management_request request;
  4258. event_config = kmalloc(PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  4259. GFP_KERNEL);
  4260. if (!event_config)
  4261. return -ENOMEM;
  4262. memset(&request, 0, sizeof(request));
  4263. request.header.iu_type = PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG;
  4264. put_unaligned_le16(offsetof(struct pqi_general_management_request,
  4265. data.report_event_configuration.sg_descriptors[1]) -
  4266. PQI_REQUEST_HEADER_LENGTH, &request.header.iu_length);
  4267. put_unaligned_le32(PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  4268. &request.data.report_event_configuration.buffer_length);
  4269. rc = pqi_map_single(ctrl_info->pci_dev,
  4270. request.data.report_event_configuration.sg_descriptors,
  4271. event_config, PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  4272. DMA_FROM_DEVICE);
  4273. if (rc)
  4274. goto out;
  4275. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, NULL);
  4276. pqi_pci_unmap(ctrl_info->pci_dev,
  4277. request.data.report_event_configuration.sg_descriptors, 1,
  4278. DMA_FROM_DEVICE);
  4279. if (rc)
  4280. goto out;
  4281. for (i = 0; i < event_config->num_event_descriptors; i++) {
  4282. event_descriptor = &event_config->descriptors[i];
  4283. if (enable_events &&
  4284. pqi_is_supported_event(event_descriptor->event_type))
  4285. put_unaligned_le16(ctrl_info->event_queue.oq_id,
  4286. &event_descriptor->oq_id);
  4287. else
  4288. put_unaligned_le16(0, &event_descriptor->oq_id);
  4289. }
  4290. memset(&request, 0, sizeof(request));
  4291. request.header.iu_type = PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG;
  4292. put_unaligned_le16(offsetof(struct pqi_general_management_request,
  4293. data.report_event_configuration.sg_descriptors[1]) -
  4294. PQI_REQUEST_HEADER_LENGTH, &request.header.iu_length);
  4295. put_unaligned_le32(PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  4296. &request.data.report_event_configuration.buffer_length);
  4297. rc = pqi_map_single(ctrl_info->pci_dev,
  4298. request.data.report_event_configuration.sg_descriptors,
  4299. event_config, PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  4300. DMA_TO_DEVICE);
  4301. if (rc)
  4302. goto out;
  4303. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, NULL);
  4304. pqi_pci_unmap(ctrl_info->pci_dev,
  4305. request.data.report_event_configuration.sg_descriptors, 1,
  4306. DMA_TO_DEVICE);
  4307. out:
  4308. kfree(event_config);
  4309. return rc;
  4310. }
  4311. static inline int pqi_enable_events(struct pqi_ctrl_info *ctrl_info)
  4312. {
  4313. return pqi_configure_events(ctrl_info, true);
  4314. }
  4315. static void pqi_free_all_io_requests(struct pqi_ctrl_info *ctrl_info)
  4316. {
  4317. unsigned int i;
  4318. struct device *dev;
  4319. size_t sg_chain_buffer_length;
  4320. struct pqi_io_request *io_request;
  4321. if (!ctrl_info->io_request_pool)
  4322. return;
  4323. dev = &ctrl_info->pci_dev->dev;
  4324. sg_chain_buffer_length = ctrl_info->sg_chain_buffer_length;
  4325. io_request = ctrl_info->io_request_pool;
  4326. for (i = 0; i < ctrl_info->max_io_slots; i++) {
  4327. kfree(io_request->iu);
  4328. if (!io_request->sg_chain_buffer)
  4329. break;
  4330. dma_free_coherent(dev, sg_chain_buffer_length,
  4331. io_request->sg_chain_buffer,
  4332. io_request->sg_chain_buffer_dma_handle);
  4333. io_request++;
  4334. }
  4335. kfree(ctrl_info->io_request_pool);
  4336. ctrl_info->io_request_pool = NULL;
  4337. }
  4338. static inline int pqi_alloc_error_buffer(struct pqi_ctrl_info *ctrl_info)
  4339. {
  4340. ctrl_info->error_buffer = dma_alloc_coherent(&ctrl_info->pci_dev->dev,
  4341. ctrl_info->error_buffer_length,
  4342. &ctrl_info->error_buffer_dma_handle,
  4343. GFP_KERNEL);
  4344. if (!ctrl_info->error_buffer)
  4345. return -ENOMEM;
  4346. return 0;
  4347. }
  4348. static int pqi_alloc_io_resources(struct pqi_ctrl_info *ctrl_info)
  4349. {
  4350. unsigned int i;
  4351. void *sg_chain_buffer;
  4352. size_t sg_chain_buffer_length;
  4353. dma_addr_t sg_chain_buffer_dma_handle;
  4354. struct device *dev;
  4355. struct pqi_io_request *io_request;
  4356. ctrl_info->io_request_pool = kcalloc(ctrl_info->max_io_slots,
  4357. sizeof(ctrl_info->io_request_pool[0]), GFP_KERNEL);
  4358. if (!ctrl_info->io_request_pool) {
  4359. dev_err(&ctrl_info->pci_dev->dev,
  4360. "failed to allocate I/O request pool\n");
  4361. goto error;
  4362. }
  4363. dev = &ctrl_info->pci_dev->dev;
  4364. sg_chain_buffer_length = ctrl_info->sg_chain_buffer_length;
  4365. io_request = ctrl_info->io_request_pool;
  4366. for (i = 0; i < ctrl_info->max_io_slots; i++) {
  4367. io_request->iu = kmalloc(ctrl_info->max_inbound_iu_length, GFP_KERNEL);
  4368. if (!io_request->iu) {
  4369. dev_err(&ctrl_info->pci_dev->dev,
  4370. "failed to allocate IU buffers\n");
  4371. goto error;
  4372. }
  4373. sg_chain_buffer = dma_alloc_coherent(dev,
  4374. sg_chain_buffer_length, &sg_chain_buffer_dma_handle,
  4375. GFP_KERNEL);
  4376. if (!sg_chain_buffer) {
  4377. dev_err(&ctrl_info->pci_dev->dev,
  4378. "failed to allocate PQI scatter-gather chain buffers\n");
  4379. goto error;
  4380. }
  4381. io_request->index = i;
  4382. io_request->sg_chain_buffer = sg_chain_buffer;
  4383. io_request->sg_chain_buffer_dma_handle = sg_chain_buffer_dma_handle;
  4384. io_request++;
  4385. }
  4386. return 0;
  4387. error:
  4388. pqi_free_all_io_requests(ctrl_info);
  4389. return -ENOMEM;
  4390. }
  4391. /*
  4392. * Calculate required resources that are sized based on max. outstanding
  4393. * requests and max. transfer size.
  4394. */
  4395. static void pqi_calculate_io_resources(struct pqi_ctrl_info *ctrl_info)
  4396. {
  4397. u32 max_transfer_size;
  4398. u32 max_sg_entries;
  4399. ctrl_info->scsi_ml_can_queue =
  4400. ctrl_info->max_outstanding_requests - PQI_RESERVED_IO_SLOTS;
  4401. ctrl_info->max_io_slots = ctrl_info->max_outstanding_requests;
  4402. ctrl_info->error_buffer_length =
  4403. ctrl_info->max_io_slots * PQI_ERROR_BUFFER_ELEMENT_LENGTH;
  4404. if (reset_devices)
  4405. max_transfer_size = min(ctrl_info->max_transfer_size,
  4406. PQI_MAX_TRANSFER_SIZE_KDUMP);
  4407. else
  4408. max_transfer_size = min(ctrl_info->max_transfer_size,
  4409. PQI_MAX_TRANSFER_SIZE);
  4410. max_sg_entries = max_transfer_size / PAGE_SIZE;
  4411. /* +1 to cover when the buffer is not page-aligned. */
  4412. max_sg_entries++;
  4413. max_sg_entries = min(ctrl_info->max_sg_entries, max_sg_entries);
  4414. max_transfer_size = (max_sg_entries - 1) * PAGE_SIZE;
  4415. ctrl_info->sg_chain_buffer_length =
  4416. (max_sg_entries * sizeof(struct pqi_sg_descriptor)) +
  4417. PQI_EXTRA_SGL_MEMORY;
  4418. ctrl_info->sg_tablesize = max_sg_entries;
  4419. ctrl_info->max_sectors = max_transfer_size / 512;
  4420. }
  4421. static void pqi_calculate_queue_resources(struct pqi_ctrl_info *ctrl_info)
  4422. {
  4423. int num_queue_groups;
  4424. u16 num_elements_per_iq;
  4425. u16 num_elements_per_oq;
  4426. if (reset_devices) {
  4427. num_queue_groups = 1;
  4428. } else {
  4429. int num_cpus;
  4430. int max_queue_groups;
  4431. max_queue_groups = min(ctrl_info->max_inbound_queues / 2,
  4432. ctrl_info->max_outbound_queues - 1);
  4433. max_queue_groups = min(max_queue_groups, PQI_MAX_QUEUE_GROUPS);
  4434. num_cpus = num_online_cpus();
  4435. num_queue_groups = min(num_cpus, ctrl_info->max_msix_vectors);
  4436. num_queue_groups = min(num_queue_groups, max_queue_groups);
  4437. }
  4438. ctrl_info->num_queue_groups = num_queue_groups;
  4439. /*
  4440. * Make sure that the max. inbound IU length is an even multiple
  4441. * of our inbound element length.
  4442. */
  4443. ctrl_info->max_inbound_iu_length =
  4444. (ctrl_info->max_inbound_iu_length_per_firmware /
  4445. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH) *
  4446. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH;
  4447. num_elements_per_iq =
  4448. (ctrl_info->max_inbound_iu_length /
  4449. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  4450. /* Add one because one element in each queue is unusable. */
  4451. num_elements_per_iq++;
  4452. num_elements_per_iq = min(num_elements_per_iq,
  4453. ctrl_info->max_elements_per_iq);
  4454. num_elements_per_oq = ((num_elements_per_iq - 1) * 2) + 1;
  4455. num_elements_per_oq = min(num_elements_per_oq,
  4456. ctrl_info->max_elements_per_oq);
  4457. ctrl_info->num_elements_per_iq = num_elements_per_iq;
  4458. ctrl_info->num_elements_per_oq = num_elements_per_oq;
  4459. ctrl_info->max_sg_per_iu =
  4460. ((ctrl_info->max_inbound_iu_length -
  4461. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH) /
  4462. sizeof(struct pqi_sg_descriptor)) +
  4463. PQI_MAX_EMBEDDED_SG_DESCRIPTORS;
  4464. ctrl_info->max_sg_per_r56_iu =
  4465. ((ctrl_info->max_inbound_iu_length -
  4466. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH) /
  4467. sizeof(struct pqi_sg_descriptor)) +
  4468. PQI_MAX_EMBEDDED_R56_SG_DESCRIPTORS;
  4469. }
  4470. static inline void pqi_set_sg_descriptor(struct pqi_sg_descriptor *sg_descriptor,
  4471. struct scatterlist *sg)
  4472. {
  4473. u64 address = (u64)sg_dma_address(sg);
  4474. unsigned int length = sg_dma_len(sg);
  4475. put_unaligned_le64(address, &sg_descriptor->address);
  4476. put_unaligned_le32(length, &sg_descriptor->length);
  4477. put_unaligned_le32(0, &sg_descriptor->flags);
  4478. }
  4479. static unsigned int pqi_build_sg_list(struct pqi_sg_descriptor *sg_descriptor,
  4480. struct scatterlist *sg, int sg_count, struct pqi_io_request *io_request,
  4481. int max_sg_per_iu, bool *chained)
  4482. {
  4483. int i;
  4484. unsigned int num_sg_in_iu;
  4485. *chained = false;
  4486. i = 0;
  4487. num_sg_in_iu = 0;
  4488. max_sg_per_iu--; /* Subtract 1 to leave room for chain marker. */
  4489. while (1) {
  4490. pqi_set_sg_descriptor(sg_descriptor, sg);
  4491. if (!*chained)
  4492. num_sg_in_iu++;
  4493. i++;
  4494. if (i == sg_count)
  4495. break;
  4496. sg_descriptor++;
  4497. if (i == max_sg_per_iu) {
  4498. put_unaligned_le64((u64)io_request->sg_chain_buffer_dma_handle,
  4499. &sg_descriptor->address);
  4500. put_unaligned_le32((sg_count - num_sg_in_iu) * sizeof(*sg_descriptor),
  4501. &sg_descriptor->length);
  4502. put_unaligned_le32(CISS_SG_CHAIN, &sg_descriptor->flags);
  4503. *chained = true;
  4504. num_sg_in_iu++;
  4505. sg_descriptor = io_request->sg_chain_buffer;
  4506. }
  4507. sg = sg_next(sg);
  4508. }
  4509. put_unaligned_le32(CISS_SG_LAST, &sg_descriptor->flags);
  4510. return num_sg_in_iu;
  4511. }
  4512. static int pqi_build_raid_sg_list(struct pqi_ctrl_info *ctrl_info,
  4513. struct pqi_raid_path_request *request, struct scsi_cmnd *scmd,
  4514. struct pqi_io_request *io_request)
  4515. {
  4516. u16 iu_length;
  4517. int sg_count;
  4518. bool chained;
  4519. unsigned int num_sg_in_iu;
  4520. struct scatterlist *sg;
  4521. struct pqi_sg_descriptor *sg_descriptor;
  4522. sg_count = scsi_dma_map(scmd);
  4523. if (sg_count < 0)
  4524. return sg_count;
  4525. iu_length = offsetof(struct pqi_raid_path_request, sg_descriptors) -
  4526. PQI_REQUEST_HEADER_LENGTH;
  4527. if (sg_count == 0)
  4528. goto out;
  4529. sg = scsi_sglist(scmd);
  4530. sg_descriptor = request->sg_descriptors;
  4531. num_sg_in_iu = pqi_build_sg_list(sg_descriptor, sg, sg_count, io_request,
  4532. ctrl_info->max_sg_per_iu, &chained);
  4533. request->partial = chained;
  4534. iu_length += num_sg_in_iu * sizeof(*sg_descriptor);
  4535. out:
  4536. put_unaligned_le16(iu_length, &request->header.iu_length);
  4537. return 0;
  4538. }
  4539. static int pqi_build_aio_r1_sg_list(struct pqi_ctrl_info *ctrl_info,
  4540. struct pqi_aio_r1_path_request *request, struct scsi_cmnd *scmd,
  4541. struct pqi_io_request *io_request)
  4542. {
  4543. u16 iu_length;
  4544. int sg_count;
  4545. bool chained;
  4546. unsigned int num_sg_in_iu;
  4547. struct scatterlist *sg;
  4548. struct pqi_sg_descriptor *sg_descriptor;
  4549. sg_count = scsi_dma_map(scmd);
  4550. if (sg_count < 0)
  4551. return sg_count;
  4552. iu_length = offsetof(struct pqi_aio_r1_path_request, sg_descriptors) -
  4553. PQI_REQUEST_HEADER_LENGTH;
  4554. num_sg_in_iu = 0;
  4555. if (sg_count == 0)
  4556. goto out;
  4557. sg = scsi_sglist(scmd);
  4558. sg_descriptor = request->sg_descriptors;
  4559. num_sg_in_iu = pqi_build_sg_list(sg_descriptor, sg, sg_count, io_request,
  4560. ctrl_info->max_sg_per_iu, &chained);
  4561. request->partial = chained;
  4562. iu_length += num_sg_in_iu * sizeof(*sg_descriptor);
  4563. out:
  4564. put_unaligned_le16(iu_length, &request->header.iu_length);
  4565. request->num_sg_descriptors = num_sg_in_iu;
  4566. return 0;
  4567. }
  4568. static int pqi_build_aio_r56_sg_list(struct pqi_ctrl_info *ctrl_info,
  4569. struct pqi_aio_r56_path_request *request, struct scsi_cmnd *scmd,
  4570. struct pqi_io_request *io_request)
  4571. {
  4572. u16 iu_length;
  4573. int sg_count;
  4574. bool chained;
  4575. unsigned int num_sg_in_iu;
  4576. struct scatterlist *sg;
  4577. struct pqi_sg_descriptor *sg_descriptor;
  4578. sg_count = scsi_dma_map(scmd);
  4579. if (sg_count < 0)
  4580. return sg_count;
  4581. iu_length = offsetof(struct pqi_aio_r56_path_request, sg_descriptors) -
  4582. PQI_REQUEST_HEADER_LENGTH;
  4583. num_sg_in_iu = 0;
  4584. if (sg_count != 0) {
  4585. sg = scsi_sglist(scmd);
  4586. sg_descriptor = request->sg_descriptors;
  4587. num_sg_in_iu = pqi_build_sg_list(sg_descriptor, sg, sg_count, io_request,
  4588. ctrl_info->max_sg_per_r56_iu, &chained);
  4589. request->partial = chained;
  4590. iu_length += num_sg_in_iu * sizeof(*sg_descriptor);
  4591. }
  4592. put_unaligned_le16(iu_length, &request->header.iu_length);
  4593. request->num_sg_descriptors = num_sg_in_iu;
  4594. return 0;
  4595. }
  4596. static int pqi_build_aio_sg_list(struct pqi_ctrl_info *ctrl_info,
  4597. struct pqi_aio_path_request *request, struct scsi_cmnd *scmd,
  4598. struct pqi_io_request *io_request)
  4599. {
  4600. u16 iu_length;
  4601. int sg_count;
  4602. bool chained;
  4603. unsigned int num_sg_in_iu;
  4604. struct scatterlist *sg;
  4605. struct pqi_sg_descriptor *sg_descriptor;
  4606. sg_count = scsi_dma_map(scmd);
  4607. if (sg_count < 0)
  4608. return sg_count;
  4609. iu_length = offsetof(struct pqi_aio_path_request, sg_descriptors) -
  4610. PQI_REQUEST_HEADER_LENGTH;
  4611. num_sg_in_iu = 0;
  4612. if (sg_count == 0)
  4613. goto out;
  4614. sg = scsi_sglist(scmd);
  4615. sg_descriptor = request->sg_descriptors;
  4616. num_sg_in_iu = pqi_build_sg_list(sg_descriptor, sg, sg_count, io_request,
  4617. ctrl_info->max_sg_per_iu, &chained);
  4618. request->partial = chained;
  4619. iu_length += num_sg_in_iu * sizeof(*sg_descriptor);
  4620. out:
  4621. put_unaligned_le16(iu_length, &request->header.iu_length);
  4622. request->num_sg_descriptors = num_sg_in_iu;
  4623. return 0;
  4624. }
  4625. static void pqi_raid_io_complete(struct pqi_io_request *io_request,
  4626. void *context)
  4627. {
  4628. struct scsi_cmnd *scmd;
  4629. scmd = io_request->scmd;
  4630. pqi_free_io_request(io_request);
  4631. scsi_dma_unmap(scmd);
  4632. pqi_scsi_done(scmd);
  4633. }
  4634. static int pqi_raid_submit_io(struct pqi_ctrl_info *ctrl_info,
  4635. struct pqi_scsi_dev *device, struct scsi_cmnd *scmd,
  4636. struct pqi_queue_group *queue_group, bool io_high_prio)
  4637. {
  4638. int rc;
  4639. size_t cdb_length;
  4640. struct pqi_io_request *io_request;
  4641. struct pqi_raid_path_request *request;
  4642. io_request = pqi_alloc_io_request(ctrl_info, scmd);
  4643. if (!io_request)
  4644. return SCSI_MLQUEUE_HOST_BUSY;
  4645. io_request->io_complete_callback = pqi_raid_io_complete;
  4646. io_request->scmd = scmd;
  4647. request = io_request->iu;
  4648. memset(request, 0, offsetof(struct pqi_raid_path_request, sg_descriptors));
  4649. request->header.iu_type = PQI_REQUEST_IU_RAID_PATH_IO;
  4650. put_unaligned_le32(scsi_bufflen(scmd), &request->buffer_length);
  4651. request->task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  4652. request->command_priority = io_high_prio;
  4653. put_unaligned_le16(io_request->index, &request->request_id);
  4654. request->error_index = request->request_id;
  4655. memcpy(request->lun_number, device->scsi3addr, sizeof(request->lun_number));
  4656. request->ml_device_lun_number = (u8)scmd->device->lun;
  4657. cdb_length = min_t(size_t, scmd->cmd_len, sizeof(request->cdb));
  4658. memcpy(request->cdb, scmd->cmnd, cdb_length);
  4659. switch (cdb_length) {
  4660. case 6:
  4661. case 10:
  4662. case 12:
  4663. case 16:
  4664. request->additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_0;
  4665. break;
  4666. case 20:
  4667. request->additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_4;
  4668. break;
  4669. case 24:
  4670. request->additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_8;
  4671. break;
  4672. case 28:
  4673. request->additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_12;
  4674. break;
  4675. case 32:
  4676. default:
  4677. request->additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_16;
  4678. break;
  4679. }
  4680. switch (scmd->sc_data_direction) {
  4681. case DMA_FROM_DEVICE:
  4682. request->data_direction = SOP_READ_FLAG;
  4683. break;
  4684. case DMA_TO_DEVICE:
  4685. request->data_direction = SOP_WRITE_FLAG;
  4686. break;
  4687. case DMA_NONE:
  4688. request->data_direction = SOP_NO_DIRECTION_FLAG;
  4689. break;
  4690. case DMA_BIDIRECTIONAL:
  4691. request->data_direction = SOP_BIDIRECTIONAL;
  4692. break;
  4693. default:
  4694. dev_err(&ctrl_info->pci_dev->dev,
  4695. "unknown data direction: %d\n",
  4696. scmd->sc_data_direction);
  4697. break;
  4698. }
  4699. rc = pqi_build_raid_sg_list(ctrl_info, request, scmd, io_request);
  4700. if (rc) {
  4701. pqi_free_io_request(io_request);
  4702. return SCSI_MLQUEUE_HOST_BUSY;
  4703. }
  4704. pqi_start_io(ctrl_info, queue_group, RAID_PATH, io_request);
  4705. return 0;
  4706. }
  4707. static inline int pqi_raid_submit_scsi_cmd(struct pqi_ctrl_info *ctrl_info,
  4708. struct pqi_scsi_dev *device, struct scsi_cmnd *scmd,
  4709. struct pqi_queue_group *queue_group)
  4710. {
  4711. bool io_high_prio;
  4712. io_high_prio = pqi_is_io_high_priority(device, scmd);
  4713. return pqi_raid_submit_io(ctrl_info, device, scmd, queue_group, io_high_prio);
  4714. }
  4715. static bool pqi_raid_bypass_retry_needed(struct pqi_io_request *io_request)
  4716. {
  4717. struct scsi_cmnd *scmd;
  4718. struct pqi_scsi_dev *device;
  4719. struct pqi_ctrl_info *ctrl_info;
  4720. if (!io_request->raid_bypass)
  4721. return false;
  4722. scmd = io_request->scmd;
  4723. if ((scmd->result & 0xff) == SAM_STAT_GOOD)
  4724. return false;
  4725. if (host_byte(scmd->result) == DID_NO_CONNECT)
  4726. return false;
  4727. device = scmd->device->hostdata;
  4728. if (pqi_device_offline(device) || pqi_device_in_remove(device))
  4729. return false;
  4730. ctrl_info = shost_to_hba(scmd->device->host);
  4731. if (pqi_ctrl_offline(ctrl_info))
  4732. return false;
  4733. return true;
  4734. }
  4735. static void pqi_aio_io_complete(struct pqi_io_request *io_request,
  4736. void *context)
  4737. {
  4738. struct scsi_cmnd *scmd;
  4739. scmd = io_request->scmd;
  4740. scsi_dma_unmap(scmd);
  4741. if (io_request->status == -EAGAIN || pqi_raid_bypass_retry_needed(io_request)) {
  4742. set_host_byte(scmd, DID_IMM_RETRY);
  4743. pqi_cmd_priv(scmd)->this_residual++;
  4744. }
  4745. pqi_free_io_request(io_request);
  4746. pqi_scsi_done(scmd);
  4747. }
  4748. static inline int pqi_aio_submit_scsi_cmd(struct pqi_ctrl_info *ctrl_info,
  4749. struct pqi_scsi_dev *device, struct scsi_cmnd *scmd,
  4750. struct pqi_queue_group *queue_group)
  4751. {
  4752. bool io_high_prio;
  4753. io_high_prio = pqi_is_io_high_priority(device, scmd);
  4754. return pqi_aio_submit_io(ctrl_info, scmd, device->aio_handle,
  4755. scmd->cmnd, scmd->cmd_len, queue_group, NULL,
  4756. false, io_high_prio);
  4757. }
  4758. static int pqi_aio_submit_io(struct pqi_ctrl_info *ctrl_info,
  4759. struct scsi_cmnd *scmd, u32 aio_handle, u8 *cdb,
  4760. unsigned int cdb_length, struct pqi_queue_group *queue_group,
  4761. struct pqi_encryption_info *encryption_info, bool raid_bypass,
  4762. bool io_high_prio)
  4763. {
  4764. int rc;
  4765. struct pqi_io_request *io_request;
  4766. struct pqi_aio_path_request *request;
  4767. io_request = pqi_alloc_io_request(ctrl_info, scmd);
  4768. if (!io_request)
  4769. return SCSI_MLQUEUE_HOST_BUSY;
  4770. io_request->io_complete_callback = pqi_aio_io_complete;
  4771. io_request->scmd = scmd;
  4772. io_request->raid_bypass = raid_bypass;
  4773. request = io_request->iu;
  4774. memset(request, 0, offsetof(struct pqi_aio_path_request, sg_descriptors));
  4775. request->header.iu_type = PQI_REQUEST_IU_AIO_PATH_IO;
  4776. put_unaligned_le32(aio_handle, &request->nexus_id);
  4777. put_unaligned_le32(scsi_bufflen(scmd), &request->buffer_length);
  4778. request->task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  4779. request->command_priority = io_high_prio;
  4780. put_unaligned_le16(io_request->index, &request->request_id);
  4781. request->error_index = request->request_id;
  4782. if (!raid_bypass && ctrl_info->multi_lun_device_supported)
  4783. put_unaligned_le64(scmd->device->lun << 8, &request->lun_number);
  4784. if (cdb_length > sizeof(request->cdb))
  4785. cdb_length = sizeof(request->cdb);
  4786. request->cdb_length = cdb_length;
  4787. memcpy(request->cdb, cdb, cdb_length);
  4788. switch (scmd->sc_data_direction) {
  4789. case DMA_TO_DEVICE:
  4790. request->data_direction = SOP_READ_FLAG;
  4791. break;
  4792. case DMA_FROM_DEVICE:
  4793. request->data_direction = SOP_WRITE_FLAG;
  4794. break;
  4795. case DMA_NONE:
  4796. request->data_direction = SOP_NO_DIRECTION_FLAG;
  4797. break;
  4798. case DMA_BIDIRECTIONAL:
  4799. request->data_direction = SOP_BIDIRECTIONAL;
  4800. break;
  4801. default:
  4802. dev_err(&ctrl_info->pci_dev->dev,
  4803. "unknown data direction: %d\n",
  4804. scmd->sc_data_direction);
  4805. break;
  4806. }
  4807. if (encryption_info) {
  4808. request->encryption_enable = true;
  4809. put_unaligned_le16(encryption_info->data_encryption_key_index,
  4810. &request->data_encryption_key_index);
  4811. put_unaligned_le32(encryption_info->encrypt_tweak_lower,
  4812. &request->encrypt_tweak_lower);
  4813. put_unaligned_le32(encryption_info->encrypt_tweak_upper,
  4814. &request->encrypt_tweak_upper);
  4815. }
  4816. rc = pqi_build_aio_sg_list(ctrl_info, request, scmd, io_request);
  4817. if (rc) {
  4818. pqi_free_io_request(io_request);
  4819. return SCSI_MLQUEUE_HOST_BUSY;
  4820. }
  4821. pqi_start_io(ctrl_info, queue_group, AIO_PATH, io_request);
  4822. return 0;
  4823. }
  4824. static int pqi_aio_submit_r1_write_io(struct pqi_ctrl_info *ctrl_info,
  4825. struct scsi_cmnd *scmd, struct pqi_queue_group *queue_group,
  4826. struct pqi_encryption_info *encryption_info, struct pqi_scsi_dev *device,
  4827. struct pqi_scsi_dev_raid_map_data *rmd)
  4828. {
  4829. int rc;
  4830. struct pqi_io_request *io_request;
  4831. struct pqi_aio_r1_path_request *r1_request;
  4832. io_request = pqi_alloc_io_request(ctrl_info, scmd);
  4833. if (!io_request)
  4834. return SCSI_MLQUEUE_HOST_BUSY;
  4835. io_request->io_complete_callback = pqi_aio_io_complete;
  4836. io_request->scmd = scmd;
  4837. io_request->raid_bypass = true;
  4838. r1_request = io_request->iu;
  4839. memset(r1_request, 0, offsetof(struct pqi_aio_r1_path_request, sg_descriptors));
  4840. r1_request->header.iu_type = PQI_REQUEST_IU_AIO_PATH_RAID1_IO;
  4841. put_unaligned_le16(*(u16 *)device->scsi3addr & 0x3fff, &r1_request->volume_id);
  4842. r1_request->num_drives = rmd->num_it_nexus_entries;
  4843. put_unaligned_le32(rmd->it_nexus[0], &r1_request->it_nexus_1);
  4844. put_unaligned_le32(rmd->it_nexus[1], &r1_request->it_nexus_2);
  4845. if (rmd->num_it_nexus_entries == 3)
  4846. put_unaligned_le32(rmd->it_nexus[2], &r1_request->it_nexus_3);
  4847. put_unaligned_le32(scsi_bufflen(scmd), &r1_request->data_length);
  4848. r1_request->task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  4849. put_unaligned_le16(io_request->index, &r1_request->request_id);
  4850. r1_request->error_index = r1_request->request_id;
  4851. if (rmd->cdb_length > sizeof(r1_request->cdb))
  4852. rmd->cdb_length = sizeof(r1_request->cdb);
  4853. r1_request->cdb_length = rmd->cdb_length;
  4854. memcpy(r1_request->cdb, rmd->cdb, rmd->cdb_length);
  4855. /* The direction is always write. */
  4856. r1_request->data_direction = SOP_READ_FLAG;
  4857. if (encryption_info) {
  4858. r1_request->encryption_enable = true;
  4859. put_unaligned_le16(encryption_info->data_encryption_key_index,
  4860. &r1_request->data_encryption_key_index);
  4861. put_unaligned_le32(encryption_info->encrypt_tweak_lower,
  4862. &r1_request->encrypt_tweak_lower);
  4863. put_unaligned_le32(encryption_info->encrypt_tweak_upper,
  4864. &r1_request->encrypt_tweak_upper);
  4865. }
  4866. rc = pqi_build_aio_r1_sg_list(ctrl_info, r1_request, scmd, io_request);
  4867. if (rc) {
  4868. pqi_free_io_request(io_request);
  4869. return SCSI_MLQUEUE_HOST_BUSY;
  4870. }
  4871. pqi_start_io(ctrl_info, queue_group, AIO_PATH, io_request);
  4872. return 0;
  4873. }
  4874. static int pqi_aio_submit_r56_write_io(struct pqi_ctrl_info *ctrl_info,
  4875. struct scsi_cmnd *scmd, struct pqi_queue_group *queue_group,
  4876. struct pqi_encryption_info *encryption_info, struct pqi_scsi_dev *device,
  4877. struct pqi_scsi_dev_raid_map_data *rmd)
  4878. {
  4879. int rc;
  4880. struct pqi_io_request *io_request;
  4881. struct pqi_aio_r56_path_request *r56_request;
  4882. io_request = pqi_alloc_io_request(ctrl_info, scmd);
  4883. if (!io_request)
  4884. return SCSI_MLQUEUE_HOST_BUSY;
  4885. io_request->io_complete_callback = pqi_aio_io_complete;
  4886. io_request->scmd = scmd;
  4887. io_request->raid_bypass = true;
  4888. r56_request = io_request->iu;
  4889. memset(r56_request, 0, offsetof(struct pqi_aio_r56_path_request, sg_descriptors));
  4890. if (device->raid_level == SA_RAID_5 || device->raid_level == SA_RAID_51)
  4891. r56_request->header.iu_type = PQI_REQUEST_IU_AIO_PATH_RAID5_IO;
  4892. else
  4893. r56_request->header.iu_type = PQI_REQUEST_IU_AIO_PATH_RAID6_IO;
  4894. put_unaligned_le16(*(u16 *)device->scsi3addr & 0x3fff, &r56_request->volume_id);
  4895. put_unaligned_le32(rmd->aio_handle, &r56_request->data_it_nexus);
  4896. put_unaligned_le32(rmd->p_parity_it_nexus, &r56_request->p_parity_it_nexus);
  4897. if (rmd->raid_level == SA_RAID_6) {
  4898. put_unaligned_le32(rmd->q_parity_it_nexus, &r56_request->q_parity_it_nexus);
  4899. r56_request->xor_multiplier = rmd->xor_mult;
  4900. }
  4901. put_unaligned_le32(scsi_bufflen(scmd), &r56_request->data_length);
  4902. r56_request->task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  4903. put_unaligned_le64(rmd->row, &r56_request->row);
  4904. put_unaligned_le16(io_request->index, &r56_request->request_id);
  4905. r56_request->error_index = r56_request->request_id;
  4906. if (rmd->cdb_length > sizeof(r56_request->cdb))
  4907. rmd->cdb_length = sizeof(r56_request->cdb);
  4908. r56_request->cdb_length = rmd->cdb_length;
  4909. memcpy(r56_request->cdb, rmd->cdb, rmd->cdb_length);
  4910. /* The direction is always write. */
  4911. r56_request->data_direction = SOP_READ_FLAG;
  4912. if (encryption_info) {
  4913. r56_request->encryption_enable = true;
  4914. put_unaligned_le16(encryption_info->data_encryption_key_index,
  4915. &r56_request->data_encryption_key_index);
  4916. put_unaligned_le32(encryption_info->encrypt_tweak_lower,
  4917. &r56_request->encrypt_tweak_lower);
  4918. put_unaligned_le32(encryption_info->encrypt_tweak_upper,
  4919. &r56_request->encrypt_tweak_upper);
  4920. }
  4921. rc = pqi_build_aio_r56_sg_list(ctrl_info, r56_request, scmd, io_request);
  4922. if (rc) {
  4923. pqi_free_io_request(io_request);
  4924. return SCSI_MLQUEUE_HOST_BUSY;
  4925. }
  4926. pqi_start_io(ctrl_info, queue_group, AIO_PATH, io_request);
  4927. return 0;
  4928. }
  4929. static inline u16 pqi_get_hw_queue(struct pqi_ctrl_info *ctrl_info,
  4930. struct scsi_cmnd *scmd)
  4931. {
  4932. /*
  4933. * We are setting host_tagset = 1 during init.
  4934. */
  4935. return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(scsi_cmd_to_rq(scmd)));
  4936. }
  4937. static inline bool pqi_is_bypass_eligible_request(struct scsi_cmnd *scmd)
  4938. {
  4939. if (blk_rq_is_passthrough(scsi_cmd_to_rq(scmd)))
  4940. return false;
  4941. return pqi_cmd_priv(scmd)->this_residual == 0;
  4942. }
  4943. /*
  4944. * This function gets called just before we hand the completed SCSI request
  4945. * back to the SML.
  4946. */
  4947. void pqi_prep_for_scsi_done(struct scsi_cmnd *scmd)
  4948. {
  4949. struct pqi_scsi_dev *device;
  4950. struct completion *wait;
  4951. if (!scmd->device) {
  4952. set_host_byte(scmd, DID_NO_CONNECT);
  4953. return;
  4954. }
  4955. device = scmd->device->hostdata;
  4956. if (!device) {
  4957. set_host_byte(scmd, DID_NO_CONNECT);
  4958. return;
  4959. }
  4960. atomic_dec(&device->scsi_cmds_outstanding[scmd->device->lun]);
  4961. wait = (struct completion *)xchg(&scmd->host_scribble, NULL);
  4962. if (wait != PQI_NO_COMPLETION)
  4963. complete(wait);
  4964. }
  4965. static bool pqi_is_parity_write_stream(struct pqi_ctrl_info *ctrl_info,
  4966. struct scsi_cmnd *scmd)
  4967. {
  4968. u32 oldest_jiffies;
  4969. u8 lru_index;
  4970. int i;
  4971. int rc;
  4972. struct pqi_scsi_dev *device;
  4973. struct pqi_stream_data *pqi_stream_data;
  4974. struct pqi_scsi_dev_raid_map_data rmd = { 0 };
  4975. if (!ctrl_info->enable_stream_detection)
  4976. return false;
  4977. rc = pqi_get_aio_lba_and_block_count(scmd, &rmd);
  4978. if (rc)
  4979. return false;
  4980. /* Check writes only. */
  4981. if (!rmd.is_write)
  4982. return false;
  4983. device = scmd->device->hostdata;
  4984. /* Check for RAID 5/6 streams. */
  4985. if (device->raid_level != SA_RAID_5 && device->raid_level != SA_RAID_6)
  4986. return false;
  4987. /*
  4988. * If controller does not support AIO RAID{5,6} writes, need to send
  4989. * requests down non-AIO path.
  4990. */
  4991. if ((device->raid_level == SA_RAID_5 && !ctrl_info->enable_r5_writes) ||
  4992. (device->raid_level == SA_RAID_6 && !ctrl_info->enable_r6_writes))
  4993. return true;
  4994. lru_index = 0;
  4995. oldest_jiffies = INT_MAX;
  4996. for (i = 0; i < NUM_STREAMS_PER_LUN; i++) {
  4997. pqi_stream_data = &device->stream_data[i];
  4998. /*
  4999. * Check for adjacent request or request is within
  5000. * the previous request.
  5001. */
  5002. if ((pqi_stream_data->next_lba &&
  5003. rmd.first_block >= pqi_stream_data->next_lba) &&
  5004. rmd.first_block <= pqi_stream_data->next_lba +
  5005. rmd.block_cnt) {
  5006. pqi_stream_data->next_lba = rmd.first_block +
  5007. rmd.block_cnt;
  5008. pqi_stream_data->last_accessed = jiffies;
  5009. per_cpu_ptr(device->raid_io_stats, smp_processor_id())->write_stream_cnt++;
  5010. return true;
  5011. }
  5012. /* unused entry */
  5013. if (pqi_stream_data->last_accessed == 0) {
  5014. lru_index = i;
  5015. break;
  5016. }
  5017. /* Find entry with oldest last accessed time. */
  5018. if (pqi_stream_data->last_accessed <= oldest_jiffies) {
  5019. oldest_jiffies = pqi_stream_data->last_accessed;
  5020. lru_index = i;
  5021. }
  5022. }
  5023. /* Set LRU entry. */
  5024. pqi_stream_data = &device->stream_data[lru_index];
  5025. pqi_stream_data->last_accessed = jiffies;
  5026. pqi_stream_data->next_lba = rmd.first_block + rmd.block_cnt;
  5027. return false;
  5028. }
  5029. static int pqi_scsi_queue_command(struct Scsi_Host *shost, struct scsi_cmnd *scmd)
  5030. {
  5031. int rc;
  5032. struct pqi_ctrl_info *ctrl_info;
  5033. struct pqi_scsi_dev *device;
  5034. u16 hw_queue;
  5035. struct pqi_queue_group *queue_group;
  5036. bool raid_bypassed;
  5037. u8 lun;
  5038. scmd->host_scribble = PQI_NO_COMPLETION;
  5039. device = scmd->device->hostdata;
  5040. if (!device) {
  5041. set_host_byte(scmd, DID_NO_CONNECT);
  5042. pqi_scsi_done(scmd);
  5043. return 0;
  5044. }
  5045. lun = (u8)scmd->device->lun;
  5046. atomic_inc(&device->scsi_cmds_outstanding[lun]);
  5047. ctrl_info = shost_to_hba(shost);
  5048. if (pqi_ctrl_offline(ctrl_info) || pqi_device_offline(device) || pqi_device_in_remove(device)) {
  5049. set_host_byte(scmd, DID_NO_CONNECT);
  5050. pqi_scsi_done(scmd);
  5051. return 0;
  5052. }
  5053. if (pqi_ctrl_blocked(ctrl_info) || pqi_device_in_reset(device, lun)) {
  5054. rc = SCSI_MLQUEUE_HOST_BUSY;
  5055. goto out;
  5056. }
  5057. /*
  5058. * This is necessary because the SML doesn't zero out this field during
  5059. * error recovery.
  5060. */
  5061. scmd->result = 0;
  5062. hw_queue = pqi_get_hw_queue(ctrl_info, scmd);
  5063. queue_group = &ctrl_info->queue_groups[hw_queue];
  5064. if (pqi_is_logical_device(device)) {
  5065. raid_bypassed = false;
  5066. if (device->raid_bypass_enabled &&
  5067. pqi_is_bypass_eligible_request(scmd) &&
  5068. !pqi_is_parity_write_stream(ctrl_info, scmd)) {
  5069. rc = pqi_raid_bypass_submit_scsi_cmd(ctrl_info, device, scmd, queue_group);
  5070. if (rc == 0 || rc == SCSI_MLQUEUE_HOST_BUSY) {
  5071. raid_bypassed = true;
  5072. per_cpu_ptr(device->raid_io_stats, smp_processor_id())->raid_bypass_cnt++;
  5073. }
  5074. }
  5075. if (!raid_bypassed)
  5076. rc = pqi_raid_submit_scsi_cmd(ctrl_info, device, scmd, queue_group);
  5077. } else {
  5078. if (device->aio_enabled)
  5079. rc = pqi_aio_submit_scsi_cmd(ctrl_info, device, scmd, queue_group);
  5080. else
  5081. rc = pqi_raid_submit_scsi_cmd(ctrl_info, device, scmd, queue_group);
  5082. }
  5083. out:
  5084. if (rc) {
  5085. scmd->host_scribble = NULL;
  5086. atomic_dec(&device->scsi_cmds_outstanding[lun]);
  5087. }
  5088. return rc;
  5089. }
  5090. static unsigned int pqi_queued_io_count(struct pqi_ctrl_info *ctrl_info)
  5091. {
  5092. unsigned int i;
  5093. unsigned int path;
  5094. unsigned long flags;
  5095. unsigned int queued_io_count;
  5096. struct pqi_queue_group *queue_group;
  5097. struct pqi_io_request *io_request;
  5098. queued_io_count = 0;
  5099. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  5100. queue_group = &ctrl_info->queue_groups[i];
  5101. for (path = 0; path < 2; path++) {
  5102. spin_lock_irqsave(&queue_group->submit_lock[path], flags);
  5103. list_for_each_entry(io_request, &queue_group->request_list[path], request_list_entry)
  5104. queued_io_count++;
  5105. spin_unlock_irqrestore(&queue_group->submit_lock[path], flags);
  5106. }
  5107. }
  5108. return queued_io_count;
  5109. }
  5110. static unsigned int pqi_nonempty_inbound_queue_count(struct pqi_ctrl_info *ctrl_info)
  5111. {
  5112. unsigned int i;
  5113. unsigned int path;
  5114. unsigned int nonempty_inbound_queue_count;
  5115. struct pqi_queue_group *queue_group;
  5116. pqi_index_t iq_pi;
  5117. pqi_index_t iq_ci;
  5118. nonempty_inbound_queue_count = 0;
  5119. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  5120. queue_group = &ctrl_info->queue_groups[i];
  5121. for (path = 0; path < 2; path++) {
  5122. iq_pi = queue_group->iq_pi_copy[path];
  5123. iq_ci = readl(queue_group->iq_ci[path]);
  5124. if (iq_ci != iq_pi)
  5125. nonempty_inbound_queue_count++;
  5126. }
  5127. }
  5128. return nonempty_inbound_queue_count;
  5129. }
  5130. #define PQI_INBOUND_QUEUES_NONEMPTY_WARNING_TIMEOUT_SECS 10
  5131. static int pqi_wait_until_inbound_queues_empty(struct pqi_ctrl_info *ctrl_info)
  5132. {
  5133. unsigned long start_jiffies;
  5134. unsigned long warning_timeout;
  5135. unsigned int queued_io_count;
  5136. unsigned int nonempty_inbound_queue_count;
  5137. bool displayed_warning;
  5138. displayed_warning = false;
  5139. start_jiffies = jiffies;
  5140. warning_timeout = (PQI_INBOUND_QUEUES_NONEMPTY_WARNING_TIMEOUT_SECS * HZ) + start_jiffies;
  5141. while (1) {
  5142. queued_io_count = pqi_queued_io_count(ctrl_info);
  5143. nonempty_inbound_queue_count = pqi_nonempty_inbound_queue_count(ctrl_info);
  5144. if (queued_io_count == 0 && nonempty_inbound_queue_count == 0)
  5145. break;
  5146. pqi_check_ctrl_health(ctrl_info);
  5147. if (pqi_ctrl_offline(ctrl_info))
  5148. return -ENXIO;
  5149. if (time_after(jiffies, warning_timeout)) {
  5150. dev_warn(&ctrl_info->pci_dev->dev,
  5151. "waiting %u seconds for queued I/O to drain (queued I/O count: %u; non-empty inbound queue count: %u)\n",
  5152. jiffies_to_msecs(jiffies - start_jiffies) / 1000, queued_io_count, nonempty_inbound_queue_count);
  5153. displayed_warning = true;
  5154. warning_timeout = (PQI_INBOUND_QUEUES_NONEMPTY_WARNING_TIMEOUT_SECS * HZ) + jiffies;
  5155. }
  5156. usleep_range(1000, 2000);
  5157. }
  5158. if (displayed_warning)
  5159. dev_warn(&ctrl_info->pci_dev->dev,
  5160. "queued I/O drained after waiting for %u seconds\n",
  5161. jiffies_to_msecs(jiffies - start_jiffies) / 1000);
  5162. return 0;
  5163. }
  5164. static void pqi_fail_io_queued_for_device(struct pqi_ctrl_info *ctrl_info,
  5165. struct pqi_scsi_dev *device, u8 lun)
  5166. {
  5167. unsigned int i;
  5168. unsigned int path;
  5169. struct pqi_queue_group *queue_group;
  5170. unsigned long flags;
  5171. struct pqi_io_request *io_request;
  5172. struct pqi_io_request *next;
  5173. struct scsi_cmnd *scmd;
  5174. struct pqi_scsi_dev *scsi_device;
  5175. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  5176. queue_group = &ctrl_info->queue_groups[i];
  5177. for (path = 0; path < 2; path++) {
  5178. spin_lock_irqsave(
  5179. &queue_group->submit_lock[path], flags);
  5180. list_for_each_entry_safe(io_request, next,
  5181. &queue_group->request_list[path],
  5182. request_list_entry) {
  5183. scmd = io_request->scmd;
  5184. if (!scmd)
  5185. continue;
  5186. scsi_device = scmd->device->hostdata;
  5187. list_del(&io_request->request_list_entry);
  5188. if (scsi_device == device && (u8)scmd->device->lun == lun)
  5189. set_host_byte(scmd, DID_RESET);
  5190. else
  5191. set_host_byte(scmd, DID_REQUEUE);
  5192. pqi_free_io_request(io_request);
  5193. scsi_dma_unmap(scmd);
  5194. pqi_scsi_done(scmd);
  5195. }
  5196. spin_unlock_irqrestore(
  5197. &queue_group->submit_lock[path], flags);
  5198. }
  5199. }
  5200. }
  5201. #define PQI_PENDING_IO_WARNING_TIMEOUT_SECS 10
  5202. static int pqi_device_wait_for_pending_io(struct pqi_ctrl_info *ctrl_info,
  5203. struct pqi_scsi_dev *device, u8 lun, unsigned long timeout_msecs)
  5204. {
  5205. int cmds_outstanding;
  5206. unsigned long start_jiffies;
  5207. unsigned long warning_timeout;
  5208. unsigned long msecs_waiting;
  5209. start_jiffies = jiffies;
  5210. warning_timeout = (PQI_PENDING_IO_WARNING_TIMEOUT_SECS * HZ) + start_jiffies;
  5211. while ((cmds_outstanding = atomic_read(&device->scsi_cmds_outstanding[lun])) > 0) {
  5212. if (ctrl_info->ctrl_removal_state != PQI_CTRL_GRACEFUL_REMOVAL) {
  5213. pqi_check_ctrl_health(ctrl_info);
  5214. if (pqi_ctrl_offline(ctrl_info))
  5215. return -ENXIO;
  5216. }
  5217. msecs_waiting = jiffies_to_msecs(jiffies - start_jiffies);
  5218. if (msecs_waiting >= timeout_msecs) {
  5219. dev_err(&ctrl_info->pci_dev->dev,
  5220. "scsi %d:%d:%d:%d: timed out after %lu seconds waiting for %d outstanding command(s)\n",
  5221. ctrl_info->scsi_host->host_no, device->bus, device->target,
  5222. lun, msecs_waiting / 1000, cmds_outstanding);
  5223. return -ETIMEDOUT;
  5224. }
  5225. if (time_after(jiffies, warning_timeout)) {
  5226. dev_warn(&ctrl_info->pci_dev->dev,
  5227. "scsi %d:%d:%d:%d: waiting %lu seconds for %d outstanding command(s)\n",
  5228. ctrl_info->scsi_host->host_no, device->bus, device->target,
  5229. lun, msecs_waiting / 1000, cmds_outstanding);
  5230. warning_timeout = (PQI_PENDING_IO_WARNING_TIMEOUT_SECS * HZ) + jiffies;
  5231. }
  5232. usleep_range(1000, 2000);
  5233. }
  5234. return 0;
  5235. }
  5236. static void pqi_lun_reset_complete(struct pqi_io_request *io_request,
  5237. void *context)
  5238. {
  5239. struct completion *waiting = context;
  5240. complete(waiting);
  5241. }
  5242. #define PQI_LUN_RESET_POLL_COMPLETION_SECS 10
  5243. static int pqi_wait_for_lun_reset_completion(struct pqi_ctrl_info *ctrl_info,
  5244. struct pqi_scsi_dev *device, u8 lun, struct completion *wait)
  5245. {
  5246. int rc;
  5247. unsigned int wait_secs;
  5248. int cmds_outstanding;
  5249. wait_secs = 0;
  5250. while (1) {
  5251. if (wait_for_completion_io_timeout(wait,
  5252. PQI_LUN_RESET_POLL_COMPLETION_SECS * HZ)) {
  5253. rc = 0;
  5254. break;
  5255. }
  5256. pqi_check_ctrl_health(ctrl_info);
  5257. if (pqi_ctrl_offline(ctrl_info)) {
  5258. rc = -ENXIO;
  5259. break;
  5260. }
  5261. wait_secs += PQI_LUN_RESET_POLL_COMPLETION_SECS;
  5262. cmds_outstanding = atomic_read(&device->scsi_cmds_outstanding[lun]);
  5263. dev_warn(&ctrl_info->pci_dev->dev,
  5264. "scsi %d:%d:%d:%d: waiting %u seconds for LUN reset to complete (%d command(s) outstanding)\n",
  5265. ctrl_info->scsi_host->host_no, device->bus, device->target, lun, wait_secs, cmds_outstanding);
  5266. }
  5267. return rc;
  5268. }
  5269. #define PQI_LUN_RESET_FIRMWARE_TIMEOUT_SECS 30
  5270. static int pqi_lun_reset(struct pqi_ctrl_info *ctrl_info, struct pqi_scsi_dev *device, u8 lun)
  5271. {
  5272. int rc;
  5273. struct pqi_io_request *io_request;
  5274. DECLARE_COMPLETION_ONSTACK(wait);
  5275. struct pqi_task_management_request *request;
  5276. io_request = pqi_alloc_io_request(ctrl_info, NULL);
  5277. io_request->io_complete_callback = pqi_lun_reset_complete;
  5278. io_request->context = &wait;
  5279. request = io_request->iu;
  5280. memset(request, 0, sizeof(*request));
  5281. request->header.iu_type = PQI_REQUEST_IU_TASK_MANAGEMENT;
  5282. put_unaligned_le16(sizeof(*request) - PQI_REQUEST_HEADER_LENGTH,
  5283. &request->header.iu_length);
  5284. put_unaligned_le16(io_request->index, &request->request_id);
  5285. memcpy(request->lun_number, device->scsi3addr,
  5286. sizeof(request->lun_number));
  5287. if (!pqi_is_logical_device(device) && ctrl_info->multi_lun_device_supported)
  5288. request->ml_device_lun_number = lun;
  5289. request->task_management_function = SOP_TASK_MANAGEMENT_LUN_RESET;
  5290. if (ctrl_info->tmf_iu_timeout_supported)
  5291. put_unaligned_le16(PQI_LUN_RESET_FIRMWARE_TIMEOUT_SECS, &request->timeout);
  5292. pqi_start_io(ctrl_info, &ctrl_info->queue_groups[PQI_DEFAULT_QUEUE_GROUP], RAID_PATH,
  5293. io_request);
  5294. rc = pqi_wait_for_lun_reset_completion(ctrl_info, device, lun, &wait);
  5295. if (rc == 0)
  5296. rc = io_request->status;
  5297. pqi_free_io_request(io_request);
  5298. return rc;
  5299. }
  5300. #define PQI_LUN_RESET_RETRIES 3
  5301. #define PQI_LUN_RESET_RETRY_INTERVAL_MSECS (10 * 1000)
  5302. #define PQI_LUN_RESET_PENDING_IO_TIMEOUT_MSECS (10 * 60 * 1000)
  5303. #define PQI_LUN_RESET_FAILED_PENDING_IO_TIMEOUT_MSECS (2 * 60 * 1000)
  5304. static int pqi_lun_reset_with_retries(struct pqi_ctrl_info *ctrl_info, struct pqi_scsi_dev *device, u8 lun)
  5305. {
  5306. int reset_rc;
  5307. int wait_rc;
  5308. unsigned int retries;
  5309. unsigned long timeout_msecs;
  5310. for (retries = 0;;) {
  5311. reset_rc = pqi_lun_reset(ctrl_info, device, lun);
  5312. if (reset_rc == 0 || reset_rc == -ENODEV || reset_rc == -ENXIO || ++retries > PQI_LUN_RESET_RETRIES)
  5313. break;
  5314. msleep(PQI_LUN_RESET_RETRY_INTERVAL_MSECS);
  5315. }
  5316. timeout_msecs = reset_rc ? PQI_LUN_RESET_FAILED_PENDING_IO_TIMEOUT_MSECS :
  5317. PQI_LUN_RESET_PENDING_IO_TIMEOUT_MSECS;
  5318. wait_rc = pqi_device_wait_for_pending_io(ctrl_info, device, lun, timeout_msecs);
  5319. if (wait_rc && reset_rc == 0)
  5320. reset_rc = wait_rc;
  5321. return reset_rc == 0 ? SUCCESS : FAILED;
  5322. }
  5323. static int pqi_device_reset(struct pqi_ctrl_info *ctrl_info, struct pqi_scsi_dev *device, u8 lun)
  5324. {
  5325. int rc;
  5326. pqi_ctrl_block_requests(ctrl_info);
  5327. pqi_ctrl_wait_until_quiesced(ctrl_info);
  5328. pqi_fail_io_queued_for_device(ctrl_info, device, lun);
  5329. rc = pqi_wait_until_inbound_queues_empty(ctrl_info);
  5330. pqi_device_reset_start(device, lun);
  5331. pqi_ctrl_unblock_requests(ctrl_info);
  5332. if (rc)
  5333. rc = FAILED;
  5334. else
  5335. rc = pqi_lun_reset_with_retries(ctrl_info, device, lun);
  5336. pqi_device_reset_done(device, lun);
  5337. return rc;
  5338. }
  5339. static int pqi_device_reset_handler(struct pqi_ctrl_info *ctrl_info, struct pqi_scsi_dev *device, u8 lun, struct scsi_cmnd *scmd, u8 scsi_opcode)
  5340. {
  5341. int rc;
  5342. mutex_lock(&ctrl_info->lun_reset_mutex);
  5343. dev_err(&ctrl_info->pci_dev->dev,
  5344. "resetting scsi %d:%d:%d:%u SCSI cmd at %p due to cmd opcode 0x%02x\n",
  5345. ctrl_info->scsi_host->host_no, device->bus, device->target, lun, scmd, scsi_opcode);
  5346. pqi_check_ctrl_health(ctrl_info);
  5347. if (pqi_ctrl_offline(ctrl_info))
  5348. rc = FAILED;
  5349. else
  5350. rc = pqi_device_reset(ctrl_info, device, lun);
  5351. dev_err(&ctrl_info->pci_dev->dev,
  5352. "reset of scsi %d:%d:%d:%u: %s\n",
  5353. ctrl_info->scsi_host->host_no, device->bus, device->target, lun,
  5354. rc == SUCCESS ? "SUCCESS" : "FAILED");
  5355. mutex_unlock(&ctrl_info->lun_reset_mutex);
  5356. return rc;
  5357. }
  5358. static int pqi_eh_device_reset_handler(struct scsi_cmnd *scmd)
  5359. {
  5360. struct Scsi_Host *shost;
  5361. struct pqi_ctrl_info *ctrl_info;
  5362. struct pqi_scsi_dev *device;
  5363. u8 scsi_opcode;
  5364. shost = scmd->device->host;
  5365. ctrl_info = shost_to_hba(shost);
  5366. device = scmd->device->hostdata;
  5367. scsi_opcode = scmd->cmd_len > 0 ? scmd->cmnd[0] : 0xff;
  5368. return pqi_device_reset_handler(ctrl_info, device, (u8)scmd->device->lun, scmd, scsi_opcode);
  5369. }
  5370. static void pqi_tmf_worker(struct work_struct *work)
  5371. {
  5372. struct pqi_tmf_work *tmf_work;
  5373. struct scsi_cmnd *scmd;
  5374. tmf_work = container_of(work, struct pqi_tmf_work, work_struct);
  5375. scmd = (struct scsi_cmnd *)xchg(&tmf_work->scmd, NULL);
  5376. pqi_device_reset_handler(tmf_work->ctrl_info, tmf_work->device, tmf_work->lun, scmd, tmf_work->scsi_opcode);
  5377. }
  5378. static int pqi_eh_abort_handler(struct scsi_cmnd *scmd)
  5379. {
  5380. struct Scsi_Host *shost;
  5381. struct pqi_ctrl_info *ctrl_info;
  5382. struct pqi_scsi_dev *device;
  5383. struct pqi_tmf_work *tmf_work;
  5384. DECLARE_COMPLETION_ONSTACK(wait);
  5385. shost = scmd->device->host;
  5386. ctrl_info = shost_to_hba(shost);
  5387. device = scmd->device->hostdata;
  5388. dev_err(&ctrl_info->pci_dev->dev,
  5389. "attempting TASK ABORT on scsi %d:%d:%d:%d for SCSI cmd at %p\n",
  5390. shost->host_no, device->bus, device->target, (int)scmd->device->lun, scmd);
  5391. if (cmpxchg(&scmd->host_scribble, PQI_NO_COMPLETION, (void *)&wait) == NULL) {
  5392. dev_err(&ctrl_info->pci_dev->dev,
  5393. "scsi %d:%d:%d:%d for SCSI cmd at %p already completed\n",
  5394. shost->host_no, device->bus, device->target, (int)scmd->device->lun, scmd);
  5395. scmd->result = DID_RESET << 16;
  5396. goto out;
  5397. }
  5398. tmf_work = &device->tmf_work[scmd->device->lun];
  5399. if (cmpxchg(&tmf_work->scmd, NULL, scmd) == NULL) {
  5400. tmf_work->ctrl_info = ctrl_info;
  5401. tmf_work->device = device;
  5402. tmf_work->lun = (u8)scmd->device->lun;
  5403. tmf_work->scsi_opcode = scmd->cmd_len > 0 ? scmd->cmnd[0] : 0xff;
  5404. schedule_work(&tmf_work->work_struct);
  5405. }
  5406. wait_for_completion(&wait);
  5407. dev_err(&ctrl_info->pci_dev->dev,
  5408. "TASK ABORT on scsi %d:%d:%d:%d for SCSI cmd at %p: SUCCESS\n",
  5409. shost->host_no, device->bus, device->target, (int)scmd->device->lun, scmd);
  5410. out:
  5411. return SUCCESS;
  5412. }
  5413. static int pqi_slave_alloc(struct scsi_device *sdev)
  5414. {
  5415. struct pqi_scsi_dev *device;
  5416. unsigned long flags;
  5417. struct pqi_ctrl_info *ctrl_info;
  5418. struct scsi_target *starget;
  5419. struct sas_rphy *rphy;
  5420. ctrl_info = shost_to_hba(sdev->host);
  5421. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  5422. if (sdev_channel(sdev) == PQI_PHYSICAL_DEVICE_BUS) {
  5423. starget = scsi_target(sdev);
  5424. rphy = target_to_rphy(starget);
  5425. device = pqi_find_device_by_sas_rphy(ctrl_info, rphy);
  5426. if (device) {
  5427. if (device->target_lun_valid) {
  5428. device->ignore_device = true;
  5429. } else {
  5430. device->target = sdev_id(sdev);
  5431. device->lun = sdev->lun;
  5432. device->target_lun_valid = true;
  5433. }
  5434. }
  5435. } else {
  5436. device = pqi_find_scsi_dev(ctrl_info, sdev_channel(sdev),
  5437. sdev_id(sdev), sdev->lun);
  5438. }
  5439. if (device) {
  5440. sdev->hostdata = device;
  5441. device->sdev = sdev;
  5442. if (device->queue_depth) {
  5443. device->advertised_queue_depth = device->queue_depth;
  5444. scsi_change_queue_depth(sdev,
  5445. device->advertised_queue_depth);
  5446. }
  5447. if (pqi_is_logical_device(device)) {
  5448. pqi_disable_write_same(sdev);
  5449. } else {
  5450. sdev->allow_restart = 1;
  5451. if (device->device_type == SA_DEVICE_TYPE_NVME)
  5452. pqi_disable_write_same(sdev);
  5453. }
  5454. }
  5455. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5456. return 0;
  5457. }
  5458. static void pqi_map_queues(struct Scsi_Host *shost)
  5459. {
  5460. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  5461. if (!ctrl_info->disable_managed_interrupts)
  5462. return blk_mq_pci_map_queues(&shost->tag_set.map[HCTX_TYPE_DEFAULT],
  5463. ctrl_info->pci_dev, 0);
  5464. else
  5465. return blk_mq_map_queues(&shost->tag_set.map[HCTX_TYPE_DEFAULT]);
  5466. }
  5467. static inline bool pqi_is_tape_changer_device(struct pqi_scsi_dev *device)
  5468. {
  5469. return device->devtype == TYPE_TAPE || device->devtype == TYPE_MEDIUM_CHANGER;
  5470. }
  5471. static int pqi_slave_configure(struct scsi_device *sdev)
  5472. {
  5473. int rc = 0;
  5474. struct pqi_scsi_dev *device;
  5475. device = sdev->hostdata;
  5476. device->devtype = sdev->type;
  5477. if (pqi_is_tape_changer_device(device) && device->ignore_device) {
  5478. rc = -ENXIO;
  5479. device->ignore_device = false;
  5480. }
  5481. return rc;
  5482. }
  5483. static void pqi_slave_destroy(struct scsi_device *sdev)
  5484. {
  5485. struct pqi_ctrl_info *ctrl_info;
  5486. struct pqi_scsi_dev *device;
  5487. int mutex_acquired;
  5488. unsigned long flags;
  5489. ctrl_info = shost_to_hba(sdev->host);
  5490. mutex_acquired = mutex_trylock(&ctrl_info->scan_mutex);
  5491. if (!mutex_acquired)
  5492. return;
  5493. device = sdev->hostdata;
  5494. if (!device) {
  5495. mutex_unlock(&ctrl_info->scan_mutex);
  5496. return;
  5497. }
  5498. device->lun_count--;
  5499. if (device->lun_count > 0) {
  5500. mutex_unlock(&ctrl_info->scan_mutex);
  5501. return;
  5502. }
  5503. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  5504. list_del(&device->scsi_device_list_entry);
  5505. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5506. mutex_unlock(&ctrl_info->scan_mutex);
  5507. pqi_dev_info(ctrl_info, "removed", device);
  5508. pqi_free_device(device);
  5509. }
  5510. static int pqi_getpciinfo_ioctl(struct pqi_ctrl_info *ctrl_info, void __user *arg)
  5511. {
  5512. struct pci_dev *pci_dev;
  5513. u32 subsystem_vendor;
  5514. u32 subsystem_device;
  5515. cciss_pci_info_struct pci_info;
  5516. if (!arg)
  5517. return -EINVAL;
  5518. pci_dev = ctrl_info->pci_dev;
  5519. pci_info.domain = pci_domain_nr(pci_dev->bus);
  5520. pci_info.bus = pci_dev->bus->number;
  5521. pci_info.dev_fn = pci_dev->devfn;
  5522. subsystem_vendor = pci_dev->subsystem_vendor;
  5523. subsystem_device = pci_dev->subsystem_device;
  5524. pci_info.board_id = ((subsystem_device << 16) & 0xffff0000) | subsystem_vendor;
  5525. if (copy_to_user(arg, &pci_info, sizeof(pci_info)))
  5526. return -EFAULT;
  5527. return 0;
  5528. }
  5529. static int pqi_getdrivver_ioctl(void __user *arg)
  5530. {
  5531. u32 version;
  5532. if (!arg)
  5533. return -EINVAL;
  5534. version = (DRIVER_MAJOR << 28) | (DRIVER_MINOR << 24) |
  5535. (DRIVER_RELEASE << 16) | DRIVER_REVISION;
  5536. if (copy_to_user(arg, &version, sizeof(version)))
  5537. return -EFAULT;
  5538. return 0;
  5539. }
  5540. struct ciss_error_info {
  5541. u8 scsi_status;
  5542. int command_status;
  5543. size_t sense_data_length;
  5544. };
  5545. static void pqi_error_info_to_ciss(struct pqi_raid_error_info *pqi_error_info,
  5546. struct ciss_error_info *ciss_error_info)
  5547. {
  5548. int ciss_cmd_status;
  5549. size_t sense_data_length;
  5550. switch (pqi_error_info->data_out_result) {
  5551. case PQI_DATA_IN_OUT_GOOD:
  5552. ciss_cmd_status = CISS_CMD_STATUS_SUCCESS;
  5553. break;
  5554. case PQI_DATA_IN_OUT_UNDERFLOW:
  5555. ciss_cmd_status = CISS_CMD_STATUS_DATA_UNDERRUN;
  5556. break;
  5557. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW:
  5558. ciss_cmd_status = CISS_CMD_STATUS_DATA_OVERRUN;
  5559. break;
  5560. case PQI_DATA_IN_OUT_PROTOCOL_ERROR:
  5561. case PQI_DATA_IN_OUT_BUFFER_ERROR:
  5562. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA:
  5563. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE:
  5564. case PQI_DATA_IN_OUT_ERROR:
  5565. ciss_cmd_status = CISS_CMD_STATUS_PROTOCOL_ERROR;
  5566. break;
  5567. case PQI_DATA_IN_OUT_HARDWARE_ERROR:
  5568. case PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR:
  5569. case PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT:
  5570. case PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED:
  5571. case PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED:
  5572. case PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED:
  5573. case PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST:
  5574. case PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION:
  5575. case PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED:
  5576. case PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ:
  5577. ciss_cmd_status = CISS_CMD_STATUS_HARDWARE_ERROR;
  5578. break;
  5579. case PQI_DATA_IN_OUT_UNSOLICITED_ABORT:
  5580. ciss_cmd_status = CISS_CMD_STATUS_UNSOLICITED_ABORT;
  5581. break;
  5582. case PQI_DATA_IN_OUT_ABORTED:
  5583. ciss_cmd_status = CISS_CMD_STATUS_ABORTED;
  5584. break;
  5585. case PQI_DATA_IN_OUT_TIMEOUT:
  5586. ciss_cmd_status = CISS_CMD_STATUS_TIMEOUT;
  5587. break;
  5588. default:
  5589. ciss_cmd_status = CISS_CMD_STATUS_TARGET_STATUS;
  5590. break;
  5591. }
  5592. sense_data_length =
  5593. get_unaligned_le16(&pqi_error_info->sense_data_length);
  5594. if (sense_data_length == 0)
  5595. sense_data_length =
  5596. get_unaligned_le16(&pqi_error_info->response_data_length);
  5597. if (sense_data_length)
  5598. if (sense_data_length > sizeof(pqi_error_info->data))
  5599. sense_data_length = sizeof(pqi_error_info->data);
  5600. ciss_error_info->scsi_status = pqi_error_info->status;
  5601. ciss_error_info->command_status = ciss_cmd_status;
  5602. ciss_error_info->sense_data_length = sense_data_length;
  5603. }
  5604. static int pqi_passthru_ioctl(struct pqi_ctrl_info *ctrl_info, void __user *arg)
  5605. {
  5606. int rc;
  5607. char *kernel_buffer = NULL;
  5608. u16 iu_length;
  5609. size_t sense_data_length;
  5610. IOCTL_Command_struct iocommand;
  5611. struct pqi_raid_path_request request;
  5612. struct pqi_raid_error_info pqi_error_info;
  5613. struct ciss_error_info ciss_error_info;
  5614. if (pqi_ctrl_offline(ctrl_info))
  5615. return -ENXIO;
  5616. if (pqi_ofa_in_progress(ctrl_info) && pqi_ctrl_blocked(ctrl_info))
  5617. return -EBUSY;
  5618. if (!arg)
  5619. return -EINVAL;
  5620. if (!capable(CAP_SYS_RAWIO))
  5621. return -EPERM;
  5622. if (copy_from_user(&iocommand, arg, sizeof(iocommand)))
  5623. return -EFAULT;
  5624. if (iocommand.buf_size < 1 &&
  5625. iocommand.Request.Type.Direction != XFER_NONE)
  5626. return -EINVAL;
  5627. if (iocommand.Request.CDBLen > sizeof(request.cdb))
  5628. return -EINVAL;
  5629. if (iocommand.Request.Type.Type != TYPE_CMD)
  5630. return -EINVAL;
  5631. switch (iocommand.Request.Type.Direction) {
  5632. case XFER_NONE:
  5633. case XFER_WRITE:
  5634. case XFER_READ:
  5635. case XFER_READ | XFER_WRITE:
  5636. break;
  5637. default:
  5638. return -EINVAL;
  5639. }
  5640. if (iocommand.buf_size > 0) {
  5641. kernel_buffer = kmalloc(iocommand.buf_size, GFP_KERNEL);
  5642. if (!kernel_buffer)
  5643. return -ENOMEM;
  5644. if (iocommand.Request.Type.Direction & XFER_WRITE) {
  5645. if (copy_from_user(kernel_buffer, iocommand.buf,
  5646. iocommand.buf_size)) {
  5647. rc = -EFAULT;
  5648. goto out;
  5649. }
  5650. } else {
  5651. memset(kernel_buffer, 0, iocommand.buf_size);
  5652. }
  5653. }
  5654. memset(&request, 0, sizeof(request));
  5655. request.header.iu_type = PQI_REQUEST_IU_RAID_PATH_IO;
  5656. iu_length = offsetof(struct pqi_raid_path_request, sg_descriptors) -
  5657. PQI_REQUEST_HEADER_LENGTH;
  5658. memcpy(request.lun_number, iocommand.LUN_info.LunAddrBytes,
  5659. sizeof(request.lun_number));
  5660. memcpy(request.cdb, iocommand.Request.CDB, iocommand.Request.CDBLen);
  5661. request.additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_0;
  5662. switch (iocommand.Request.Type.Direction) {
  5663. case XFER_NONE:
  5664. request.data_direction = SOP_NO_DIRECTION_FLAG;
  5665. break;
  5666. case XFER_WRITE:
  5667. request.data_direction = SOP_WRITE_FLAG;
  5668. break;
  5669. case XFER_READ:
  5670. request.data_direction = SOP_READ_FLAG;
  5671. break;
  5672. case XFER_READ | XFER_WRITE:
  5673. request.data_direction = SOP_BIDIRECTIONAL;
  5674. break;
  5675. }
  5676. request.task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  5677. if (iocommand.buf_size > 0) {
  5678. put_unaligned_le32(iocommand.buf_size, &request.buffer_length);
  5679. rc = pqi_map_single(ctrl_info->pci_dev,
  5680. &request.sg_descriptors[0], kernel_buffer,
  5681. iocommand.buf_size, DMA_BIDIRECTIONAL);
  5682. if (rc)
  5683. goto out;
  5684. iu_length += sizeof(request.sg_descriptors[0]);
  5685. }
  5686. put_unaligned_le16(iu_length, &request.header.iu_length);
  5687. if (ctrl_info->raid_iu_timeout_supported)
  5688. put_unaligned_le32(iocommand.Request.Timeout, &request.timeout);
  5689. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header,
  5690. PQI_SYNC_FLAGS_INTERRUPTABLE, &pqi_error_info);
  5691. if (iocommand.buf_size > 0)
  5692. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1,
  5693. DMA_BIDIRECTIONAL);
  5694. memset(&iocommand.error_info, 0, sizeof(iocommand.error_info));
  5695. if (rc == 0) {
  5696. pqi_error_info_to_ciss(&pqi_error_info, &ciss_error_info);
  5697. iocommand.error_info.ScsiStatus = ciss_error_info.scsi_status;
  5698. iocommand.error_info.CommandStatus =
  5699. ciss_error_info.command_status;
  5700. sense_data_length = ciss_error_info.sense_data_length;
  5701. if (sense_data_length) {
  5702. if (sense_data_length >
  5703. sizeof(iocommand.error_info.SenseInfo))
  5704. sense_data_length =
  5705. sizeof(iocommand.error_info.SenseInfo);
  5706. memcpy(iocommand.error_info.SenseInfo,
  5707. pqi_error_info.data, sense_data_length);
  5708. iocommand.error_info.SenseLen = sense_data_length;
  5709. }
  5710. }
  5711. if (copy_to_user(arg, &iocommand, sizeof(iocommand))) {
  5712. rc = -EFAULT;
  5713. goto out;
  5714. }
  5715. if (rc == 0 && iocommand.buf_size > 0 &&
  5716. (iocommand.Request.Type.Direction & XFER_READ)) {
  5717. if (copy_to_user(iocommand.buf, kernel_buffer,
  5718. iocommand.buf_size)) {
  5719. rc = -EFAULT;
  5720. }
  5721. }
  5722. out:
  5723. kfree(kernel_buffer);
  5724. return rc;
  5725. }
  5726. static int pqi_ioctl(struct scsi_device *sdev, unsigned int cmd,
  5727. void __user *arg)
  5728. {
  5729. int rc;
  5730. struct pqi_ctrl_info *ctrl_info;
  5731. ctrl_info = shost_to_hba(sdev->host);
  5732. switch (cmd) {
  5733. case CCISS_DEREGDISK:
  5734. case CCISS_REGNEWDISK:
  5735. case CCISS_REGNEWD:
  5736. rc = pqi_scan_scsi_devices(ctrl_info);
  5737. break;
  5738. case CCISS_GETPCIINFO:
  5739. rc = pqi_getpciinfo_ioctl(ctrl_info, arg);
  5740. break;
  5741. case CCISS_GETDRIVVER:
  5742. rc = pqi_getdrivver_ioctl(arg);
  5743. break;
  5744. case CCISS_PASSTHRU:
  5745. rc = pqi_passthru_ioctl(ctrl_info, arg);
  5746. break;
  5747. default:
  5748. rc = -EINVAL;
  5749. break;
  5750. }
  5751. return rc;
  5752. }
  5753. static ssize_t pqi_firmware_version_show(struct device *dev,
  5754. struct device_attribute *attr, char *buffer)
  5755. {
  5756. struct Scsi_Host *shost;
  5757. struct pqi_ctrl_info *ctrl_info;
  5758. shost = class_to_shost(dev);
  5759. ctrl_info = shost_to_hba(shost);
  5760. return scnprintf(buffer, PAGE_SIZE, "%s\n", ctrl_info->firmware_version);
  5761. }
  5762. static ssize_t pqi_serial_number_show(struct device *dev,
  5763. struct device_attribute *attr, char *buffer)
  5764. {
  5765. struct Scsi_Host *shost;
  5766. struct pqi_ctrl_info *ctrl_info;
  5767. shost = class_to_shost(dev);
  5768. ctrl_info = shost_to_hba(shost);
  5769. return scnprintf(buffer, PAGE_SIZE, "%s\n", ctrl_info->serial_number);
  5770. }
  5771. static ssize_t pqi_model_show(struct device *dev,
  5772. struct device_attribute *attr, char *buffer)
  5773. {
  5774. struct Scsi_Host *shost;
  5775. struct pqi_ctrl_info *ctrl_info;
  5776. shost = class_to_shost(dev);
  5777. ctrl_info = shost_to_hba(shost);
  5778. return scnprintf(buffer, PAGE_SIZE, "%s\n", ctrl_info->model);
  5779. }
  5780. static ssize_t pqi_vendor_show(struct device *dev,
  5781. struct device_attribute *attr, char *buffer)
  5782. {
  5783. struct Scsi_Host *shost;
  5784. struct pqi_ctrl_info *ctrl_info;
  5785. shost = class_to_shost(dev);
  5786. ctrl_info = shost_to_hba(shost);
  5787. return scnprintf(buffer, PAGE_SIZE, "%s\n", ctrl_info->vendor);
  5788. }
  5789. static ssize_t pqi_host_rescan_store(struct device *dev,
  5790. struct device_attribute *attr, const char *buffer, size_t count)
  5791. {
  5792. struct Scsi_Host *shost = class_to_shost(dev);
  5793. pqi_scan_start(shost);
  5794. return count;
  5795. }
  5796. static ssize_t pqi_lockup_action_show(struct device *dev,
  5797. struct device_attribute *attr, char *buffer)
  5798. {
  5799. int count = 0;
  5800. unsigned int i;
  5801. for (i = 0; i < ARRAY_SIZE(pqi_lockup_actions); i++) {
  5802. if (pqi_lockup_actions[i].action == pqi_lockup_action)
  5803. count += scnprintf(buffer + count, PAGE_SIZE - count,
  5804. "[%s] ", pqi_lockup_actions[i].name);
  5805. else
  5806. count += scnprintf(buffer + count, PAGE_SIZE - count,
  5807. "%s ", pqi_lockup_actions[i].name);
  5808. }
  5809. count += scnprintf(buffer + count, PAGE_SIZE - count, "\n");
  5810. return count;
  5811. }
  5812. static ssize_t pqi_lockup_action_store(struct device *dev,
  5813. struct device_attribute *attr, const char *buffer, size_t count)
  5814. {
  5815. unsigned int i;
  5816. char *action_name;
  5817. char action_name_buffer[32];
  5818. strscpy(action_name_buffer, buffer, sizeof(action_name_buffer));
  5819. action_name = strstrip(action_name_buffer);
  5820. for (i = 0; i < ARRAY_SIZE(pqi_lockup_actions); i++) {
  5821. if (strcmp(action_name, pqi_lockup_actions[i].name) == 0) {
  5822. pqi_lockup_action = pqi_lockup_actions[i].action;
  5823. return count;
  5824. }
  5825. }
  5826. return -EINVAL;
  5827. }
  5828. static ssize_t pqi_host_enable_stream_detection_show(struct device *dev,
  5829. struct device_attribute *attr, char *buffer)
  5830. {
  5831. struct Scsi_Host *shost = class_to_shost(dev);
  5832. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  5833. return scnprintf(buffer, 10, "%x\n",
  5834. ctrl_info->enable_stream_detection);
  5835. }
  5836. static ssize_t pqi_host_enable_stream_detection_store(struct device *dev,
  5837. struct device_attribute *attr, const char *buffer, size_t count)
  5838. {
  5839. struct Scsi_Host *shost = class_to_shost(dev);
  5840. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  5841. u8 set_stream_detection = 0;
  5842. if (kstrtou8(buffer, 0, &set_stream_detection))
  5843. return -EINVAL;
  5844. if (set_stream_detection > 0)
  5845. set_stream_detection = 1;
  5846. ctrl_info->enable_stream_detection = set_stream_detection;
  5847. return count;
  5848. }
  5849. static ssize_t pqi_host_enable_r5_writes_show(struct device *dev,
  5850. struct device_attribute *attr, char *buffer)
  5851. {
  5852. struct Scsi_Host *shost = class_to_shost(dev);
  5853. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  5854. return scnprintf(buffer, 10, "%x\n", ctrl_info->enable_r5_writes);
  5855. }
  5856. static ssize_t pqi_host_enable_r5_writes_store(struct device *dev,
  5857. struct device_attribute *attr, const char *buffer, size_t count)
  5858. {
  5859. struct Scsi_Host *shost = class_to_shost(dev);
  5860. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  5861. u8 set_r5_writes = 0;
  5862. if (kstrtou8(buffer, 0, &set_r5_writes))
  5863. return -EINVAL;
  5864. if (set_r5_writes > 0)
  5865. set_r5_writes = 1;
  5866. ctrl_info->enable_r5_writes = set_r5_writes;
  5867. return count;
  5868. }
  5869. static ssize_t pqi_host_enable_r6_writes_show(struct device *dev,
  5870. struct device_attribute *attr, char *buffer)
  5871. {
  5872. struct Scsi_Host *shost = class_to_shost(dev);
  5873. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  5874. return scnprintf(buffer, 10, "%x\n", ctrl_info->enable_r6_writes);
  5875. }
  5876. static ssize_t pqi_host_enable_r6_writes_store(struct device *dev,
  5877. struct device_attribute *attr, const char *buffer, size_t count)
  5878. {
  5879. struct Scsi_Host *shost = class_to_shost(dev);
  5880. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  5881. u8 set_r6_writes = 0;
  5882. if (kstrtou8(buffer, 0, &set_r6_writes))
  5883. return -EINVAL;
  5884. if (set_r6_writes > 0)
  5885. set_r6_writes = 1;
  5886. ctrl_info->enable_r6_writes = set_r6_writes;
  5887. return count;
  5888. }
  5889. static DEVICE_STRING_ATTR_RO(driver_version, 0444,
  5890. DRIVER_VERSION BUILD_TIMESTAMP);
  5891. static DEVICE_ATTR(firmware_version, 0444, pqi_firmware_version_show, NULL);
  5892. static DEVICE_ATTR(model, 0444, pqi_model_show, NULL);
  5893. static DEVICE_ATTR(serial_number, 0444, pqi_serial_number_show, NULL);
  5894. static DEVICE_ATTR(vendor, 0444, pqi_vendor_show, NULL);
  5895. static DEVICE_ATTR(rescan, 0200, NULL, pqi_host_rescan_store);
  5896. static DEVICE_ATTR(lockup_action, 0644, pqi_lockup_action_show,
  5897. pqi_lockup_action_store);
  5898. static DEVICE_ATTR(enable_stream_detection, 0644,
  5899. pqi_host_enable_stream_detection_show,
  5900. pqi_host_enable_stream_detection_store);
  5901. static DEVICE_ATTR(enable_r5_writes, 0644,
  5902. pqi_host_enable_r5_writes_show, pqi_host_enable_r5_writes_store);
  5903. static DEVICE_ATTR(enable_r6_writes, 0644,
  5904. pqi_host_enable_r6_writes_show, pqi_host_enable_r6_writes_store);
  5905. static struct attribute *pqi_shost_attrs[] = {
  5906. &dev_attr_driver_version.attr.attr,
  5907. &dev_attr_firmware_version.attr,
  5908. &dev_attr_model.attr,
  5909. &dev_attr_serial_number.attr,
  5910. &dev_attr_vendor.attr,
  5911. &dev_attr_rescan.attr,
  5912. &dev_attr_lockup_action.attr,
  5913. &dev_attr_enable_stream_detection.attr,
  5914. &dev_attr_enable_r5_writes.attr,
  5915. &dev_attr_enable_r6_writes.attr,
  5916. NULL
  5917. };
  5918. ATTRIBUTE_GROUPS(pqi_shost);
  5919. static ssize_t pqi_unique_id_show(struct device *dev,
  5920. struct device_attribute *attr, char *buffer)
  5921. {
  5922. struct pqi_ctrl_info *ctrl_info;
  5923. struct scsi_device *sdev;
  5924. struct pqi_scsi_dev *device;
  5925. unsigned long flags;
  5926. u8 unique_id[16];
  5927. sdev = to_scsi_device(dev);
  5928. ctrl_info = shost_to_hba(sdev->host);
  5929. if (pqi_ctrl_offline(ctrl_info))
  5930. return -ENODEV;
  5931. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  5932. device = sdev->hostdata;
  5933. if (!device) {
  5934. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5935. return -ENODEV;
  5936. }
  5937. if (device->is_physical_device)
  5938. memcpy(unique_id, device->wwid, sizeof(device->wwid));
  5939. else
  5940. memcpy(unique_id, device->volume_id, sizeof(device->volume_id));
  5941. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5942. return scnprintf(buffer, PAGE_SIZE,
  5943. "%02X%02X%02X%02X%02X%02X%02X%02X"
  5944. "%02X%02X%02X%02X%02X%02X%02X%02X\n",
  5945. unique_id[0], unique_id[1], unique_id[2], unique_id[3],
  5946. unique_id[4], unique_id[5], unique_id[6], unique_id[7],
  5947. unique_id[8], unique_id[9], unique_id[10], unique_id[11],
  5948. unique_id[12], unique_id[13], unique_id[14], unique_id[15]);
  5949. }
  5950. static ssize_t pqi_lunid_show(struct device *dev,
  5951. struct device_attribute *attr, char *buffer)
  5952. {
  5953. struct pqi_ctrl_info *ctrl_info;
  5954. struct scsi_device *sdev;
  5955. struct pqi_scsi_dev *device;
  5956. unsigned long flags;
  5957. u8 lunid[8];
  5958. sdev = to_scsi_device(dev);
  5959. ctrl_info = shost_to_hba(sdev->host);
  5960. if (pqi_ctrl_offline(ctrl_info))
  5961. return -ENODEV;
  5962. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  5963. device = sdev->hostdata;
  5964. if (!device) {
  5965. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5966. return -ENODEV;
  5967. }
  5968. memcpy(lunid, device->scsi3addr, sizeof(lunid));
  5969. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5970. return scnprintf(buffer, PAGE_SIZE, "0x%8phN\n", lunid);
  5971. }
  5972. #define MAX_PATHS 8
  5973. static ssize_t pqi_path_info_show(struct device *dev,
  5974. struct device_attribute *attr, char *buf)
  5975. {
  5976. struct pqi_ctrl_info *ctrl_info;
  5977. struct scsi_device *sdev;
  5978. struct pqi_scsi_dev *device;
  5979. unsigned long flags;
  5980. int i;
  5981. int output_len = 0;
  5982. u8 box;
  5983. u8 bay;
  5984. u8 path_map_index;
  5985. char *active;
  5986. u8 phys_connector[2];
  5987. sdev = to_scsi_device(dev);
  5988. ctrl_info = shost_to_hba(sdev->host);
  5989. if (pqi_ctrl_offline(ctrl_info))
  5990. return -ENODEV;
  5991. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  5992. device = sdev->hostdata;
  5993. if (!device) {
  5994. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5995. return -ENODEV;
  5996. }
  5997. bay = device->bay;
  5998. for (i = 0; i < MAX_PATHS; i++) {
  5999. path_map_index = 1 << i;
  6000. if (i == device->active_path_index)
  6001. active = "Active";
  6002. else if (device->path_map & path_map_index)
  6003. active = "Inactive";
  6004. else
  6005. continue;
  6006. output_len += scnprintf(buf + output_len,
  6007. PAGE_SIZE - output_len,
  6008. "[%d:%d:%d:%d] %20.20s ",
  6009. ctrl_info->scsi_host->host_no,
  6010. device->bus, device->target,
  6011. device->lun,
  6012. scsi_device_type(device->devtype));
  6013. if (device->devtype == TYPE_RAID ||
  6014. pqi_is_logical_device(device))
  6015. goto end_buffer;
  6016. memcpy(&phys_connector, &device->phys_connector[i],
  6017. sizeof(phys_connector));
  6018. if (phys_connector[0] < '0')
  6019. phys_connector[0] = '0';
  6020. if (phys_connector[1] < '0')
  6021. phys_connector[1] = '0';
  6022. output_len += scnprintf(buf + output_len,
  6023. PAGE_SIZE - output_len,
  6024. "PORT: %.2s ", phys_connector);
  6025. box = device->box[i];
  6026. if (box != 0 && box != 0xFF)
  6027. output_len += scnprintf(buf + output_len,
  6028. PAGE_SIZE - output_len,
  6029. "BOX: %hhu ", box);
  6030. if ((device->devtype == TYPE_DISK ||
  6031. device->devtype == TYPE_ZBC) &&
  6032. pqi_expose_device(device))
  6033. output_len += scnprintf(buf + output_len,
  6034. PAGE_SIZE - output_len,
  6035. "BAY: %hhu ", bay);
  6036. end_buffer:
  6037. output_len += scnprintf(buf + output_len,
  6038. PAGE_SIZE - output_len,
  6039. "%s\n", active);
  6040. }
  6041. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6042. return output_len;
  6043. }
  6044. static ssize_t pqi_sas_address_show(struct device *dev,
  6045. struct device_attribute *attr, char *buffer)
  6046. {
  6047. struct pqi_ctrl_info *ctrl_info;
  6048. struct scsi_device *sdev;
  6049. struct pqi_scsi_dev *device;
  6050. unsigned long flags;
  6051. u64 sas_address;
  6052. sdev = to_scsi_device(dev);
  6053. ctrl_info = shost_to_hba(sdev->host);
  6054. if (pqi_ctrl_offline(ctrl_info))
  6055. return -ENODEV;
  6056. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  6057. device = sdev->hostdata;
  6058. if (!device) {
  6059. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6060. return -ENODEV;
  6061. }
  6062. sas_address = device->sas_address;
  6063. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6064. return scnprintf(buffer, PAGE_SIZE, "0x%016llx\n", sas_address);
  6065. }
  6066. static ssize_t pqi_ssd_smart_path_enabled_show(struct device *dev,
  6067. struct device_attribute *attr, char *buffer)
  6068. {
  6069. struct pqi_ctrl_info *ctrl_info;
  6070. struct scsi_device *sdev;
  6071. struct pqi_scsi_dev *device;
  6072. unsigned long flags;
  6073. sdev = to_scsi_device(dev);
  6074. ctrl_info = shost_to_hba(sdev->host);
  6075. if (pqi_ctrl_offline(ctrl_info))
  6076. return -ENODEV;
  6077. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  6078. device = sdev->hostdata;
  6079. if (!device) {
  6080. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6081. return -ENODEV;
  6082. }
  6083. buffer[0] = device->raid_bypass_enabled ? '1' : '0';
  6084. buffer[1] = '\n';
  6085. buffer[2] = '\0';
  6086. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6087. return 2;
  6088. }
  6089. static ssize_t pqi_raid_level_show(struct device *dev,
  6090. struct device_attribute *attr, char *buffer)
  6091. {
  6092. struct pqi_ctrl_info *ctrl_info;
  6093. struct scsi_device *sdev;
  6094. struct pqi_scsi_dev *device;
  6095. unsigned long flags;
  6096. char *raid_level;
  6097. sdev = to_scsi_device(dev);
  6098. ctrl_info = shost_to_hba(sdev->host);
  6099. if (pqi_ctrl_offline(ctrl_info))
  6100. return -ENODEV;
  6101. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  6102. device = sdev->hostdata;
  6103. if (!device) {
  6104. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6105. return -ENODEV;
  6106. }
  6107. if (pqi_is_logical_device(device) && device->devtype == TYPE_DISK)
  6108. raid_level = pqi_raid_level_to_string(device->raid_level);
  6109. else
  6110. raid_level = "N/A";
  6111. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6112. return scnprintf(buffer, PAGE_SIZE, "%s\n", raid_level);
  6113. }
  6114. static ssize_t pqi_raid_bypass_cnt_show(struct device *dev,
  6115. struct device_attribute *attr, char *buffer)
  6116. {
  6117. struct pqi_ctrl_info *ctrl_info;
  6118. struct scsi_device *sdev;
  6119. struct pqi_scsi_dev *device;
  6120. unsigned long flags;
  6121. u64 raid_bypass_cnt;
  6122. int cpu;
  6123. sdev = to_scsi_device(dev);
  6124. ctrl_info = shost_to_hba(sdev->host);
  6125. if (pqi_ctrl_offline(ctrl_info))
  6126. return -ENODEV;
  6127. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  6128. device = sdev->hostdata;
  6129. if (!device) {
  6130. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6131. return -ENODEV;
  6132. }
  6133. raid_bypass_cnt = 0;
  6134. if (device->raid_io_stats) {
  6135. for_each_online_cpu(cpu) {
  6136. raid_bypass_cnt += per_cpu_ptr(device->raid_io_stats, cpu)->raid_bypass_cnt;
  6137. }
  6138. }
  6139. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6140. return scnprintf(buffer, PAGE_SIZE, "0x%llx\n", raid_bypass_cnt);
  6141. }
  6142. static ssize_t pqi_sas_ncq_prio_enable_show(struct device *dev,
  6143. struct device_attribute *attr, char *buf)
  6144. {
  6145. struct pqi_ctrl_info *ctrl_info;
  6146. struct scsi_device *sdev;
  6147. struct pqi_scsi_dev *device;
  6148. unsigned long flags;
  6149. int output_len = 0;
  6150. sdev = to_scsi_device(dev);
  6151. ctrl_info = shost_to_hba(sdev->host);
  6152. if (pqi_ctrl_offline(ctrl_info))
  6153. return -ENODEV;
  6154. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  6155. device = sdev->hostdata;
  6156. if (!device) {
  6157. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6158. return -ENODEV;
  6159. }
  6160. output_len = snprintf(buf, PAGE_SIZE, "%d\n",
  6161. device->ncq_prio_enable);
  6162. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6163. return output_len;
  6164. }
  6165. static ssize_t pqi_sas_ncq_prio_enable_store(struct device *dev,
  6166. struct device_attribute *attr,
  6167. const char *buf, size_t count)
  6168. {
  6169. struct pqi_ctrl_info *ctrl_info;
  6170. struct scsi_device *sdev;
  6171. struct pqi_scsi_dev *device;
  6172. unsigned long flags;
  6173. u8 ncq_prio_enable = 0;
  6174. if (kstrtou8(buf, 0, &ncq_prio_enable))
  6175. return -EINVAL;
  6176. sdev = to_scsi_device(dev);
  6177. ctrl_info = shost_to_hba(sdev->host);
  6178. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  6179. device = sdev->hostdata;
  6180. if (!device) {
  6181. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6182. return -ENODEV;
  6183. }
  6184. if (!device->ncq_prio_support) {
  6185. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6186. return -EINVAL;
  6187. }
  6188. device->ncq_prio_enable = ncq_prio_enable;
  6189. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6190. return strlen(buf);
  6191. }
  6192. static ssize_t pqi_numa_node_show(struct device *dev,
  6193. struct device_attribute *attr, char *buffer)
  6194. {
  6195. struct scsi_device *sdev;
  6196. struct pqi_ctrl_info *ctrl_info;
  6197. sdev = to_scsi_device(dev);
  6198. ctrl_info = shost_to_hba(sdev->host);
  6199. return scnprintf(buffer, PAGE_SIZE, "%d\n", ctrl_info->numa_node);
  6200. }
  6201. static ssize_t pqi_write_stream_cnt_show(struct device *dev,
  6202. struct device_attribute *attr, char *buffer)
  6203. {
  6204. struct pqi_ctrl_info *ctrl_info;
  6205. struct scsi_device *sdev;
  6206. struct pqi_scsi_dev *device;
  6207. unsigned long flags;
  6208. u64 write_stream_cnt;
  6209. int cpu;
  6210. sdev = to_scsi_device(dev);
  6211. ctrl_info = shost_to_hba(sdev->host);
  6212. if (pqi_ctrl_offline(ctrl_info))
  6213. return -ENODEV;
  6214. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  6215. device = sdev->hostdata;
  6216. if (!device) {
  6217. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6218. return -ENODEV;
  6219. }
  6220. write_stream_cnt = 0;
  6221. if (device->raid_io_stats) {
  6222. for_each_online_cpu(cpu) {
  6223. write_stream_cnt += per_cpu_ptr(device->raid_io_stats, cpu)->write_stream_cnt;
  6224. }
  6225. }
  6226. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6227. return scnprintf(buffer, PAGE_SIZE, "0x%llx\n", write_stream_cnt);
  6228. }
  6229. static DEVICE_ATTR(lunid, 0444, pqi_lunid_show, NULL);
  6230. static DEVICE_ATTR(unique_id, 0444, pqi_unique_id_show, NULL);
  6231. static DEVICE_ATTR(path_info, 0444, pqi_path_info_show, NULL);
  6232. static DEVICE_ATTR(sas_address, 0444, pqi_sas_address_show, NULL);
  6233. static DEVICE_ATTR(ssd_smart_path_enabled, 0444, pqi_ssd_smart_path_enabled_show, NULL);
  6234. static DEVICE_ATTR(raid_level, 0444, pqi_raid_level_show, NULL);
  6235. static DEVICE_ATTR(raid_bypass_cnt, 0444, pqi_raid_bypass_cnt_show, NULL);
  6236. static DEVICE_ATTR(sas_ncq_prio_enable, 0644,
  6237. pqi_sas_ncq_prio_enable_show, pqi_sas_ncq_prio_enable_store);
  6238. static DEVICE_ATTR(numa_node, 0444, pqi_numa_node_show, NULL);
  6239. static DEVICE_ATTR(write_stream_cnt, 0444, pqi_write_stream_cnt_show, NULL);
  6240. static struct attribute *pqi_sdev_attrs[] = {
  6241. &dev_attr_lunid.attr,
  6242. &dev_attr_unique_id.attr,
  6243. &dev_attr_path_info.attr,
  6244. &dev_attr_sas_address.attr,
  6245. &dev_attr_ssd_smart_path_enabled.attr,
  6246. &dev_attr_raid_level.attr,
  6247. &dev_attr_raid_bypass_cnt.attr,
  6248. &dev_attr_sas_ncq_prio_enable.attr,
  6249. &dev_attr_numa_node.attr,
  6250. &dev_attr_write_stream_cnt.attr,
  6251. NULL
  6252. };
  6253. ATTRIBUTE_GROUPS(pqi_sdev);
  6254. static const struct scsi_host_template pqi_driver_template = {
  6255. .module = THIS_MODULE,
  6256. .name = DRIVER_NAME_SHORT,
  6257. .proc_name = DRIVER_NAME_SHORT,
  6258. .queuecommand = pqi_scsi_queue_command,
  6259. .scan_start = pqi_scan_start,
  6260. .scan_finished = pqi_scan_finished,
  6261. .this_id = -1,
  6262. .eh_device_reset_handler = pqi_eh_device_reset_handler,
  6263. .eh_abort_handler = pqi_eh_abort_handler,
  6264. .ioctl = pqi_ioctl,
  6265. .slave_alloc = pqi_slave_alloc,
  6266. .slave_configure = pqi_slave_configure,
  6267. .slave_destroy = pqi_slave_destroy,
  6268. .map_queues = pqi_map_queues,
  6269. .sdev_groups = pqi_sdev_groups,
  6270. .shost_groups = pqi_shost_groups,
  6271. .cmd_size = sizeof(struct pqi_cmd_priv),
  6272. };
  6273. static int pqi_register_scsi(struct pqi_ctrl_info *ctrl_info)
  6274. {
  6275. int rc;
  6276. struct Scsi_Host *shost;
  6277. shost = scsi_host_alloc(&pqi_driver_template, sizeof(ctrl_info));
  6278. if (!shost) {
  6279. dev_err(&ctrl_info->pci_dev->dev, "scsi_host_alloc failed\n");
  6280. return -ENOMEM;
  6281. }
  6282. shost->io_port = 0;
  6283. shost->n_io_port = 0;
  6284. shost->this_id = -1;
  6285. shost->max_channel = PQI_MAX_BUS;
  6286. shost->max_cmd_len = MAX_COMMAND_SIZE;
  6287. shost->max_lun = PQI_MAX_LUNS_PER_DEVICE;
  6288. shost->max_id = ~0;
  6289. shost->max_sectors = ctrl_info->max_sectors;
  6290. shost->can_queue = ctrl_info->scsi_ml_can_queue;
  6291. shost->cmd_per_lun = shost->can_queue;
  6292. shost->sg_tablesize = ctrl_info->sg_tablesize;
  6293. shost->transportt = pqi_sas_transport_template;
  6294. shost->irq = pci_irq_vector(ctrl_info->pci_dev, 0);
  6295. shost->unique_id = shost->irq;
  6296. shost->nr_hw_queues = ctrl_info->num_queue_groups;
  6297. shost->host_tagset = 1;
  6298. shost->hostdata[0] = (unsigned long)ctrl_info;
  6299. rc = scsi_add_host(shost, &ctrl_info->pci_dev->dev);
  6300. if (rc) {
  6301. dev_err(&ctrl_info->pci_dev->dev, "scsi_add_host failed\n");
  6302. goto free_host;
  6303. }
  6304. rc = pqi_add_sas_host(shost, ctrl_info);
  6305. if (rc) {
  6306. dev_err(&ctrl_info->pci_dev->dev, "add SAS host failed\n");
  6307. goto remove_host;
  6308. }
  6309. ctrl_info->scsi_host = shost;
  6310. return 0;
  6311. remove_host:
  6312. scsi_remove_host(shost);
  6313. free_host:
  6314. scsi_host_put(shost);
  6315. return rc;
  6316. }
  6317. static void pqi_unregister_scsi(struct pqi_ctrl_info *ctrl_info)
  6318. {
  6319. struct Scsi_Host *shost;
  6320. pqi_delete_sas_host(ctrl_info);
  6321. shost = ctrl_info->scsi_host;
  6322. if (!shost)
  6323. return;
  6324. scsi_remove_host(shost);
  6325. scsi_host_put(shost);
  6326. }
  6327. static int pqi_wait_for_pqi_reset_completion(struct pqi_ctrl_info *ctrl_info)
  6328. {
  6329. int rc = 0;
  6330. struct pqi_device_registers __iomem *pqi_registers;
  6331. unsigned long timeout;
  6332. unsigned int timeout_msecs;
  6333. union pqi_reset_register reset_reg;
  6334. pqi_registers = ctrl_info->pqi_registers;
  6335. timeout_msecs = readw(&pqi_registers->max_reset_timeout) * 100;
  6336. timeout = msecs_to_jiffies(timeout_msecs) + jiffies;
  6337. while (1) {
  6338. msleep(PQI_RESET_POLL_INTERVAL_MSECS);
  6339. reset_reg.all_bits = readl(&pqi_registers->device_reset);
  6340. if (reset_reg.bits.reset_action == PQI_RESET_ACTION_COMPLETED)
  6341. break;
  6342. if (!sis_is_firmware_running(ctrl_info)) {
  6343. rc = -ENXIO;
  6344. break;
  6345. }
  6346. if (time_after(jiffies, timeout)) {
  6347. rc = -ETIMEDOUT;
  6348. break;
  6349. }
  6350. }
  6351. return rc;
  6352. }
  6353. static int pqi_reset(struct pqi_ctrl_info *ctrl_info)
  6354. {
  6355. int rc;
  6356. union pqi_reset_register reset_reg;
  6357. if (ctrl_info->pqi_reset_quiesce_supported) {
  6358. rc = sis_pqi_reset_quiesce(ctrl_info);
  6359. if (rc) {
  6360. dev_err(&ctrl_info->pci_dev->dev,
  6361. "PQI reset failed during quiesce with error %d\n", rc);
  6362. return rc;
  6363. }
  6364. }
  6365. reset_reg.all_bits = 0;
  6366. reset_reg.bits.reset_type = PQI_RESET_TYPE_HARD_RESET;
  6367. reset_reg.bits.reset_action = PQI_RESET_ACTION_RESET;
  6368. writel(reset_reg.all_bits, &ctrl_info->pqi_registers->device_reset);
  6369. rc = pqi_wait_for_pqi_reset_completion(ctrl_info);
  6370. if (rc)
  6371. dev_err(&ctrl_info->pci_dev->dev,
  6372. "PQI reset failed with error %d\n", rc);
  6373. return rc;
  6374. }
  6375. static int pqi_get_ctrl_serial_number(struct pqi_ctrl_info *ctrl_info)
  6376. {
  6377. int rc;
  6378. struct bmic_sense_subsystem_info *sense_info;
  6379. sense_info = kzalloc(sizeof(*sense_info), GFP_KERNEL);
  6380. if (!sense_info)
  6381. return -ENOMEM;
  6382. rc = pqi_sense_subsystem_info(ctrl_info, sense_info);
  6383. if (rc)
  6384. goto out;
  6385. memcpy(ctrl_info->serial_number, sense_info->ctrl_serial_number,
  6386. sizeof(sense_info->ctrl_serial_number));
  6387. ctrl_info->serial_number[sizeof(sense_info->ctrl_serial_number)] = '\0';
  6388. out:
  6389. kfree(sense_info);
  6390. return rc;
  6391. }
  6392. static int pqi_get_ctrl_product_details(struct pqi_ctrl_info *ctrl_info)
  6393. {
  6394. int rc;
  6395. struct bmic_identify_controller *identify;
  6396. identify = kmalloc(sizeof(*identify), GFP_KERNEL);
  6397. if (!identify)
  6398. return -ENOMEM;
  6399. rc = pqi_identify_controller(ctrl_info, identify);
  6400. if (rc)
  6401. goto out;
  6402. if (get_unaligned_le32(&identify->extra_controller_flags) &
  6403. BMIC_IDENTIFY_EXTRA_FLAGS_LONG_FW_VERSION_SUPPORTED) {
  6404. memcpy(ctrl_info->firmware_version,
  6405. identify->firmware_version_long,
  6406. sizeof(identify->firmware_version_long));
  6407. } else {
  6408. memcpy(ctrl_info->firmware_version,
  6409. identify->firmware_version_short,
  6410. sizeof(identify->firmware_version_short));
  6411. ctrl_info->firmware_version
  6412. [sizeof(identify->firmware_version_short)] = '\0';
  6413. snprintf(ctrl_info->firmware_version +
  6414. strlen(ctrl_info->firmware_version),
  6415. sizeof(ctrl_info->firmware_version) -
  6416. sizeof(identify->firmware_version_short),
  6417. "-%u",
  6418. get_unaligned_le16(&identify->firmware_build_number));
  6419. }
  6420. memcpy(ctrl_info->model, identify->product_id,
  6421. sizeof(identify->product_id));
  6422. ctrl_info->model[sizeof(identify->product_id)] = '\0';
  6423. memcpy(ctrl_info->vendor, identify->vendor_id,
  6424. sizeof(identify->vendor_id));
  6425. ctrl_info->vendor[sizeof(identify->vendor_id)] = '\0';
  6426. dev_info(&ctrl_info->pci_dev->dev,
  6427. "Firmware version: %s\n", ctrl_info->firmware_version);
  6428. out:
  6429. kfree(identify);
  6430. return rc;
  6431. }
  6432. struct pqi_config_table_section_info {
  6433. struct pqi_ctrl_info *ctrl_info;
  6434. void *section;
  6435. u32 section_offset;
  6436. void __iomem *section_iomem_addr;
  6437. };
  6438. static inline bool pqi_is_firmware_feature_supported(
  6439. struct pqi_config_table_firmware_features *firmware_features,
  6440. unsigned int bit_position)
  6441. {
  6442. unsigned int byte_index;
  6443. byte_index = bit_position / BITS_PER_BYTE;
  6444. if (byte_index >= le16_to_cpu(firmware_features->num_elements))
  6445. return false;
  6446. return firmware_features->features_supported[byte_index] &
  6447. (1 << (bit_position % BITS_PER_BYTE)) ? true : false;
  6448. }
  6449. static inline bool pqi_is_firmware_feature_enabled(
  6450. struct pqi_config_table_firmware_features *firmware_features,
  6451. void __iomem *firmware_features_iomem_addr,
  6452. unsigned int bit_position)
  6453. {
  6454. unsigned int byte_index;
  6455. u8 __iomem *features_enabled_iomem_addr;
  6456. byte_index = (bit_position / BITS_PER_BYTE) +
  6457. (le16_to_cpu(firmware_features->num_elements) * 2);
  6458. features_enabled_iomem_addr = firmware_features_iomem_addr +
  6459. offsetof(struct pqi_config_table_firmware_features,
  6460. features_supported) + byte_index;
  6461. return *((__force u8 *)features_enabled_iomem_addr) &
  6462. (1 << (bit_position % BITS_PER_BYTE)) ? true : false;
  6463. }
  6464. static inline void pqi_request_firmware_feature(
  6465. struct pqi_config_table_firmware_features *firmware_features,
  6466. unsigned int bit_position)
  6467. {
  6468. unsigned int byte_index;
  6469. byte_index = (bit_position / BITS_PER_BYTE) +
  6470. le16_to_cpu(firmware_features->num_elements);
  6471. firmware_features->features_supported[byte_index] |=
  6472. (1 << (bit_position % BITS_PER_BYTE));
  6473. }
  6474. static int pqi_config_table_update(struct pqi_ctrl_info *ctrl_info,
  6475. u16 first_section, u16 last_section)
  6476. {
  6477. struct pqi_vendor_general_request request;
  6478. memset(&request, 0, sizeof(request));
  6479. request.header.iu_type = PQI_REQUEST_IU_VENDOR_GENERAL;
  6480. put_unaligned_le16(sizeof(request) - PQI_REQUEST_HEADER_LENGTH,
  6481. &request.header.iu_length);
  6482. put_unaligned_le16(PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE,
  6483. &request.function_code);
  6484. put_unaligned_le16(first_section,
  6485. &request.data.config_table_update.first_section);
  6486. put_unaligned_le16(last_section,
  6487. &request.data.config_table_update.last_section);
  6488. return pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, NULL);
  6489. }
  6490. static int pqi_enable_firmware_features(struct pqi_ctrl_info *ctrl_info,
  6491. struct pqi_config_table_firmware_features *firmware_features,
  6492. void __iomem *firmware_features_iomem_addr)
  6493. {
  6494. void *features_requested;
  6495. void __iomem *features_requested_iomem_addr;
  6496. void __iomem *host_max_known_feature_iomem_addr;
  6497. features_requested = firmware_features->features_supported +
  6498. le16_to_cpu(firmware_features->num_elements);
  6499. features_requested_iomem_addr = firmware_features_iomem_addr +
  6500. (features_requested - (void *)firmware_features);
  6501. memcpy_toio(features_requested_iomem_addr, features_requested,
  6502. le16_to_cpu(firmware_features->num_elements));
  6503. if (pqi_is_firmware_feature_supported(firmware_features,
  6504. PQI_FIRMWARE_FEATURE_MAX_KNOWN_FEATURE)) {
  6505. host_max_known_feature_iomem_addr =
  6506. features_requested_iomem_addr +
  6507. (le16_to_cpu(firmware_features->num_elements) * 2) +
  6508. sizeof(__le16);
  6509. writeb(PQI_FIRMWARE_FEATURE_MAXIMUM & 0xFF, host_max_known_feature_iomem_addr);
  6510. writeb((PQI_FIRMWARE_FEATURE_MAXIMUM & 0xFF00) >> 8, host_max_known_feature_iomem_addr + 1);
  6511. }
  6512. return pqi_config_table_update(ctrl_info,
  6513. PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES,
  6514. PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES);
  6515. }
  6516. struct pqi_firmware_feature {
  6517. char *feature_name;
  6518. unsigned int feature_bit;
  6519. bool supported;
  6520. bool enabled;
  6521. void (*feature_status)(struct pqi_ctrl_info *ctrl_info,
  6522. struct pqi_firmware_feature *firmware_feature);
  6523. };
  6524. static void pqi_firmware_feature_status(struct pqi_ctrl_info *ctrl_info,
  6525. struct pqi_firmware_feature *firmware_feature)
  6526. {
  6527. if (!firmware_feature->supported) {
  6528. dev_info(&ctrl_info->pci_dev->dev, "%s not supported by controller\n",
  6529. firmware_feature->feature_name);
  6530. return;
  6531. }
  6532. if (firmware_feature->enabled) {
  6533. dev_info(&ctrl_info->pci_dev->dev,
  6534. "%s enabled\n", firmware_feature->feature_name);
  6535. return;
  6536. }
  6537. dev_err(&ctrl_info->pci_dev->dev, "failed to enable %s\n",
  6538. firmware_feature->feature_name);
  6539. }
  6540. static void pqi_ctrl_update_feature_flags(struct pqi_ctrl_info *ctrl_info,
  6541. struct pqi_firmware_feature *firmware_feature)
  6542. {
  6543. switch (firmware_feature->feature_bit) {
  6544. case PQI_FIRMWARE_FEATURE_RAID_1_WRITE_BYPASS:
  6545. ctrl_info->enable_r1_writes = firmware_feature->enabled;
  6546. break;
  6547. case PQI_FIRMWARE_FEATURE_RAID_5_WRITE_BYPASS:
  6548. ctrl_info->enable_r5_writes = firmware_feature->enabled;
  6549. break;
  6550. case PQI_FIRMWARE_FEATURE_RAID_6_WRITE_BYPASS:
  6551. ctrl_info->enable_r6_writes = firmware_feature->enabled;
  6552. break;
  6553. case PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE:
  6554. ctrl_info->soft_reset_handshake_supported =
  6555. firmware_feature->enabled &&
  6556. pqi_read_soft_reset_status(ctrl_info);
  6557. break;
  6558. case PQI_FIRMWARE_FEATURE_RAID_IU_TIMEOUT:
  6559. ctrl_info->raid_iu_timeout_supported = firmware_feature->enabled;
  6560. break;
  6561. case PQI_FIRMWARE_FEATURE_TMF_IU_TIMEOUT:
  6562. ctrl_info->tmf_iu_timeout_supported = firmware_feature->enabled;
  6563. break;
  6564. case PQI_FIRMWARE_FEATURE_FW_TRIAGE:
  6565. ctrl_info->firmware_triage_supported = firmware_feature->enabled;
  6566. pqi_save_fw_triage_setting(ctrl_info, firmware_feature->enabled);
  6567. break;
  6568. case PQI_FIRMWARE_FEATURE_RPL_EXTENDED_FORMAT_4_5:
  6569. ctrl_info->rpl_extended_format_4_5_supported = firmware_feature->enabled;
  6570. break;
  6571. case PQI_FIRMWARE_FEATURE_MULTI_LUN_DEVICE_SUPPORT:
  6572. ctrl_info->multi_lun_device_supported = firmware_feature->enabled;
  6573. break;
  6574. case PQI_FIRMWARE_FEATURE_CTRL_LOGGING:
  6575. ctrl_info->ctrl_logging_supported = firmware_feature->enabled;
  6576. break;
  6577. }
  6578. pqi_firmware_feature_status(ctrl_info, firmware_feature);
  6579. }
  6580. static inline void pqi_firmware_feature_update(struct pqi_ctrl_info *ctrl_info,
  6581. struct pqi_firmware_feature *firmware_feature)
  6582. {
  6583. if (firmware_feature->feature_status)
  6584. firmware_feature->feature_status(ctrl_info, firmware_feature);
  6585. }
  6586. static DEFINE_MUTEX(pqi_firmware_features_mutex);
  6587. static struct pqi_firmware_feature pqi_firmware_features[] = {
  6588. {
  6589. .feature_name = "Online Firmware Activation",
  6590. .feature_bit = PQI_FIRMWARE_FEATURE_OFA,
  6591. .feature_status = pqi_firmware_feature_status,
  6592. },
  6593. {
  6594. .feature_name = "Serial Management Protocol",
  6595. .feature_bit = PQI_FIRMWARE_FEATURE_SMP,
  6596. .feature_status = pqi_firmware_feature_status,
  6597. },
  6598. {
  6599. .feature_name = "Maximum Known Feature",
  6600. .feature_bit = PQI_FIRMWARE_FEATURE_MAX_KNOWN_FEATURE,
  6601. .feature_status = pqi_firmware_feature_status,
  6602. },
  6603. {
  6604. .feature_name = "RAID 0 Read Bypass",
  6605. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_0_READ_BYPASS,
  6606. .feature_status = pqi_firmware_feature_status,
  6607. },
  6608. {
  6609. .feature_name = "RAID 1 Read Bypass",
  6610. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_1_READ_BYPASS,
  6611. .feature_status = pqi_firmware_feature_status,
  6612. },
  6613. {
  6614. .feature_name = "RAID 5 Read Bypass",
  6615. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_5_READ_BYPASS,
  6616. .feature_status = pqi_firmware_feature_status,
  6617. },
  6618. {
  6619. .feature_name = "RAID 6 Read Bypass",
  6620. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_6_READ_BYPASS,
  6621. .feature_status = pqi_firmware_feature_status,
  6622. },
  6623. {
  6624. .feature_name = "RAID 0 Write Bypass",
  6625. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_0_WRITE_BYPASS,
  6626. .feature_status = pqi_firmware_feature_status,
  6627. },
  6628. {
  6629. .feature_name = "RAID 1 Write Bypass",
  6630. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_1_WRITE_BYPASS,
  6631. .feature_status = pqi_ctrl_update_feature_flags,
  6632. },
  6633. {
  6634. .feature_name = "RAID 5 Write Bypass",
  6635. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_5_WRITE_BYPASS,
  6636. .feature_status = pqi_ctrl_update_feature_flags,
  6637. },
  6638. {
  6639. .feature_name = "RAID 6 Write Bypass",
  6640. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_6_WRITE_BYPASS,
  6641. .feature_status = pqi_ctrl_update_feature_flags,
  6642. },
  6643. {
  6644. .feature_name = "New Soft Reset Handshake",
  6645. .feature_bit = PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE,
  6646. .feature_status = pqi_ctrl_update_feature_flags,
  6647. },
  6648. {
  6649. .feature_name = "RAID IU Timeout",
  6650. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_IU_TIMEOUT,
  6651. .feature_status = pqi_ctrl_update_feature_flags,
  6652. },
  6653. {
  6654. .feature_name = "TMF IU Timeout",
  6655. .feature_bit = PQI_FIRMWARE_FEATURE_TMF_IU_TIMEOUT,
  6656. .feature_status = pqi_ctrl_update_feature_flags,
  6657. },
  6658. {
  6659. .feature_name = "RAID Bypass on encrypted logical volumes on NVMe",
  6660. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_BYPASS_ON_ENCRYPTED_NVME,
  6661. .feature_status = pqi_firmware_feature_status,
  6662. },
  6663. {
  6664. .feature_name = "Firmware Triage",
  6665. .feature_bit = PQI_FIRMWARE_FEATURE_FW_TRIAGE,
  6666. .feature_status = pqi_ctrl_update_feature_flags,
  6667. },
  6668. {
  6669. .feature_name = "RPL Extended Formats 4 and 5",
  6670. .feature_bit = PQI_FIRMWARE_FEATURE_RPL_EXTENDED_FORMAT_4_5,
  6671. .feature_status = pqi_ctrl_update_feature_flags,
  6672. },
  6673. {
  6674. .feature_name = "Multi-LUN Target",
  6675. .feature_bit = PQI_FIRMWARE_FEATURE_MULTI_LUN_DEVICE_SUPPORT,
  6676. .feature_status = pqi_ctrl_update_feature_flags,
  6677. },
  6678. {
  6679. .feature_name = "Controller Data Logging",
  6680. .feature_bit = PQI_FIRMWARE_FEATURE_CTRL_LOGGING,
  6681. .feature_status = pqi_ctrl_update_feature_flags,
  6682. },
  6683. };
  6684. static void pqi_process_firmware_features(
  6685. struct pqi_config_table_section_info *section_info)
  6686. {
  6687. int rc;
  6688. struct pqi_ctrl_info *ctrl_info;
  6689. struct pqi_config_table_firmware_features *firmware_features;
  6690. void __iomem *firmware_features_iomem_addr;
  6691. unsigned int i;
  6692. unsigned int num_features_supported;
  6693. ctrl_info = section_info->ctrl_info;
  6694. firmware_features = section_info->section;
  6695. firmware_features_iomem_addr = section_info->section_iomem_addr;
  6696. for (i = 0, num_features_supported = 0;
  6697. i < ARRAY_SIZE(pqi_firmware_features); i++) {
  6698. if (pqi_is_firmware_feature_supported(firmware_features,
  6699. pqi_firmware_features[i].feature_bit)) {
  6700. pqi_firmware_features[i].supported = true;
  6701. num_features_supported++;
  6702. } else {
  6703. pqi_firmware_feature_update(ctrl_info,
  6704. &pqi_firmware_features[i]);
  6705. }
  6706. }
  6707. if (num_features_supported == 0)
  6708. return;
  6709. for (i = 0; i < ARRAY_SIZE(pqi_firmware_features); i++) {
  6710. if (!pqi_firmware_features[i].supported)
  6711. continue;
  6712. pqi_request_firmware_feature(firmware_features,
  6713. pqi_firmware_features[i].feature_bit);
  6714. }
  6715. rc = pqi_enable_firmware_features(ctrl_info, firmware_features,
  6716. firmware_features_iomem_addr);
  6717. if (rc) {
  6718. dev_err(&ctrl_info->pci_dev->dev,
  6719. "failed to enable firmware features in PQI configuration table\n");
  6720. for (i = 0; i < ARRAY_SIZE(pqi_firmware_features); i++) {
  6721. if (!pqi_firmware_features[i].supported)
  6722. continue;
  6723. pqi_firmware_feature_update(ctrl_info,
  6724. &pqi_firmware_features[i]);
  6725. }
  6726. return;
  6727. }
  6728. for (i = 0; i < ARRAY_SIZE(pqi_firmware_features); i++) {
  6729. if (!pqi_firmware_features[i].supported)
  6730. continue;
  6731. if (pqi_is_firmware_feature_enabled(firmware_features,
  6732. firmware_features_iomem_addr,
  6733. pqi_firmware_features[i].feature_bit)) {
  6734. pqi_firmware_features[i].enabled = true;
  6735. }
  6736. pqi_firmware_feature_update(ctrl_info,
  6737. &pqi_firmware_features[i]);
  6738. }
  6739. }
  6740. static void pqi_init_firmware_features(void)
  6741. {
  6742. unsigned int i;
  6743. for (i = 0; i < ARRAY_SIZE(pqi_firmware_features); i++) {
  6744. pqi_firmware_features[i].supported = false;
  6745. pqi_firmware_features[i].enabled = false;
  6746. }
  6747. }
  6748. static void pqi_process_firmware_features_section(
  6749. struct pqi_config_table_section_info *section_info)
  6750. {
  6751. mutex_lock(&pqi_firmware_features_mutex);
  6752. pqi_init_firmware_features();
  6753. pqi_process_firmware_features(section_info);
  6754. mutex_unlock(&pqi_firmware_features_mutex);
  6755. }
  6756. /*
  6757. * Reset all controller settings that can be initialized during the processing
  6758. * of the PQI Configuration Table.
  6759. */
  6760. static void pqi_ctrl_reset_config(struct pqi_ctrl_info *ctrl_info)
  6761. {
  6762. ctrl_info->heartbeat_counter = NULL;
  6763. ctrl_info->soft_reset_status = NULL;
  6764. ctrl_info->soft_reset_handshake_supported = false;
  6765. ctrl_info->enable_r1_writes = false;
  6766. ctrl_info->enable_r5_writes = false;
  6767. ctrl_info->enable_r6_writes = false;
  6768. ctrl_info->raid_iu_timeout_supported = false;
  6769. ctrl_info->tmf_iu_timeout_supported = false;
  6770. ctrl_info->firmware_triage_supported = false;
  6771. ctrl_info->rpl_extended_format_4_5_supported = false;
  6772. ctrl_info->multi_lun_device_supported = false;
  6773. ctrl_info->ctrl_logging_supported = false;
  6774. }
  6775. static int pqi_process_config_table(struct pqi_ctrl_info *ctrl_info)
  6776. {
  6777. u32 table_length;
  6778. u32 section_offset;
  6779. bool firmware_feature_section_present;
  6780. void __iomem *table_iomem_addr;
  6781. struct pqi_config_table *config_table;
  6782. struct pqi_config_table_section_header *section;
  6783. struct pqi_config_table_section_info section_info;
  6784. struct pqi_config_table_section_info feature_section_info = {0};
  6785. table_length = ctrl_info->config_table_length;
  6786. if (table_length == 0)
  6787. return 0;
  6788. config_table = kmalloc(table_length, GFP_KERNEL);
  6789. if (!config_table) {
  6790. dev_err(&ctrl_info->pci_dev->dev,
  6791. "failed to allocate memory for PQI configuration table\n");
  6792. return -ENOMEM;
  6793. }
  6794. /*
  6795. * Copy the config table contents from I/O memory space into the
  6796. * temporary buffer.
  6797. */
  6798. table_iomem_addr = ctrl_info->iomem_base + ctrl_info->config_table_offset;
  6799. memcpy_fromio(config_table, table_iomem_addr, table_length);
  6800. firmware_feature_section_present = false;
  6801. section_info.ctrl_info = ctrl_info;
  6802. section_offset = get_unaligned_le32(&config_table->first_section_offset);
  6803. while (section_offset) {
  6804. section = (void *)config_table + section_offset;
  6805. section_info.section = section;
  6806. section_info.section_offset = section_offset;
  6807. section_info.section_iomem_addr = table_iomem_addr + section_offset;
  6808. switch (get_unaligned_le16(&section->section_id)) {
  6809. case PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES:
  6810. firmware_feature_section_present = true;
  6811. feature_section_info = section_info;
  6812. break;
  6813. case PQI_CONFIG_TABLE_SECTION_HEARTBEAT:
  6814. if (pqi_disable_heartbeat)
  6815. dev_warn(&ctrl_info->pci_dev->dev,
  6816. "heartbeat disabled by module parameter\n");
  6817. else
  6818. ctrl_info->heartbeat_counter =
  6819. table_iomem_addr +
  6820. section_offset +
  6821. offsetof(struct pqi_config_table_heartbeat,
  6822. heartbeat_counter);
  6823. break;
  6824. case PQI_CONFIG_TABLE_SECTION_SOFT_RESET:
  6825. ctrl_info->soft_reset_status =
  6826. table_iomem_addr +
  6827. section_offset +
  6828. offsetof(struct pqi_config_table_soft_reset,
  6829. soft_reset_status);
  6830. break;
  6831. }
  6832. section_offset = get_unaligned_le16(&section->next_section_offset);
  6833. }
  6834. /*
  6835. * We process the firmware feature section after all other sections
  6836. * have been processed so that the feature bit callbacks can take
  6837. * into account the settings configured by other sections.
  6838. */
  6839. if (firmware_feature_section_present)
  6840. pqi_process_firmware_features_section(&feature_section_info);
  6841. kfree(config_table);
  6842. return 0;
  6843. }
  6844. /* Switches the controller from PQI mode back into SIS mode. */
  6845. static int pqi_revert_to_sis_mode(struct pqi_ctrl_info *ctrl_info)
  6846. {
  6847. int rc;
  6848. pqi_change_irq_mode(ctrl_info, IRQ_MODE_NONE);
  6849. rc = pqi_reset(ctrl_info);
  6850. if (rc)
  6851. return rc;
  6852. rc = sis_reenable_sis_mode(ctrl_info);
  6853. if (rc) {
  6854. dev_err(&ctrl_info->pci_dev->dev,
  6855. "re-enabling SIS mode failed with error %d\n", rc);
  6856. return rc;
  6857. }
  6858. pqi_save_ctrl_mode(ctrl_info, SIS_MODE);
  6859. return 0;
  6860. }
  6861. /*
  6862. * If the controller isn't already in SIS mode, this function forces it into
  6863. * SIS mode.
  6864. */
  6865. static int pqi_force_sis_mode(struct pqi_ctrl_info *ctrl_info)
  6866. {
  6867. if (!sis_is_firmware_running(ctrl_info))
  6868. return -ENXIO;
  6869. if (pqi_get_ctrl_mode(ctrl_info) == SIS_MODE)
  6870. return 0;
  6871. if (sis_is_kernel_up(ctrl_info)) {
  6872. pqi_save_ctrl_mode(ctrl_info, SIS_MODE);
  6873. return 0;
  6874. }
  6875. return pqi_revert_to_sis_mode(ctrl_info);
  6876. }
  6877. static void pqi_perform_lockup_action(void)
  6878. {
  6879. switch (pqi_lockup_action) {
  6880. case PANIC:
  6881. panic("FATAL: Smart Family Controller lockup detected");
  6882. break;
  6883. case REBOOT:
  6884. emergency_restart();
  6885. break;
  6886. case NONE:
  6887. default:
  6888. break;
  6889. }
  6890. }
  6891. #define PQI_CTRL_LOG_TOTAL_SIZE (4 * 1024 * 1024)
  6892. #define PQI_CTRL_LOG_MIN_SIZE (PQI_CTRL_LOG_TOTAL_SIZE / PQI_HOST_MAX_SG_DESCRIPTORS)
  6893. static int pqi_ctrl_init(struct pqi_ctrl_info *ctrl_info)
  6894. {
  6895. int rc;
  6896. u32 product_id;
  6897. if (reset_devices) {
  6898. if (pqi_is_fw_triage_supported(ctrl_info)) {
  6899. rc = sis_wait_for_fw_triage_completion(ctrl_info);
  6900. if (rc)
  6901. return rc;
  6902. }
  6903. if (sis_is_ctrl_logging_supported(ctrl_info)) {
  6904. sis_notify_kdump(ctrl_info);
  6905. rc = sis_wait_for_ctrl_logging_completion(ctrl_info);
  6906. if (rc)
  6907. return rc;
  6908. }
  6909. sis_soft_reset(ctrl_info);
  6910. ssleep(PQI_POST_RESET_DELAY_SECS);
  6911. } else {
  6912. rc = pqi_force_sis_mode(ctrl_info);
  6913. if (rc)
  6914. return rc;
  6915. }
  6916. /*
  6917. * Wait until the controller is ready to start accepting SIS
  6918. * commands.
  6919. */
  6920. rc = sis_wait_for_ctrl_ready(ctrl_info);
  6921. if (rc) {
  6922. if (reset_devices) {
  6923. dev_err(&ctrl_info->pci_dev->dev,
  6924. "kdump init failed with error %d\n", rc);
  6925. pqi_lockup_action = REBOOT;
  6926. pqi_perform_lockup_action();
  6927. }
  6928. return rc;
  6929. }
  6930. /*
  6931. * Get the controller properties. This allows us to determine
  6932. * whether or not it supports PQI mode.
  6933. */
  6934. rc = sis_get_ctrl_properties(ctrl_info);
  6935. if (rc) {
  6936. dev_err(&ctrl_info->pci_dev->dev,
  6937. "error obtaining controller properties\n");
  6938. return rc;
  6939. }
  6940. rc = sis_get_pqi_capabilities(ctrl_info);
  6941. if (rc) {
  6942. dev_err(&ctrl_info->pci_dev->dev,
  6943. "error obtaining controller capabilities\n");
  6944. return rc;
  6945. }
  6946. product_id = sis_get_product_id(ctrl_info);
  6947. ctrl_info->product_id = (u8)product_id;
  6948. ctrl_info->product_revision = (u8)(product_id >> 8);
  6949. if (reset_devices) {
  6950. if (ctrl_info->max_outstanding_requests >
  6951. PQI_MAX_OUTSTANDING_REQUESTS_KDUMP)
  6952. ctrl_info->max_outstanding_requests =
  6953. PQI_MAX_OUTSTANDING_REQUESTS_KDUMP;
  6954. } else {
  6955. if (ctrl_info->max_outstanding_requests >
  6956. PQI_MAX_OUTSTANDING_REQUESTS)
  6957. ctrl_info->max_outstanding_requests =
  6958. PQI_MAX_OUTSTANDING_REQUESTS;
  6959. }
  6960. pqi_calculate_io_resources(ctrl_info);
  6961. rc = pqi_alloc_error_buffer(ctrl_info);
  6962. if (rc) {
  6963. dev_err(&ctrl_info->pci_dev->dev,
  6964. "failed to allocate PQI error buffer\n");
  6965. return rc;
  6966. }
  6967. /*
  6968. * If the function we are about to call succeeds, the
  6969. * controller will transition from legacy SIS mode
  6970. * into PQI mode.
  6971. */
  6972. rc = sis_init_base_struct_addr(ctrl_info);
  6973. if (rc) {
  6974. dev_err(&ctrl_info->pci_dev->dev,
  6975. "error initializing PQI mode\n");
  6976. return rc;
  6977. }
  6978. /* Wait for the controller to complete the SIS -> PQI transition. */
  6979. rc = pqi_wait_for_pqi_mode_ready(ctrl_info);
  6980. if (rc) {
  6981. dev_err(&ctrl_info->pci_dev->dev,
  6982. "transition to PQI mode failed\n");
  6983. return rc;
  6984. }
  6985. /* From here on, we are running in PQI mode. */
  6986. ctrl_info->pqi_mode_enabled = true;
  6987. pqi_save_ctrl_mode(ctrl_info, PQI_MODE);
  6988. rc = pqi_alloc_admin_queues(ctrl_info);
  6989. if (rc) {
  6990. dev_err(&ctrl_info->pci_dev->dev,
  6991. "failed to allocate admin queues\n");
  6992. return rc;
  6993. }
  6994. rc = pqi_create_admin_queues(ctrl_info);
  6995. if (rc) {
  6996. dev_err(&ctrl_info->pci_dev->dev,
  6997. "error creating admin queues\n");
  6998. return rc;
  6999. }
  7000. rc = pqi_report_device_capability(ctrl_info);
  7001. if (rc) {
  7002. dev_err(&ctrl_info->pci_dev->dev,
  7003. "obtaining device capability failed\n");
  7004. return rc;
  7005. }
  7006. rc = pqi_validate_device_capability(ctrl_info);
  7007. if (rc)
  7008. return rc;
  7009. pqi_calculate_queue_resources(ctrl_info);
  7010. rc = pqi_enable_msix_interrupts(ctrl_info);
  7011. if (rc)
  7012. return rc;
  7013. if (ctrl_info->num_msix_vectors_enabled < ctrl_info->num_queue_groups) {
  7014. ctrl_info->max_msix_vectors =
  7015. ctrl_info->num_msix_vectors_enabled;
  7016. pqi_calculate_queue_resources(ctrl_info);
  7017. }
  7018. rc = pqi_alloc_io_resources(ctrl_info);
  7019. if (rc)
  7020. return rc;
  7021. rc = pqi_alloc_operational_queues(ctrl_info);
  7022. if (rc) {
  7023. dev_err(&ctrl_info->pci_dev->dev,
  7024. "failed to allocate operational queues\n");
  7025. return rc;
  7026. }
  7027. pqi_init_operational_queues(ctrl_info);
  7028. rc = pqi_create_queues(ctrl_info);
  7029. if (rc)
  7030. return rc;
  7031. rc = pqi_request_irqs(ctrl_info);
  7032. if (rc)
  7033. return rc;
  7034. pqi_change_irq_mode(ctrl_info, IRQ_MODE_MSIX);
  7035. ctrl_info->controller_online = true;
  7036. rc = pqi_process_config_table(ctrl_info);
  7037. if (rc)
  7038. return rc;
  7039. pqi_start_heartbeat_timer(ctrl_info);
  7040. if (ctrl_info->enable_r5_writes || ctrl_info->enable_r6_writes) {
  7041. rc = pqi_get_advanced_raid_bypass_config(ctrl_info);
  7042. if (rc) { /* Supported features not returned correctly. */
  7043. dev_err(&ctrl_info->pci_dev->dev,
  7044. "error obtaining advanced RAID bypass configuration\n");
  7045. return rc;
  7046. }
  7047. ctrl_info->ciss_report_log_flags |=
  7048. CISS_REPORT_LOG_FLAG_DRIVE_TYPE_MIX;
  7049. }
  7050. rc = pqi_enable_events(ctrl_info);
  7051. if (rc) {
  7052. dev_err(&ctrl_info->pci_dev->dev,
  7053. "error enabling events\n");
  7054. return rc;
  7055. }
  7056. /* Register with the SCSI subsystem. */
  7057. rc = pqi_register_scsi(ctrl_info);
  7058. if (rc)
  7059. return rc;
  7060. if (ctrl_info->ctrl_logging_supported && !reset_devices) {
  7061. pqi_host_setup_buffer(ctrl_info, &ctrl_info->ctrl_log_memory, PQI_CTRL_LOG_TOTAL_SIZE, PQI_CTRL_LOG_MIN_SIZE);
  7062. pqi_host_memory_update(ctrl_info, &ctrl_info->ctrl_log_memory, PQI_VENDOR_GENERAL_CTRL_LOG_MEMORY_UPDATE);
  7063. }
  7064. rc = pqi_get_ctrl_product_details(ctrl_info);
  7065. if (rc) {
  7066. dev_err(&ctrl_info->pci_dev->dev,
  7067. "error obtaining product details\n");
  7068. return rc;
  7069. }
  7070. rc = pqi_get_ctrl_serial_number(ctrl_info);
  7071. if (rc) {
  7072. dev_err(&ctrl_info->pci_dev->dev,
  7073. "error obtaining ctrl serial number\n");
  7074. return rc;
  7075. }
  7076. rc = pqi_set_diag_rescan(ctrl_info);
  7077. if (rc) {
  7078. dev_err(&ctrl_info->pci_dev->dev,
  7079. "error enabling multi-lun rescan\n");
  7080. return rc;
  7081. }
  7082. rc = pqi_write_driver_version_to_host_wellness(ctrl_info);
  7083. if (rc) {
  7084. dev_err(&ctrl_info->pci_dev->dev,
  7085. "error updating host wellness\n");
  7086. return rc;
  7087. }
  7088. pqi_schedule_update_time_worker(ctrl_info);
  7089. pqi_scan_scsi_devices(ctrl_info);
  7090. return 0;
  7091. }
  7092. static void pqi_reinit_queues(struct pqi_ctrl_info *ctrl_info)
  7093. {
  7094. unsigned int i;
  7095. struct pqi_admin_queues *admin_queues;
  7096. struct pqi_event_queue *event_queue;
  7097. admin_queues = &ctrl_info->admin_queues;
  7098. admin_queues->iq_pi_copy = 0;
  7099. admin_queues->oq_ci_copy = 0;
  7100. writel(0, admin_queues->oq_pi);
  7101. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  7102. ctrl_info->queue_groups[i].iq_pi_copy[RAID_PATH] = 0;
  7103. ctrl_info->queue_groups[i].iq_pi_copy[AIO_PATH] = 0;
  7104. ctrl_info->queue_groups[i].oq_ci_copy = 0;
  7105. writel(0, ctrl_info->queue_groups[i].iq_ci[RAID_PATH]);
  7106. writel(0, ctrl_info->queue_groups[i].iq_ci[AIO_PATH]);
  7107. writel(0, ctrl_info->queue_groups[i].oq_pi);
  7108. }
  7109. event_queue = &ctrl_info->event_queue;
  7110. writel(0, event_queue->oq_pi);
  7111. event_queue->oq_ci_copy = 0;
  7112. }
  7113. static int pqi_ctrl_init_resume(struct pqi_ctrl_info *ctrl_info)
  7114. {
  7115. int rc;
  7116. rc = pqi_force_sis_mode(ctrl_info);
  7117. if (rc)
  7118. return rc;
  7119. /*
  7120. * Wait until the controller is ready to start accepting SIS
  7121. * commands.
  7122. */
  7123. rc = sis_wait_for_ctrl_ready_resume(ctrl_info);
  7124. if (rc)
  7125. return rc;
  7126. /*
  7127. * Get the controller properties. This allows us to determine
  7128. * whether or not it supports PQI mode.
  7129. */
  7130. rc = sis_get_ctrl_properties(ctrl_info);
  7131. if (rc) {
  7132. dev_err(&ctrl_info->pci_dev->dev,
  7133. "error obtaining controller properties\n");
  7134. return rc;
  7135. }
  7136. rc = sis_get_pqi_capabilities(ctrl_info);
  7137. if (rc) {
  7138. dev_err(&ctrl_info->pci_dev->dev,
  7139. "error obtaining controller capabilities\n");
  7140. return rc;
  7141. }
  7142. /*
  7143. * If the function we are about to call succeeds, the
  7144. * controller will transition from legacy SIS mode
  7145. * into PQI mode.
  7146. */
  7147. rc = sis_init_base_struct_addr(ctrl_info);
  7148. if (rc) {
  7149. dev_err(&ctrl_info->pci_dev->dev,
  7150. "error initializing PQI mode\n");
  7151. return rc;
  7152. }
  7153. /* Wait for the controller to complete the SIS -> PQI transition. */
  7154. rc = pqi_wait_for_pqi_mode_ready(ctrl_info);
  7155. if (rc) {
  7156. dev_err(&ctrl_info->pci_dev->dev,
  7157. "transition to PQI mode failed\n");
  7158. return rc;
  7159. }
  7160. /* From here on, we are running in PQI mode. */
  7161. ctrl_info->pqi_mode_enabled = true;
  7162. pqi_save_ctrl_mode(ctrl_info, PQI_MODE);
  7163. pqi_reinit_queues(ctrl_info);
  7164. rc = pqi_create_admin_queues(ctrl_info);
  7165. if (rc) {
  7166. dev_err(&ctrl_info->pci_dev->dev,
  7167. "error creating admin queues\n");
  7168. return rc;
  7169. }
  7170. rc = pqi_create_queues(ctrl_info);
  7171. if (rc)
  7172. return rc;
  7173. pqi_change_irq_mode(ctrl_info, IRQ_MODE_MSIX);
  7174. ctrl_info->controller_online = true;
  7175. pqi_ctrl_unblock_requests(ctrl_info);
  7176. pqi_ctrl_reset_config(ctrl_info);
  7177. rc = pqi_process_config_table(ctrl_info);
  7178. if (rc)
  7179. return rc;
  7180. pqi_start_heartbeat_timer(ctrl_info);
  7181. if (ctrl_info->enable_r5_writes || ctrl_info->enable_r6_writes) {
  7182. rc = pqi_get_advanced_raid_bypass_config(ctrl_info);
  7183. if (rc) {
  7184. dev_err(&ctrl_info->pci_dev->dev,
  7185. "error obtaining advanced RAID bypass configuration\n");
  7186. return rc;
  7187. }
  7188. ctrl_info->ciss_report_log_flags |=
  7189. CISS_REPORT_LOG_FLAG_DRIVE_TYPE_MIX;
  7190. }
  7191. rc = pqi_enable_events(ctrl_info);
  7192. if (rc) {
  7193. dev_err(&ctrl_info->pci_dev->dev,
  7194. "error enabling events\n");
  7195. return rc;
  7196. }
  7197. rc = pqi_get_ctrl_product_details(ctrl_info);
  7198. if (rc) {
  7199. dev_err(&ctrl_info->pci_dev->dev,
  7200. "error obtaining product details\n");
  7201. return rc;
  7202. }
  7203. rc = pqi_set_diag_rescan(ctrl_info);
  7204. if (rc) {
  7205. dev_err(&ctrl_info->pci_dev->dev,
  7206. "error enabling multi-lun rescan\n");
  7207. return rc;
  7208. }
  7209. rc = pqi_write_driver_version_to_host_wellness(ctrl_info);
  7210. if (rc) {
  7211. dev_err(&ctrl_info->pci_dev->dev,
  7212. "error updating host wellness\n");
  7213. return rc;
  7214. }
  7215. if (pqi_ofa_in_progress(ctrl_info)) {
  7216. pqi_ctrl_unblock_scan(ctrl_info);
  7217. if (ctrl_info->ctrl_logging_supported) {
  7218. if (!ctrl_info->ctrl_log_memory.host_memory)
  7219. pqi_host_setup_buffer(ctrl_info,
  7220. &ctrl_info->ctrl_log_memory,
  7221. PQI_CTRL_LOG_TOTAL_SIZE,
  7222. PQI_CTRL_LOG_MIN_SIZE);
  7223. pqi_host_memory_update(ctrl_info,
  7224. &ctrl_info->ctrl_log_memory, PQI_VENDOR_GENERAL_CTRL_LOG_MEMORY_UPDATE);
  7225. } else {
  7226. if (ctrl_info->ctrl_log_memory.host_memory)
  7227. pqi_host_free_buffer(ctrl_info,
  7228. &ctrl_info->ctrl_log_memory);
  7229. }
  7230. }
  7231. pqi_scan_scsi_devices(ctrl_info);
  7232. return 0;
  7233. }
  7234. static inline int pqi_set_pcie_completion_timeout(struct pci_dev *pci_dev, u16 timeout)
  7235. {
  7236. int rc;
  7237. rc = pcie_capability_clear_and_set_word(pci_dev, PCI_EXP_DEVCTL2,
  7238. PCI_EXP_DEVCTL2_COMP_TIMEOUT, timeout);
  7239. return pcibios_err_to_errno(rc);
  7240. }
  7241. static int pqi_pci_init(struct pqi_ctrl_info *ctrl_info)
  7242. {
  7243. int rc;
  7244. u64 mask;
  7245. rc = pci_enable_device(ctrl_info->pci_dev);
  7246. if (rc) {
  7247. dev_err(&ctrl_info->pci_dev->dev,
  7248. "failed to enable PCI device\n");
  7249. return rc;
  7250. }
  7251. if (sizeof(dma_addr_t) > 4)
  7252. mask = DMA_BIT_MASK(64);
  7253. else
  7254. mask = DMA_BIT_MASK(32);
  7255. rc = dma_set_mask_and_coherent(&ctrl_info->pci_dev->dev, mask);
  7256. if (rc) {
  7257. dev_err(&ctrl_info->pci_dev->dev, "failed to set DMA mask\n");
  7258. goto disable_device;
  7259. }
  7260. rc = pci_request_regions(ctrl_info->pci_dev, DRIVER_NAME_SHORT);
  7261. if (rc) {
  7262. dev_err(&ctrl_info->pci_dev->dev,
  7263. "failed to obtain PCI resources\n");
  7264. goto disable_device;
  7265. }
  7266. ctrl_info->iomem_base = ioremap(pci_resource_start(
  7267. ctrl_info->pci_dev, 0),
  7268. pci_resource_len(ctrl_info->pci_dev, 0));
  7269. if (!ctrl_info->iomem_base) {
  7270. dev_err(&ctrl_info->pci_dev->dev,
  7271. "failed to map memory for controller registers\n");
  7272. rc = -ENOMEM;
  7273. goto release_regions;
  7274. }
  7275. #define PCI_EXP_COMP_TIMEOUT_65_TO_210_MS 0x6
  7276. /* Increase the PCIe completion timeout. */
  7277. rc = pqi_set_pcie_completion_timeout(ctrl_info->pci_dev,
  7278. PCI_EXP_COMP_TIMEOUT_65_TO_210_MS);
  7279. if (rc) {
  7280. dev_err(&ctrl_info->pci_dev->dev,
  7281. "failed to set PCIe completion timeout\n");
  7282. goto release_regions;
  7283. }
  7284. /* Enable bus mastering. */
  7285. pci_set_master(ctrl_info->pci_dev);
  7286. ctrl_info->registers = ctrl_info->iomem_base;
  7287. ctrl_info->pqi_registers = &ctrl_info->registers->pqi_registers;
  7288. pci_set_drvdata(ctrl_info->pci_dev, ctrl_info);
  7289. return 0;
  7290. release_regions:
  7291. pci_release_regions(ctrl_info->pci_dev);
  7292. disable_device:
  7293. pci_disable_device(ctrl_info->pci_dev);
  7294. return rc;
  7295. }
  7296. static void pqi_cleanup_pci_init(struct pqi_ctrl_info *ctrl_info)
  7297. {
  7298. iounmap(ctrl_info->iomem_base);
  7299. pci_release_regions(ctrl_info->pci_dev);
  7300. if (pci_is_enabled(ctrl_info->pci_dev))
  7301. pci_disable_device(ctrl_info->pci_dev);
  7302. pci_set_drvdata(ctrl_info->pci_dev, NULL);
  7303. }
  7304. static struct pqi_ctrl_info *pqi_alloc_ctrl_info(int numa_node)
  7305. {
  7306. struct pqi_ctrl_info *ctrl_info;
  7307. ctrl_info = kzalloc_node(sizeof(struct pqi_ctrl_info),
  7308. GFP_KERNEL, numa_node);
  7309. if (!ctrl_info)
  7310. return NULL;
  7311. mutex_init(&ctrl_info->scan_mutex);
  7312. mutex_init(&ctrl_info->lun_reset_mutex);
  7313. mutex_init(&ctrl_info->ofa_mutex);
  7314. INIT_LIST_HEAD(&ctrl_info->scsi_device_list);
  7315. spin_lock_init(&ctrl_info->scsi_device_list_lock);
  7316. INIT_WORK(&ctrl_info->event_work, pqi_event_worker);
  7317. atomic_set(&ctrl_info->num_interrupts, 0);
  7318. INIT_DELAYED_WORK(&ctrl_info->rescan_work, pqi_rescan_worker);
  7319. INIT_DELAYED_WORK(&ctrl_info->update_time_work, pqi_update_time_worker);
  7320. timer_setup(&ctrl_info->heartbeat_timer, pqi_heartbeat_timer_handler, 0);
  7321. INIT_WORK(&ctrl_info->ctrl_offline_work, pqi_ctrl_offline_worker);
  7322. INIT_WORK(&ctrl_info->ofa_memory_alloc_work, pqi_ofa_memory_alloc_worker);
  7323. INIT_WORK(&ctrl_info->ofa_quiesce_work, pqi_ofa_quiesce_worker);
  7324. sema_init(&ctrl_info->sync_request_sem,
  7325. PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS);
  7326. init_waitqueue_head(&ctrl_info->block_requests_wait);
  7327. ctrl_info->ctrl_id = atomic_inc_return(&pqi_controller_count) - 1;
  7328. ctrl_info->irq_mode = IRQ_MODE_NONE;
  7329. ctrl_info->max_msix_vectors = PQI_MAX_MSIX_VECTORS;
  7330. ctrl_info->ciss_report_log_flags = CISS_REPORT_LOG_FLAG_UNIQUE_LUN_ID;
  7331. ctrl_info->max_transfer_encrypted_sas_sata =
  7332. PQI_DEFAULT_MAX_TRANSFER_ENCRYPTED_SAS_SATA;
  7333. ctrl_info->max_transfer_encrypted_nvme =
  7334. PQI_DEFAULT_MAX_TRANSFER_ENCRYPTED_NVME;
  7335. ctrl_info->max_write_raid_5_6 = PQI_DEFAULT_MAX_WRITE_RAID_5_6;
  7336. ctrl_info->max_write_raid_1_10_2drive = ~0;
  7337. ctrl_info->max_write_raid_1_10_3drive = ~0;
  7338. ctrl_info->disable_managed_interrupts = pqi_disable_managed_interrupts;
  7339. return ctrl_info;
  7340. }
  7341. static inline void pqi_free_ctrl_info(struct pqi_ctrl_info *ctrl_info)
  7342. {
  7343. kfree(ctrl_info);
  7344. }
  7345. static void pqi_free_interrupts(struct pqi_ctrl_info *ctrl_info)
  7346. {
  7347. pqi_free_irqs(ctrl_info);
  7348. pqi_disable_msix_interrupts(ctrl_info);
  7349. }
  7350. static void pqi_free_ctrl_resources(struct pqi_ctrl_info *ctrl_info)
  7351. {
  7352. pqi_free_interrupts(ctrl_info);
  7353. if (ctrl_info->queue_memory_base)
  7354. dma_free_coherent(&ctrl_info->pci_dev->dev,
  7355. ctrl_info->queue_memory_length,
  7356. ctrl_info->queue_memory_base,
  7357. ctrl_info->queue_memory_base_dma_handle);
  7358. if (ctrl_info->admin_queue_memory_base)
  7359. dma_free_coherent(&ctrl_info->pci_dev->dev,
  7360. ctrl_info->admin_queue_memory_length,
  7361. ctrl_info->admin_queue_memory_base,
  7362. ctrl_info->admin_queue_memory_base_dma_handle);
  7363. pqi_free_all_io_requests(ctrl_info);
  7364. if (ctrl_info->error_buffer)
  7365. dma_free_coherent(&ctrl_info->pci_dev->dev,
  7366. ctrl_info->error_buffer_length,
  7367. ctrl_info->error_buffer,
  7368. ctrl_info->error_buffer_dma_handle);
  7369. if (ctrl_info->iomem_base)
  7370. pqi_cleanup_pci_init(ctrl_info);
  7371. pqi_free_ctrl_info(ctrl_info);
  7372. }
  7373. static void pqi_remove_ctrl(struct pqi_ctrl_info *ctrl_info)
  7374. {
  7375. ctrl_info->controller_online = false;
  7376. pqi_stop_heartbeat_timer(ctrl_info);
  7377. pqi_ctrl_block_requests(ctrl_info);
  7378. pqi_cancel_rescan_worker(ctrl_info);
  7379. pqi_cancel_update_time_worker(ctrl_info);
  7380. if (ctrl_info->ctrl_removal_state == PQI_CTRL_SURPRISE_REMOVAL) {
  7381. pqi_fail_all_outstanding_requests(ctrl_info);
  7382. ctrl_info->pqi_mode_enabled = false;
  7383. }
  7384. pqi_host_free_buffer(ctrl_info, &ctrl_info->ctrl_log_memory);
  7385. pqi_unregister_scsi(ctrl_info);
  7386. if (ctrl_info->pqi_mode_enabled)
  7387. pqi_revert_to_sis_mode(ctrl_info);
  7388. pqi_free_ctrl_resources(ctrl_info);
  7389. }
  7390. static void pqi_ofa_ctrl_quiesce(struct pqi_ctrl_info *ctrl_info)
  7391. {
  7392. pqi_ctrl_block_scan(ctrl_info);
  7393. pqi_scsi_block_requests(ctrl_info);
  7394. pqi_ctrl_block_device_reset(ctrl_info);
  7395. pqi_ctrl_block_requests(ctrl_info);
  7396. pqi_ctrl_wait_until_quiesced(ctrl_info);
  7397. pqi_stop_heartbeat_timer(ctrl_info);
  7398. }
  7399. static void pqi_ofa_ctrl_unquiesce(struct pqi_ctrl_info *ctrl_info)
  7400. {
  7401. pqi_start_heartbeat_timer(ctrl_info);
  7402. pqi_ctrl_unblock_requests(ctrl_info);
  7403. pqi_ctrl_unblock_device_reset(ctrl_info);
  7404. pqi_scsi_unblock_requests(ctrl_info);
  7405. pqi_ctrl_unblock_scan(ctrl_info);
  7406. }
  7407. static int pqi_ofa_ctrl_restart(struct pqi_ctrl_info *ctrl_info, unsigned int delay_secs)
  7408. {
  7409. ssleep(delay_secs);
  7410. return pqi_ctrl_init_resume(ctrl_info);
  7411. }
  7412. static int pqi_host_alloc_mem(struct pqi_ctrl_info *ctrl_info,
  7413. struct pqi_host_memory_descriptor *host_memory_descriptor,
  7414. u32 total_size, u32 chunk_size)
  7415. {
  7416. int i;
  7417. u32 sg_count;
  7418. struct device *dev;
  7419. struct pqi_host_memory *host_memory;
  7420. struct pqi_sg_descriptor *mem_descriptor;
  7421. dma_addr_t dma_handle;
  7422. sg_count = DIV_ROUND_UP(total_size, chunk_size);
  7423. if (sg_count == 0 || sg_count > PQI_HOST_MAX_SG_DESCRIPTORS)
  7424. goto out;
  7425. host_memory_descriptor->host_chunk_virt_address = kmalloc(sg_count * sizeof(void *), GFP_KERNEL);
  7426. if (!host_memory_descriptor->host_chunk_virt_address)
  7427. goto out;
  7428. dev = &ctrl_info->pci_dev->dev;
  7429. host_memory = host_memory_descriptor->host_memory;
  7430. for (i = 0; i < sg_count; i++) {
  7431. host_memory_descriptor->host_chunk_virt_address[i] = dma_alloc_coherent(dev, chunk_size, &dma_handle, GFP_KERNEL);
  7432. if (!host_memory_descriptor->host_chunk_virt_address[i])
  7433. goto out_free_chunks;
  7434. mem_descriptor = &host_memory->sg_descriptor[i];
  7435. put_unaligned_le64((u64)dma_handle, &mem_descriptor->address);
  7436. put_unaligned_le32(chunk_size, &mem_descriptor->length);
  7437. }
  7438. put_unaligned_le32(CISS_SG_LAST, &mem_descriptor->flags);
  7439. put_unaligned_le16(sg_count, &host_memory->num_memory_descriptors);
  7440. put_unaligned_le32(sg_count * chunk_size, &host_memory->bytes_allocated);
  7441. return 0;
  7442. out_free_chunks:
  7443. while (--i >= 0) {
  7444. mem_descriptor = &host_memory->sg_descriptor[i];
  7445. dma_free_coherent(dev, chunk_size,
  7446. host_memory_descriptor->host_chunk_virt_address[i],
  7447. get_unaligned_le64(&mem_descriptor->address));
  7448. }
  7449. kfree(host_memory_descriptor->host_chunk_virt_address);
  7450. out:
  7451. return -ENOMEM;
  7452. }
  7453. static int pqi_host_alloc_buffer(struct pqi_ctrl_info *ctrl_info,
  7454. struct pqi_host_memory_descriptor *host_memory_descriptor,
  7455. u32 total_required_size, u32 min_required_size)
  7456. {
  7457. u32 chunk_size;
  7458. u32 min_chunk_size;
  7459. if (total_required_size == 0 || min_required_size == 0)
  7460. return 0;
  7461. total_required_size = PAGE_ALIGN(total_required_size);
  7462. min_required_size = PAGE_ALIGN(min_required_size);
  7463. min_chunk_size = DIV_ROUND_UP(total_required_size, PQI_HOST_MAX_SG_DESCRIPTORS);
  7464. min_chunk_size = PAGE_ALIGN(min_chunk_size);
  7465. while (total_required_size >= min_required_size) {
  7466. for (chunk_size = total_required_size; chunk_size >= min_chunk_size;) {
  7467. if (pqi_host_alloc_mem(ctrl_info,
  7468. host_memory_descriptor, total_required_size,
  7469. chunk_size) == 0)
  7470. return 0;
  7471. chunk_size /= 2;
  7472. chunk_size = PAGE_ALIGN(chunk_size);
  7473. }
  7474. total_required_size /= 2;
  7475. total_required_size = PAGE_ALIGN(total_required_size);
  7476. }
  7477. return -ENOMEM;
  7478. }
  7479. static void pqi_host_setup_buffer(struct pqi_ctrl_info *ctrl_info,
  7480. struct pqi_host_memory_descriptor *host_memory_descriptor,
  7481. u32 total_size, u32 min_size)
  7482. {
  7483. struct device *dev;
  7484. struct pqi_host_memory *host_memory;
  7485. dev = &ctrl_info->pci_dev->dev;
  7486. host_memory = dma_alloc_coherent(dev, sizeof(*host_memory),
  7487. &host_memory_descriptor->host_memory_dma_handle, GFP_KERNEL);
  7488. if (!host_memory)
  7489. return;
  7490. host_memory_descriptor->host_memory = host_memory;
  7491. if (pqi_host_alloc_buffer(ctrl_info, host_memory_descriptor,
  7492. total_size, min_size) < 0) {
  7493. dev_err(dev, "failed to allocate firmware usable host buffer\n");
  7494. dma_free_coherent(dev, sizeof(*host_memory), host_memory,
  7495. host_memory_descriptor->host_memory_dma_handle);
  7496. host_memory_descriptor->host_memory = NULL;
  7497. return;
  7498. }
  7499. }
  7500. static void pqi_host_free_buffer(struct pqi_ctrl_info *ctrl_info,
  7501. struct pqi_host_memory_descriptor *host_memory_descriptor)
  7502. {
  7503. unsigned int i;
  7504. struct device *dev;
  7505. struct pqi_host_memory *host_memory;
  7506. struct pqi_sg_descriptor *mem_descriptor;
  7507. unsigned int num_memory_descriptors;
  7508. host_memory = host_memory_descriptor->host_memory;
  7509. if (!host_memory)
  7510. return;
  7511. dev = &ctrl_info->pci_dev->dev;
  7512. if (get_unaligned_le32(&host_memory->bytes_allocated) == 0)
  7513. goto out;
  7514. mem_descriptor = host_memory->sg_descriptor;
  7515. num_memory_descriptors = get_unaligned_le16(&host_memory->num_memory_descriptors);
  7516. for (i = 0; i < num_memory_descriptors; i++) {
  7517. dma_free_coherent(dev,
  7518. get_unaligned_le32(&mem_descriptor[i].length),
  7519. host_memory_descriptor->host_chunk_virt_address[i],
  7520. get_unaligned_le64(&mem_descriptor[i].address));
  7521. }
  7522. kfree(host_memory_descriptor->host_chunk_virt_address);
  7523. out:
  7524. dma_free_coherent(dev, sizeof(*host_memory), host_memory,
  7525. host_memory_descriptor->host_memory_dma_handle);
  7526. host_memory_descriptor->host_memory = NULL;
  7527. }
  7528. static int pqi_host_memory_update(struct pqi_ctrl_info *ctrl_info,
  7529. struct pqi_host_memory_descriptor *host_memory_descriptor,
  7530. u16 function_code)
  7531. {
  7532. u32 buffer_length;
  7533. struct pqi_vendor_general_request request;
  7534. struct pqi_host_memory *host_memory;
  7535. memset(&request, 0, sizeof(request));
  7536. request.header.iu_type = PQI_REQUEST_IU_VENDOR_GENERAL;
  7537. put_unaligned_le16(sizeof(request) - PQI_REQUEST_HEADER_LENGTH, &request.header.iu_length);
  7538. put_unaligned_le16(function_code, &request.function_code);
  7539. host_memory = host_memory_descriptor->host_memory;
  7540. if (host_memory) {
  7541. buffer_length = offsetof(struct pqi_host_memory, sg_descriptor) + get_unaligned_le16(&host_memory->num_memory_descriptors) * sizeof(struct pqi_sg_descriptor);
  7542. put_unaligned_le64((u64)host_memory_descriptor->host_memory_dma_handle, &request.data.host_memory_allocation.buffer_address);
  7543. put_unaligned_le32(buffer_length, &request.data.host_memory_allocation.buffer_length);
  7544. if (function_code == PQI_VENDOR_GENERAL_OFA_MEMORY_UPDATE) {
  7545. put_unaligned_le16(PQI_OFA_VERSION, &host_memory->version);
  7546. memcpy(&host_memory->signature, PQI_OFA_SIGNATURE, sizeof(host_memory->signature));
  7547. } else if (function_code == PQI_VENDOR_GENERAL_CTRL_LOG_MEMORY_UPDATE) {
  7548. put_unaligned_le16(PQI_CTRL_LOG_VERSION, &host_memory->version);
  7549. memcpy(&host_memory->signature, PQI_CTRL_LOG_SIGNATURE, sizeof(host_memory->signature));
  7550. }
  7551. }
  7552. return pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, NULL);
  7553. }
  7554. static struct pqi_raid_error_info pqi_ctrl_offline_raid_error_info = {
  7555. .data_out_result = PQI_DATA_IN_OUT_HARDWARE_ERROR,
  7556. .status = SAM_STAT_CHECK_CONDITION,
  7557. };
  7558. static void pqi_fail_all_outstanding_requests(struct pqi_ctrl_info *ctrl_info)
  7559. {
  7560. unsigned int i;
  7561. struct pqi_io_request *io_request;
  7562. struct scsi_cmnd *scmd;
  7563. struct scsi_device *sdev;
  7564. for (i = 0; i < ctrl_info->max_io_slots; i++) {
  7565. io_request = &ctrl_info->io_request_pool[i];
  7566. if (atomic_read(&io_request->refcount) == 0)
  7567. continue;
  7568. scmd = io_request->scmd;
  7569. if (scmd) {
  7570. sdev = scmd->device;
  7571. if (!sdev || !scsi_device_online(sdev)) {
  7572. pqi_free_io_request(io_request);
  7573. continue;
  7574. } else {
  7575. set_host_byte(scmd, DID_NO_CONNECT);
  7576. }
  7577. } else {
  7578. io_request->status = -ENXIO;
  7579. io_request->error_info =
  7580. &pqi_ctrl_offline_raid_error_info;
  7581. }
  7582. io_request->io_complete_callback(io_request,
  7583. io_request->context);
  7584. }
  7585. }
  7586. static void pqi_take_ctrl_offline_deferred(struct pqi_ctrl_info *ctrl_info)
  7587. {
  7588. pqi_perform_lockup_action();
  7589. pqi_stop_heartbeat_timer(ctrl_info);
  7590. pqi_free_interrupts(ctrl_info);
  7591. pqi_cancel_rescan_worker(ctrl_info);
  7592. pqi_cancel_update_time_worker(ctrl_info);
  7593. pqi_ctrl_wait_until_quiesced(ctrl_info);
  7594. pqi_fail_all_outstanding_requests(ctrl_info);
  7595. pqi_ctrl_unblock_requests(ctrl_info);
  7596. }
  7597. static void pqi_ctrl_offline_worker(struct work_struct *work)
  7598. {
  7599. struct pqi_ctrl_info *ctrl_info;
  7600. ctrl_info = container_of(work, struct pqi_ctrl_info, ctrl_offline_work);
  7601. pqi_take_ctrl_offline_deferred(ctrl_info);
  7602. }
  7603. static char *pqi_ctrl_shutdown_reason_to_string(enum pqi_ctrl_shutdown_reason ctrl_shutdown_reason)
  7604. {
  7605. char *string;
  7606. switch (ctrl_shutdown_reason) {
  7607. case PQI_IQ_NOT_DRAINED_TIMEOUT:
  7608. string = "inbound queue not drained timeout";
  7609. break;
  7610. case PQI_LUN_RESET_TIMEOUT:
  7611. string = "LUN reset timeout";
  7612. break;
  7613. case PQI_IO_PENDING_POST_LUN_RESET_TIMEOUT:
  7614. string = "I/O pending timeout after LUN reset";
  7615. break;
  7616. case PQI_NO_HEARTBEAT:
  7617. string = "no controller heartbeat detected";
  7618. break;
  7619. case PQI_FIRMWARE_KERNEL_NOT_UP:
  7620. string = "firmware kernel not ready";
  7621. break;
  7622. case PQI_OFA_RESPONSE_TIMEOUT:
  7623. string = "OFA response timeout";
  7624. break;
  7625. case PQI_INVALID_REQ_ID:
  7626. string = "invalid request ID";
  7627. break;
  7628. case PQI_UNMATCHED_REQ_ID:
  7629. string = "unmatched request ID";
  7630. break;
  7631. case PQI_IO_PI_OUT_OF_RANGE:
  7632. string = "I/O queue producer index out of range";
  7633. break;
  7634. case PQI_EVENT_PI_OUT_OF_RANGE:
  7635. string = "event queue producer index out of range";
  7636. break;
  7637. case PQI_UNEXPECTED_IU_TYPE:
  7638. string = "unexpected IU type";
  7639. break;
  7640. default:
  7641. string = "unknown reason";
  7642. break;
  7643. }
  7644. return string;
  7645. }
  7646. static void pqi_take_ctrl_offline(struct pqi_ctrl_info *ctrl_info,
  7647. enum pqi_ctrl_shutdown_reason ctrl_shutdown_reason)
  7648. {
  7649. if (!ctrl_info->controller_online)
  7650. return;
  7651. ctrl_info->controller_online = false;
  7652. ctrl_info->pqi_mode_enabled = false;
  7653. pqi_ctrl_block_requests(ctrl_info);
  7654. if (!pqi_disable_ctrl_shutdown)
  7655. sis_shutdown_ctrl(ctrl_info, ctrl_shutdown_reason);
  7656. pci_disable_device(ctrl_info->pci_dev);
  7657. dev_err(&ctrl_info->pci_dev->dev,
  7658. "controller offline: reason code 0x%x (%s)\n",
  7659. ctrl_shutdown_reason, pqi_ctrl_shutdown_reason_to_string(ctrl_shutdown_reason));
  7660. schedule_work(&ctrl_info->ctrl_offline_work);
  7661. }
  7662. static void pqi_print_ctrl_info(struct pci_dev *pci_dev,
  7663. const struct pci_device_id *id)
  7664. {
  7665. char *ctrl_description;
  7666. if (id->driver_data)
  7667. ctrl_description = (char *)id->driver_data;
  7668. else
  7669. ctrl_description = "Microchip Smart Family Controller";
  7670. dev_info(&pci_dev->dev, "%s found\n", ctrl_description);
  7671. }
  7672. static int pqi_pci_probe(struct pci_dev *pci_dev,
  7673. const struct pci_device_id *id)
  7674. {
  7675. int rc;
  7676. int node;
  7677. struct pqi_ctrl_info *ctrl_info;
  7678. pqi_print_ctrl_info(pci_dev, id);
  7679. if (pqi_disable_device_id_wildcards &&
  7680. id->subvendor == PCI_ANY_ID &&
  7681. id->subdevice == PCI_ANY_ID) {
  7682. dev_warn(&pci_dev->dev,
  7683. "controller not probed because device ID wildcards are disabled\n");
  7684. return -ENODEV;
  7685. }
  7686. if (id->subvendor == PCI_ANY_ID || id->subdevice == PCI_ANY_ID)
  7687. dev_warn(&pci_dev->dev,
  7688. "controller device ID matched using wildcards\n");
  7689. node = dev_to_node(&pci_dev->dev);
  7690. if (node == NUMA_NO_NODE) {
  7691. node = cpu_to_node(0);
  7692. if (node == NUMA_NO_NODE)
  7693. node = 0;
  7694. set_dev_node(&pci_dev->dev, node);
  7695. }
  7696. ctrl_info = pqi_alloc_ctrl_info(node);
  7697. if (!ctrl_info) {
  7698. dev_err(&pci_dev->dev,
  7699. "failed to allocate controller info block\n");
  7700. return -ENOMEM;
  7701. }
  7702. ctrl_info->numa_node = node;
  7703. ctrl_info->pci_dev = pci_dev;
  7704. rc = pqi_pci_init(ctrl_info);
  7705. if (rc)
  7706. goto error;
  7707. rc = pqi_ctrl_init(ctrl_info);
  7708. if (rc)
  7709. goto error;
  7710. return 0;
  7711. error:
  7712. pqi_remove_ctrl(ctrl_info);
  7713. return rc;
  7714. }
  7715. static void pqi_pci_remove(struct pci_dev *pci_dev)
  7716. {
  7717. struct pqi_ctrl_info *ctrl_info;
  7718. u16 vendor_id;
  7719. int rc;
  7720. ctrl_info = pci_get_drvdata(pci_dev);
  7721. if (!ctrl_info)
  7722. return;
  7723. pci_read_config_word(ctrl_info->pci_dev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
  7724. if (vendor_id == 0xffff)
  7725. ctrl_info->ctrl_removal_state = PQI_CTRL_SURPRISE_REMOVAL;
  7726. else
  7727. ctrl_info->ctrl_removal_state = PQI_CTRL_GRACEFUL_REMOVAL;
  7728. if (ctrl_info->ctrl_removal_state == PQI_CTRL_GRACEFUL_REMOVAL) {
  7729. rc = pqi_flush_cache(ctrl_info, RESTART);
  7730. if (rc)
  7731. dev_err(&pci_dev->dev,
  7732. "unable to flush controller cache during remove\n");
  7733. }
  7734. pqi_remove_ctrl(ctrl_info);
  7735. }
  7736. static void pqi_crash_if_pending_command(struct pqi_ctrl_info *ctrl_info)
  7737. {
  7738. unsigned int i;
  7739. struct pqi_io_request *io_request;
  7740. struct scsi_cmnd *scmd;
  7741. for (i = 0; i < ctrl_info->max_io_slots; i++) {
  7742. io_request = &ctrl_info->io_request_pool[i];
  7743. if (atomic_read(&io_request->refcount) == 0)
  7744. continue;
  7745. scmd = io_request->scmd;
  7746. WARN_ON(scmd != NULL); /* IO command from SML */
  7747. WARN_ON(scmd == NULL); /* Non-IO cmd or driver initiated*/
  7748. }
  7749. }
  7750. static void pqi_shutdown(struct pci_dev *pci_dev)
  7751. {
  7752. int rc;
  7753. struct pqi_ctrl_info *ctrl_info;
  7754. enum bmic_flush_cache_shutdown_event shutdown_event;
  7755. ctrl_info = pci_get_drvdata(pci_dev);
  7756. if (!ctrl_info) {
  7757. dev_err(&pci_dev->dev,
  7758. "cache could not be flushed\n");
  7759. return;
  7760. }
  7761. pqi_wait_until_ofa_finished(ctrl_info);
  7762. pqi_scsi_block_requests(ctrl_info);
  7763. pqi_ctrl_block_device_reset(ctrl_info);
  7764. pqi_ctrl_block_requests(ctrl_info);
  7765. pqi_ctrl_wait_until_quiesced(ctrl_info);
  7766. if (system_state == SYSTEM_RESTART)
  7767. shutdown_event = RESTART;
  7768. else
  7769. shutdown_event = SHUTDOWN;
  7770. /*
  7771. * Write all data in the controller's battery-backed cache to
  7772. * storage.
  7773. */
  7774. rc = pqi_flush_cache(ctrl_info, shutdown_event);
  7775. if (rc)
  7776. dev_err(&pci_dev->dev,
  7777. "unable to flush controller cache during shutdown\n");
  7778. pqi_crash_if_pending_command(ctrl_info);
  7779. pqi_reset(ctrl_info);
  7780. }
  7781. static void pqi_process_lockup_action_param(void)
  7782. {
  7783. unsigned int i;
  7784. if (!pqi_lockup_action_param)
  7785. return;
  7786. for (i = 0; i < ARRAY_SIZE(pqi_lockup_actions); i++) {
  7787. if (strcmp(pqi_lockup_action_param,
  7788. pqi_lockup_actions[i].name) == 0) {
  7789. pqi_lockup_action = pqi_lockup_actions[i].action;
  7790. return;
  7791. }
  7792. }
  7793. pr_warn("%s: invalid lockup action setting \"%s\" - supported settings: none, reboot, panic\n",
  7794. DRIVER_NAME_SHORT, pqi_lockup_action_param);
  7795. }
  7796. #define PQI_CTRL_READY_TIMEOUT_PARAM_MIN_SECS 30
  7797. #define PQI_CTRL_READY_TIMEOUT_PARAM_MAX_SECS (30 * 60)
  7798. static void pqi_process_ctrl_ready_timeout_param(void)
  7799. {
  7800. if (pqi_ctrl_ready_timeout_secs == 0)
  7801. return;
  7802. if (pqi_ctrl_ready_timeout_secs < PQI_CTRL_READY_TIMEOUT_PARAM_MIN_SECS) {
  7803. pr_warn("%s: ctrl_ready_timeout parm of %u second(s) is less than minimum timeout of %d seconds - setting timeout to %d seconds\n",
  7804. DRIVER_NAME_SHORT, pqi_ctrl_ready_timeout_secs, PQI_CTRL_READY_TIMEOUT_PARAM_MIN_SECS, PQI_CTRL_READY_TIMEOUT_PARAM_MIN_SECS);
  7805. pqi_ctrl_ready_timeout_secs = PQI_CTRL_READY_TIMEOUT_PARAM_MIN_SECS;
  7806. } else if (pqi_ctrl_ready_timeout_secs > PQI_CTRL_READY_TIMEOUT_PARAM_MAX_SECS) {
  7807. pr_warn("%s: ctrl_ready_timeout parm of %u seconds is greater than maximum timeout of %d seconds - setting timeout to %d seconds\n",
  7808. DRIVER_NAME_SHORT, pqi_ctrl_ready_timeout_secs, PQI_CTRL_READY_TIMEOUT_PARAM_MAX_SECS, PQI_CTRL_READY_TIMEOUT_PARAM_MAX_SECS);
  7809. pqi_ctrl_ready_timeout_secs = PQI_CTRL_READY_TIMEOUT_PARAM_MAX_SECS;
  7810. }
  7811. sis_ctrl_ready_timeout_secs = pqi_ctrl_ready_timeout_secs;
  7812. }
  7813. static void pqi_process_module_params(void)
  7814. {
  7815. pqi_process_lockup_action_param();
  7816. pqi_process_ctrl_ready_timeout_param();
  7817. }
  7818. #if defined(CONFIG_PM)
  7819. static inline enum bmic_flush_cache_shutdown_event pqi_get_flush_cache_shutdown_event(struct pci_dev *pci_dev)
  7820. {
  7821. if (pci_dev->subsystem_vendor == PCI_VENDOR_ID_ADAPTEC2 && pci_dev->subsystem_device == 0x1304)
  7822. return RESTART;
  7823. return SUSPEND;
  7824. }
  7825. static int pqi_suspend_or_freeze(struct device *dev, bool suspend)
  7826. {
  7827. struct pci_dev *pci_dev;
  7828. struct pqi_ctrl_info *ctrl_info;
  7829. pci_dev = to_pci_dev(dev);
  7830. ctrl_info = pci_get_drvdata(pci_dev);
  7831. pqi_wait_until_ofa_finished(ctrl_info);
  7832. pqi_ctrl_block_scan(ctrl_info);
  7833. pqi_scsi_block_requests(ctrl_info);
  7834. pqi_ctrl_block_device_reset(ctrl_info);
  7835. pqi_ctrl_block_requests(ctrl_info);
  7836. pqi_ctrl_wait_until_quiesced(ctrl_info);
  7837. if (suspend) {
  7838. enum bmic_flush_cache_shutdown_event shutdown_event;
  7839. shutdown_event = pqi_get_flush_cache_shutdown_event(pci_dev);
  7840. pqi_flush_cache(ctrl_info, shutdown_event);
  7841. }
  7842. pqi_stop_heartbeat_timer(ctrl_info);
  7843. pqi_crash_if_pending_command(ctrl_info);
  7844. pqi_free_irqs(ctrl_info);
  7845. ctrl_info->controller_online = false;
  7846. ctrl_info->pqi_mode_enabled = false;
  7847. return 0;
  7848. }
  7849. static __maybe_unused int pqi_suspend(struct device *dev)
  7850. {
  7851. return pqi_suspend_or_freeze(dev, true);
  7852. }
  7853. static int pqi_resume_or_restore(struct device *dev)
  7854. {
  7855. int rc;
  7856. struct pci_dev *pci_dev;
  7857. struct pqi_ctrl_info *ctrl_info;
  7858. pci_dev = to_pci_dev(dev);
  7859. ctrl_info = pci_get_drvdata(pci_dev);
  7860. rc = pqi_request_irqs(ctrl_info);
  7861. if (rc)
  7862. return rc;
  7863. pqi_ctrl_unblock_device_reset(ctrl_info);
  7864. pqi_ctrl_unblock_requests(ctrl_info);
  7865. pqi_scsi_unblock_requests(ctrl_info);
  7866. pqi_ctrl_unblock_scan(ctrl_info);
  7867. ssleep(PQI_POST_RESET_DELAY_SECS);
  7868. return pqi_ctrl_init_resume(ctrl_info);
  7869. }
  7870. static int pqi_freeze(struct device *dev)
  7871. {
  7872. return pqi_suspend_or_freeze(dev, false);
  7873. }
  7874. static int pqi_thaw(struct device *dev)
  7875. {
  7876. int rc;
  7877. struct pci_dev *pci_dev;
  7878. struct pqi_ctrl_info *ctrl_info;
  7879. pci_dev = to_pci_dev(dev);
  7880. ctrl_info = pci_get_drvdata(pci_dev);
  7881. rc = pqi_request_irqs(ctrl_info);
  7882. if (rc)
  7883. return rc;
  7884. ctrl_info->controller_online = true;
  7885. ctrl_info->pqi_mode_enabled = true;
  7886. pqi_ctrl_unblock_device_reset(ctrl_info);
  7887. pqi_ctrl_unblock_requests(ctrl_info);
  7888. pqi_scsi_unblock_requests(ctrl_info);
  7889. pqi_ctrl_unblock_scan(ctrl_info);
  7890. return 0;
  7891. }
  7892. static int pqi_poweroff(struct device *dev)
  7893. {
  7894. struct pci_dev *pci_dev;
  7895. struct pqi_ctrl_info *ctrl_info;
  7896. enum bmic_flush_cache_shutdown_event shutdown_event;
  7897. pci_dev = to_pci_dev(dev);
  7898. ctrl_info = pci_get_drvdata(pci_dev);
  7899. shutdown_event = pqi_get_flush_cache_shutdown_event(pci_dev);
  7900. pqi_flush_cache(ctrl_info, shutdown_event);
  7901. return 0;
  7902. }
  7903. static const struct dev_pm_ops pqi_pm_ops = {
  7904. .suspend = pqi_suspend,
  7905. .resume = pqi_resume_or_restore,
  7906. .freeze = pqi_freeze,
  7907. .thaw = pqi_thaw,
  7908. .poweroff = pqi_poweroff,
  7909. .restore = pqi_resume_or_restore,
  7910. };
  7911. #endif /* CONFIG_PM */
  7912. /* Define the PCI IDs for the controllers that we support. */
  7913. static const struct pci_device_id pqi_pci_id_table[] = {
  7914. {
  7915. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7916. 0x105b, 0x1211)
  7917. },
  7918. {
  7919. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7920. 0x105b, 0x1321)
  7921. },
  7922. {
  7923. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7924. 0x152d, 0x8a22)
  7925. },
  7926. {
  7927. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7928. 0x152d, 0x8a23)
  7929. },
  7930. {
  7931. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7932. 0x152d, 0x8a24)
  7933. },
  7934. {
  7935. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7936. 0x152d, 0x8a36)
  7937. },
  7938. {
  7939. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7940. 0x152d, 0x8a37)
  7941. },
  7942. {
  7943. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7944. 0x193d, 0x0462)
  7945. },
  7946. {
  7947. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7948. 0x193d, 0x1104)
  7949. },
  7950. {
  7951. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7952. 0x193d, 0x1105)
  7953. },
  7954. {
  7955. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7956. 0x193d, 0x1106)
  7957. },
  7958. {
  7959. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7960. 0x193d, 0x1107)
  7961. },
  7962. {
  7963. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7964. 0x193d, 0x1108)
  7965. },
  7966. {
  7967. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7968. 0x193d, 0x1109)
  7969. },
  7970. {
  7971. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7972. 0x193d, 0x110b)
  7973. },
  7974. {
  7975. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7976. 0x193d, 0x1110)
  7977. },
  7978. {
  7979. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7980. 0x193d, 0x8460)
  7981. },
  7982. {
  7983. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7984. 0x193d, 0x8461)
  7985. },
  7986. {
  7987. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7988. 0x193d, 0x8462)
  7989. },
  7990. {
  7991. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7992. 0x193d, 0xc460)
  7993. },
  7994. {
  7995. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7996. 0x193d, 0xc461)
  7997. },
  7998. {
  7999. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8000. 0x193d, 0xf460)
  8001. },
  8002. {
  8003. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8004. 0x193d, 0xf461)
  8005. },
  8006. {
  8007. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8008. 0x1bd4, 0x0045)
  8009. },
  8010. {
  8011. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8012. 0x1bd4, 0x0046)
  8013. },
  8014. {
  8015. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8016. 0x1bd4, 0x0047)
  8017. },
  8018. {
  8019. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8020. 0x1bd4, 0x0048)
  8021. },
  8022. {
  8023. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8024. 0x1bd4, 0x004a)
  8025. },
  8026. {
  8027. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8028. 0x1bd4, 0x004b)
  8029. },
  8030. {
  8031. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8032. 0x1bd4, 0x004c)
  8033. },
  8034. {
  8035. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8036. 0x1bd4, 0x004f)
  8037. },
  8038. {
  8039. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8040. 0x1bd4, 0x0051)
  8041. },
  8042. {
  8043. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8044. 0x1bd4, 0x0052)
  8045. },
  8046. {
  8047. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8048. 0x1bd4, 0x0053)
  8049. },
  8050. {
  8051. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8052. 0x1bd4, 0x0054)
  8053. },
  8054. {
  8055. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8056. 0x1bd4, 0x006b)
  8057. },
  8058. {
  8059. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8060. 0x1bd4, 0x006c)
  8061. },
  8062. {
  8063. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8064. 0x1bd4, 0x006d)
  8065. },
  8066. {
  8067. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8068. 0x1bd4, 0x006f)
  8069. },
  8070. {
  8071. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8072. 0x1bd4, 0x0070)
  8073. },
  8074. {
  8075. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8076. 0x1bd4, 0x0071)
  8077. },
  8078. {
  8079. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8080. 0x1bd4, 0x0072)
  8081. },
  8082. {
  8083. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8084. 0x1bd4, 0x0086)
  8085. },
  8086. {
  8087. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8088. 0x1bd4, 0x0087)
  8089. },
  8090. {
  8091. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8092. 0x1bd4, 0x0088)
  8093. },
  8094. {
  8095. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8096. 0x1bd4, 0x0089)
  8097. },
  8098. {
  8099. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8100. 0x1ff9, 0x00a1)
  8101. },
  8102. {
  8103. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8104. 0x1f3a, 0x0104)
  8105. },
  8106. {
  8107. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8108. 0x19e5, 0xd227)
  8109. },
  8110. {
  8111. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8112. 0x19e5, 0xd228)
  8113. },
  8114. {
  8115. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8116. 0x19e5, 0xd229)
  8117. },
  8118. {
  8119. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8120. 0x19e5, 0xd22a)
  8121. },
  8122. {
  8123. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8124. 0x19e5, 0xd22b)
  8125. },
  8126. {
  8127. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8128. 0x19e5, 0xd22c)
  8129. },
  8130. {
  8131. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8132. PCI_VENDOR_ID_ADAPTEC2, 0x0110)
  8133. },
  8134. {
  8135. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8136. PCI_VENDOR_ID_ADAPTEC2, 0x0608)
  8137. },
  8138. {
  8139. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8140. PCI_VENDOR_ID_ADAPTEC2, 0x0659)
  8141. },
  8142. {
  8143. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8144. PCI_VENDOR_ID_ADAPTEC2, 0x0800)
  8145. },
  8146. {
  8147. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8148. PCI_VENDOR_ID_ADAPTEC2, 0x0801)
  8149. },
  8150. {
  8151. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8152. PCI_VENDOR_ID_ADAPTEC2, 0x0802)
  8153. },
  8154. {
  8155. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8156. PCI_VENDOR_ID_ADAPTEC2, 0x0803)
  8157. },
  8158. {
  8159. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8160. PCI_VENDOR_ID_ADAPTEC2, 0x0804)
  8161. },
  8162. {
  8163. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8164. PCI_VENDOR_ID_ADAPTEC2, 0x0805)
  8165. },
  8166. {
  8167. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8168. PCI_VENDOR_ID_ADAPTEC2, 0x0806)
  8169. },
  8170. {
  8171. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8172. PCI_VENDOR_ID_ADAPTEC2, 0x0807)
  8173. },
  8174. {
  8175. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8176. PCI_VENDOR_ID_ADAPTEC2, 0x0808)
  8177. },
  8178. {
  8179. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8180. PCI_VENDOR_ID_ADAPTEC2, 0x0809)
  8181. },
  8182. {
  8183. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8184. PCI_VENDOR_ID_ADAPTEC2, 0x080a)
  8185. },
  8186. {
  8187. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8188. PCI_VENDOR_ID_ADAPTEC2, 0x0900)
  8189. },
  8190. {
  8191. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8192. PCI_VENDOR_ID_ADAPTEC2, 0x0901)
  8193. },
  8194. {
  8195. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8196. PCI_VENDOR_ID_ADAPTEC2, 0x0902)
  8197. },
  8198. {
  8199. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8200. PCI_VENDOR_ID_ADAPTEC2, 0x0903)
  8201. },
  8202. {
  8203. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8204. PCI_VENDOR_ID_ADAPTEC2, 0x0904)
  8205. },
  8206. {
  8207. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8208. PCI_VENDOR_ID_ADAPTEC2, 0x0905)
  8209. },
  8210. {
  8211. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8212. PCI_VENDOR_ID_ADAPTEC2, 0x0906)
  8213. },
  8214. {
  8215. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8216. PCI_VENDOR_ID_ADAPTEC2, 0x0907)
  8217. },
  8218. {
  8219. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8220. PCI_VENDOR_ID_ADAPTEC2, 0x0908)
  8221. },
  8222. {
  8223. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8224. PCI_VENDOR_ID_ADAPTEC2, 0x090a)
  8225. },
  8226. {
  8227. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8228. PCI_VENDOR_ID_ADAPTEC2, 0x1200)
  8229. },
  8230. {
  8231. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8232. PCI_VENDOR_ID_ADAPTEC2, 0x1201)
  8233. },
  8234. {
  8235. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8236. PCI_VENDOR_ID_ADAPTEC2, 0x1202)
  8237. },
  8238. {
  8239. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8240. PCI_VENDOR_ID_ADAPTEC2, 0x1280)
  8241. },
  8242. {
  8243. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8244. PCI_VENDOR_ID_ADAPTEC2, 0x1281)
  8245. },
  8246. {
  8247. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8248. PCI_VENDOR_ID_ADAPTEC2, 0x1282)
  8249. },
  8250. {
  8251. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8252. PCI_VENDOR_ID_ADAPTEC2, 0x1300)
  8253. },
  8254. {
  8255. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8256. PCI_VENDOR_ID_ADAPTEC2, 0x1301)
  8257. },
  8258. {
  8259. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8260. PCI_VENDOR_ID_ADAPTEC2, 0x1302)
  8261. },
  8262. {
  8263. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8264. PCI_VENDOR_ID_ADAPTEC2, 0x1303)
  8265. },
  8266. {
  8267. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8268. PCI_VENDOR_ID_ADAPTEC2, 0x1304)
  8269. },
  8270. {
  8271. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8272. PCI_VENDOR_ID_ADAPTEC2, 0x1380)
  8273. },
  8274. {
  8275. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8276. PCI_VENDOR_ID_ADAPTEC2, 0x1400)
  8277. },
  8278. {
  8279. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8280. PCI_VENDOR_ID_ADAPTEC2, 0x1402)
  8281. },
  8282. {
  8283. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8284. PCI_VENDOR_ID_ADAPTEC2, 0x1410)
  8285. },
  8286. {
  8287. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8288. PCI_VENDOR_ID_ADAPTEC2, 0x1411)
  8289. },
  8290. {
  8291. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8292. PCI_VENDOR_ID_ADAPTEC2, 0x1412)
  8293. },
  8294. {
  8295. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8296. PCI_VENDOR_ID_ADAPTEC2, 0x1420)
  8297. },
  8298. {
  8299. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8300. PCI_VENDOR_ID_ADAPTEC2, 0x1430)
  8301. },
  8302. {
  8303. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8304. PCI_VENDOR_ID_ADAPTEC2, 0x1440)
  8305. },
  8306. {
  8307. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8308. PCI_VENDOR_ID_ADAPTEC2, 0x1441)
  8309. },
  8310. {
  8311. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8312. PCI_VENDOR_ID_ADAPTEC2, 0x1450)
  8313. },
  8314. {
  8315. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8316. PCI_VENDOR_ID_ADAPTEC2, 0x1452)
  8317. },
  8318. {
  8319. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8320. PCI_VENDOR_ID_ADAPTEC2, 0x1460)
  8321. },
  8322. {
  8323. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8324. PCI_VENDOR_ID_ADAPTEC2, 0x1461)
  8325. },
  8326. {
  8327. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8328. PCI_VENDOR_ID_ADAPTEC2, 0x1462)
  8329. },
  8330. {
  8331. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8332. PCI_VENDOR_ID_ADAPTEC2, 0x1463)
  8333. },
  8334. {
  8335. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8336. PCI_VENDOR_ID_ADAPTEC2, 0x1470)
  8337. },
  8338. {
  8339. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8340. PCI_VENDOR_ID_ADAPTEC2, 0x1471)
  8341. },
  8342. {
  8343. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8344. PCI_VENDOR_ID_ADAPTEC2, 0x1472)
  8345. },
  8346. {
  8347. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8348. PCI_VENDOR_ID_ADAPTEC2, 0x1473)
  8349. },
  8350. {
  8351. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8352. PCI_VENDOR_ID_ADAPTEC2, 0x1474)
  8353. },
  8354. {
  8355. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8356. PCI_VENDOR_ID_ADAPTEC2, 0x1475)
  8357. },
  8358. {
  8359. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8360. PCI_VENDOR_ID_ADAPTEC2, 0x1480)
  8361. },
  8362. {
  8363. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8364. PCI_VENDOR_ID_ADAPTEC2, 0x1490)
  8365. },
  8366. {
  8367. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8368. PCI_VENDOR_ID_ADAPTEC2, 0x1491)
  8369. },
  8370. {
  8371. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8372. PCI_VENDOR_ID_ADAPTEC2, 0x14a0)
  8373. },
  8374. {
  8375. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8376. PCI_VENDOR_ID_ADAPTEC2, 0x14a1)
  8377. },
  8378. {
  8379. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8380. PCI_VENDOR_ID_ADAPTEC2, 0x14a2)
  8381. },
  8382. {
  8383. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8384. PCI_VENDOR_ID_ADAPTEC2, 0x14a4)
  8385. },
  8386. {
  8387. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8388. PCI_VENDOR_ID_ADAPTEC2, 0x14a5)
  8389. },
  8390. {
  8391. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8392. PCI_VENDOR_ID_ADAPTEC2, 0x14a6)
  8393. },
  8394. {
  8395. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8396. PCI_VENDOR_ID_ADAPTEC2, 0x14b0)
  8397. },
  8398. {
  8399. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8400. PCI_VENDOR_ID_ADAPTEC2, 0x14b1)
  8401. },
  8402. {
  8403. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8404. PCI_VENDOR_ID_ADAPTEC2, 0x14c0)
  8405. },
  8406. {
  8407. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8408. PCI_VENDOR_ID_ADAPTEC2, 0x14c1)
  8409. },
  8410. {
  8411. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8412. PCI_VENDOR_ID_ADAPTEC2, 0x14c2)
  8413. },
  8414. {
  8415. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8416. PCI_VENDOR_ID_ADAPTEC2, 0x14c3)
  8417. },
  8418. {
  8419. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8420. PCI_VENDOR_ID_ADAPTEC2, 0x14c4)
  8421. },
  8422. {
  8423. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8424. PCI_VENDOR_ID_ADAPTEC2, 0x14d0)
  8425. },
  8426. {
  8427. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8428. PCI_VENDOR_ID_ADAPTEC2, 0x14e0)
  8429. },
  8430. {
  8431. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8432. PCI_VENDOR_ID_ADAPTEC2, 0x14f0)
  8433. },
  8434. {
  8435. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8436. PCI_VENDOR_ID_ADVANTECH, 0x8312)
  8437. },
  8438. {
  8439. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8440. PCI_VENDOR_ID_DELL, 0x1fe0)
  8441. },
  8442. {
  8443. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8444. PCI_VENDOR_ID_HP, 0x0600)
  8445. },
  8446. {
  8447. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8448. PCI_VENDOR_ID_HP, 0x0601)
  8449. },
  8450. {
  8451. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8452. PCI_VENDOR_ID_HP, 0x0602)
  8453. },
  8454. {
  8455. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8456. PCI_VENDOR_ID_HP, 0x0603)
  8457. },
  8458. {
  8459. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8460. PCI_VENDOR_ID_HP, 0x0609)
  8461. },
  8462. {
  8463. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8464. PCI_VENDOR_ID_HP, 0x0650)
  8465. },
  8466. {
  8467. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8468. PCI_VENDOR_ID_HP, 0x0651)
  8469. },
  8470. {
  8471. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8472. PCI_VENDOR_ID_HP, 0x0652)
  8473. },
  8474. {
  8475. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8476. PCI_VENDOR_ID_HP, 0x0653)
  8477. },
  8478. {
  8479. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8480. PCI_VENDOR_ID_HP, 0x0654)
  8481. },
  8482. {
  8483. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8484. PCI_VENDOR_ID_HP, 0x0655)
  8485. },
  8486. {
  8487. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8488. PCI_VENDOR_ID_HP, 0x0700)
  8489. },
  8490. {
  8491. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8492. PCI_VENDOR_ID_HP, 0x0701)
  8493. },
  8494. {
  8495. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8496. PCI_VENDOR_ID_HP, 0x1001)
  8497. },
  8498. {
  8499. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8500. PCI_VENDOR_ID_HP, 0x1002)
  8501. },
  8502. {
  8503. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8504. PCI_VENDOR_ID_HP, 0x1100)
  8505. },
  8506. {
  8507. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8508. PCI_VENDOR_ID_HP, 0x1101)
  8509. },
  8510. {
  8511. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8512. 0x1590, 0x0294)
  8513. },
  8514. {
  8515. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8516. 0x1590, 0x02db)
  8517. },
  8518. {
  8519. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8520. 0x1590, 0x02dc)
  8521. },
  8522. {
  8523. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8524. 0x1590, 0x032e)
  8525. },
  8526. {
  8527. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8528. 0x1590, 0x036f)
  8529. },
  8530. {
  8531. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8532. 0x1590, 0x0381)
  8533. },
  8534. {
  8535. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8536. 0x1590, 0x0382)
  8537. },
  8538. {
  8539. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8540. 0x1590, 0x0383)
  8541. },
  8542. {
  8543. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8544. 0x1d8d, 0x0800)
  8545. },
  8546. {
  8547. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8548. 0x1d8d, 0x0908)
  8549. },
  8550. {
  8551. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8552. 0x1d8d, 0x0806)
  8553. },
  8554. {
  8555. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8556. 0x1d8d, 0x0916)
  8557. },
  8558. {
  8559. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8560. PCI_VENDOR_ID_GIGABYTE, 0x1000)
  8561. },
  8562. {
  8563. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8564. 0x1dfc, 0x3161)
  8565. },
  8566. {
  8567. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8568. 0x1f0c, 0x3161)
  8569. },
  8570. {
  8571. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8572. 0x1cf2, 0x0804)
  8573. },
  8574. {
  8575. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8576. 0x1cf2, 0x0805)
  8577. },
  8578. {
  8579. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8580. 0x1cf2, 0x0806)
  8581. },
  8582. {
  8583. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8584. 0x1cf2, 0x5445)
  8585. },
  8586. {
  8587. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8588. 0x1cf2, 0x5446)
  8589. },
  8590. {
  8591. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8592. 0x1cf2, 0x5447)
  8593. },
  8594. {
  8595. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8596. 0x1cf2, 0x5449)
  8597. },
  8598. {
  8599. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8600. 0x1cf2, 0x544a)
  8601. },
  8602. {
  8603. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8604. 0x1cf2, 0x544b)
  8605. },
  8606. {
  8607. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8608. 0x1cf2, 0x544d)
  8609. },
  8610. {
  8611. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8612. 0x1cf2, 0x544e)
  8613. },
  8614. {
  8615. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8616. 0x1cf2, 0x544f)
  8617. },
  8618. {
  8619. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8620. 0x1cf2, 0x54da)
  8621. },
  8622. {
  8623. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8624. 0x1cf2, 0x54db)
  8625. },
  8626. {
  8627. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8628. 0x1cf2, 0x54dc)
  8629. },
  8630. {
  8631. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8632. 0x1cf2, 0x0b27)
  8633. },
  8634. {
  8635. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8636. 0x1cf2, 0x0b29)
  8637. },
  8638. {
  8639. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8640. 0x1cf2, 0x0b45)
  8641. },
  8642. {
  8643. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8644. 0x1cc4, 0x0101)
  8645. },
  8646. {
  8647. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8648. 0x1cc4, 0x0201)
  8649. },
  8650. {
  8651. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8652. PCI_VENDOR_ID_LENOVO, 0x0220)
  8653. },
  8654. {
  8655. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8656. PCI_VENDOR_ID_LENOVO, 0x0221)
  8657. },
  8658. {
  8659. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8660. PCI_VENDOR_ID_LENOVO, 0x0520)
  8661. },
  8662. {
  8663. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8664. PCI_VENDOR_ID_LENOVO, 0x0522)
  8665. },
  8666. {
  8667. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8668. PCI_VENDOR_ID_LENOVO, 0x0620)
  8669. },
  8670. {
  8671. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8672. PCI_VENDOR_ID_LENOVO, 0x0621)
  8673. },
  8674. {
  8675. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8676. PCI_VENDOR_ID_LENOVO, 0x0622)
  8677. },
  8678. {
  8679. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8680. PCI_VENDOR_ID_LENOVO, 0x0623)
  8681. },
  8682. {
  8683. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8684. 0x1014, 0x0718)
  8685. },
  8686. {
  8687. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8688. 0x1137, 0x02f8)
  8689. },
  8690. {
  8691. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8692. 0x1137, 0x02f9)
  8693. },
  8694. {
  8695. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8696. 0x1137, 0x02fa)
  8697. },
  8698. {
  8699. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8700. 0x1137, 0x02fe)
  8701. },
  8702. {
  8703. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8704. 0x1137, 0x02ff)
  8705. },
  8706. {
  8707. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8708. 0x1137, 0x0300)
  8709. },
  8710. {
  8711. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8712. 0x1ff9, 0x0045)
  8713. },
  8714. {
  8715. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8716. 0x1ff9, 0x0046)
  8717. },
  8718. {
  8719. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8720. 0x1ff9, 0x0047)
  8721. },
  8722. {
  8723. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8724. 0x1ff9, 0x0048)
  8725. },
  8726. {
  8727. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8728. 0x1ff9, 0x004a)
  8729. },
  8730. {
  8731. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8732. 0x1ff9, 0x004b)
  8733. },
  8734. {
  8735. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8736. 0x1ff9, 0x004c)
  8737. },
  8738. {
  8739. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8740. 0x1ff9, 0x004f)
  8741. },
  8742. {
  8743. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8744. 0x1ff9, 0x0051)
  8745. },
  8746. {
  8747. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8748. 0x1ff9, 0x0052)
  8749. },
  8750. {
  8751. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8752. 0x1ff9, 0x0053)
  8753. },
  8754. {
  8755. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8756. 0x1ff9, 0x0054)
  8757. },
  8758. {
  8759. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8760. 0x1ff9, 0x006b)
  8761. },
  8762. {
  8763. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8764. 0x1ff9, 0x006c)
  8765. },
  8766. {
  8767. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8768. 0x1ff9, 0x006d)
  8769. },
  8770. {
  8771. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8772. 0x1ff9, 0x006f)
  8773. },
  8774. {
  8775. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8776. 0x1ff9, 0x0070)
  8777. },
  8778. {
  8779. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8780. 0x1ff9, 0x0071)
  8781. },
  8782. {
  8783. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8784. 0x1ff9, 0x0072)
  8785. },
  8786. {
  8787. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8788. 0x1ff9, 0x0086)
  8789. },
  8790. {
  8791. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8792. 0x1ff9, 0x0087)
  8793. },
  8794. {
  8795. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8796. 0x1ff9, 0x0088)
  8797. },
  8798. {
  8799. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8800. 0x1ff9, 0x0089)
  8801. },
  8802. {
  8803. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8804. 0x1e93, 0x1000)
  8805. },
  8806. {
  8807. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8808. 0x1e93, 0x1001)
  8809. },
  8810. {
  8811. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8812. 0x1e93, 0x1002)
  8813. },
  8814. {
  8815. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8816. 0x1e93, 0x1005)
  8817. },
  8818. {
  8819. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8820. 0x1f51, 0x1001)
  8821. },
  8822. {
  8823. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8824. 0x1f51, 0x1002)
  8825. },
  8826. {
  8827. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8828. 0x1f51, 0x1003)
  8829. },
  8830. {
  8831. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8832. 0x1f51, 0x1004)
  8833. },
  8834. {
  8835. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8836. 0x1f51, 0x1005)
  8837. },
  8838. {
  8839. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8840. 0x1f51, 0x1006)
  8841. },
  8842. {
  8843. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8844. 0x1f51, 0x1007)
  8845. },
  8846. {
  8847. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8848. 0x1f51, 0x1008)
  8849. },
  8850. {
  8851. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8852. 0x1f51, 0x1009)
  8853. },
  8854. {
  8855. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8856. 0x1f51, 0x100a)
  8857. },
  8858. {
  8859. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8860. 0x1f51, 0x100e)
  8861. },
  8862. {
  8863. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8864. 0x1f51, 0x100f)
  8865. },
  8866. {
  8867. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8868. 0x1f51, 0x1010)
  8869. },
  8870. {
  8871. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8872. 0x1f51, 0x1011)
  8873. },
  8874. {
  8875. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8876. 0x1f51, 0x1043)
  8877. },
  8878. {
  8879. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8880. 0x1f51, 0x1044)
  8881. },
  8882. {
  8883. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8884. 0x1f51, 0x1045)
  8885. },
  8886. {
  8887. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8888. 0x1ff9, 0x00a3)
  8889. },
  8890. {
  8891. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8892. PCI_ANY_ID, PCI_ANY_ID)
  8893. },
  8894. { 0 }
  8895. };
  8896. MODULE_DEVICE_TABLE(pci, pqi_pci_id_table);
  8897. static struct pci_driver pqi_pci_driver = {
  8898. .name = DRIVER_NAME_SHORT,
  8899. .id_table = pqi_pci_id_table,
  8900. .probe = pqi_pci_probe,
  8901. .remove = pqi_pci_remove,
  8902. .shutdown = pqi_shutdown,
  8903. #if defined(CONFIG_PM)
  8904. .driver = {
  8905. .pm = &pqi_pm_ops
  8906. },
  8907. #endif
  8908. };
  8909. static int __init pqi_init(void)
  8910. {
  8911. int rc;
  8912. pr_info(DRIVER_NAME "\n");
  8913. pqi_verify_structures();
  8914. sis_verify_structures();
  8915. pqi_sas_transport_template = sas_attach_transport(&pqi_sas_transport_functions);
  8916. if (!pqi_sas_transport_template)
  8917. return -ENODEV;
  8918. pqi_process_module_params();
  8919. rc = pci_register_driver(&pqi_pci_driver);
  8920. if (rc)
  8921. sas_release_transport(pqi_sas_transport_template);
  8922. return rc;
  8923. }
  8924. static void __exit pqi_cleanup(void)
  8925. {
  8926. pci_unregister_driver(&pqi_pci_driver);
  8927. sas_release_transport(pqi_sas_transport_template);
  8928. }
  8929. module_init(pqi_init);
  8930. module_exit(pqi_cleanup);
  8931. static void pqi_verify_structures(void)
  8932. {
  8933. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8934. sis_host_to_ctrl_doorbell) != 0x20);
  8935. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8936. sis_interrupt_mask) != 0x34);
  8937. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8938. sis_ctrl_to_host_doorbell) != 0x9c);
  8939. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8940. sis_ctrl_to_host_doorbell_clear) != 0xa0);
  8941. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8942. sis_driver_scratch) != 0xb0);
  8943. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8944. sis_product_identifier) != 0xb4);
  8945. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8946. sis_firmware_status) != 0xbc);
  8947. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8948. sis_ctrl_shutdown_reason_code) != 0xcc);
  8949. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8950. sis_mailbox) != 0x1000);
  8951. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8952. pqi_registers) != 0x4000);
  8953. BUILD_BUG_ON(offsetof(struct pqi_iu_header,
  8954. iu_type) != 0x0);
  8955. BUILD_BUG_ON(offsetof(struct pqi_iu_header,
  8956. iu_length) != 0x2);
  8957. BUILD_BUG_ON(offsetof(struct pqi_iu_header,
  8958. response_queue_id) != 0x4);
  8959. BUILD_BUG_ON(offsetof(struct pqi_iu_header,
  8960. driver_flags) != 0x6);
  8961. BUILD_BUG_ON(sizeof(struct pqi_iu_header) != 0x8);
  8962. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8963. status) != 0x0);
  8964. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8965. service_response) != 0x1);
  8966. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8967. data_present) != 0x2);
  8968. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8969. reserved) != 0x3);
  8970. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8971. residual_count) != 0x4);
  8972. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8973. data_length) != 0x8);
  8974. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8975. reserved1) != 0xa);
  8976. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8977. data) != 0xc);
  8978. BUILD_BUG_ON(sizeof(struct pqi_aio_error_info) != 0x10c);
  8979. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8980. data_in_result) != 0x0);
  8981. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8982. data_out_result) != 0x1);
  8983. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8984. reserved) != 0x2);
  8985. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8986. status) != 0x5);
  8987. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8988. status_qualifier) != 0x6);
  8989. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8990. sense_data_length) != 0x8);
  8991. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8992. response_data_length) != 0xa);
  8993. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8994. data_in_transferred) != 0xc);
  8995. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8996. data_out_transferred) != 0x10);
  8997. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8998. data) != 0x14);
  8999. BUILD_BUG_ON(sizeof(struct pqi_raid_error_info) != 0x114);
  9000. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9001. signature) != 0x0);
  9002. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9003. function_and_status_code) != 0x8);
  9004. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9005. max_admin_iq_elements) != 0x10);
  9006. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9007. max_admin_oq_elements) != 0x11);
  9008. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9009. admin_iq_element_length) != 0x12);
  9010. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9011. admin_oq_element_length) != 0x13);
  9012. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9013. max_reset_timeout) != 0x14);
  9014. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9015. legacy_intx_status) != 0x18);
  9016. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9017. legacy_intx_mask_set) != 0x1c);
  9018. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9019. legacy_intx_mask_clear) != 0x20);
  9020. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9021. device_status) != 0x40);
  9022. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9023. admin_iq_pi_offset) != 0x48);
  9024. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9025. admin_oq_ci_offset) != 0x50);
  9026. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9027. admin_iq_element_array_addr) != 0x58);
  9028. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9029. admin_oq_element_array_addr) != 0x60);
  9030. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9031. admin_iq_ci_addr) != 0x68);
  9032. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9033. admin_oq_pi_addr) != 0x70);
  9034. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9035. admin_iq_num_elements) != 0x78);
  9036. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9037. admin_oq_num_elements) != 0x79);
  9038. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9039. admin_queue_int_msg_num) != 0x7a);
  9040. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9041. device_error) != 0x80);
  9042. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9043. error_details) != 0x88);
  9044. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9045. device_reset) != 0x90);
  9046. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  9047. power_action) != 0x94);
  9048. BUILD_BUG_ON(sizeof(struct pqi_device_registers) != 0x100);
  9049. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9050. header.iu_type) != 0);
  9051. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9052. header.iu_length) != 2);
  9053. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9054. header.driver_flags) != 6);
  9055. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9056. request_id) != 8);
  9057. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9058. function_code) != 10);
  9059. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9060. data.report_device_capability.buffer_length) != 44);
  9061. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9062. data.report_device_capability.sg_descriptor) != 48);
  9063. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9064. data.create_operational_iq.queue_id) != 12);
  9065. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9066. data.create_operational_iq.element_array_addr) != 16);
  9067. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9068. data.create_operational_iq.ci_addr) != 24);
  9069. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9070. data.create_operational_iq.num_elements) != 32);
  9071. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9072. data.create_operational_iq.element_length) != 34);
  9073. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9074. data.create_operational_iq.queue_protocol) != 36);
  9075. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9076. data.create_operational_oq.queue_id) != 12);
  9077. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9078. data.create_operational_oq.element_array_addr) != 16);
  9079. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9080. data.create_operational_oq.pi_addr) != 24);
  9081. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9082. data.create_operational_oq.num_elements) != 32);
  9083. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9084. data.create_operational_oq.element_length) != 34);
  9085. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9086. data.create_operational_oq.queue_protocol) != 36);
  9087. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9088. data.create_operational_oq.int_msg_num) != 40);
  9089. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9090. data.create_operational_oq.coalescing_count) != 42);
  9091. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9092. data.create_operational_oq.min_coalescing_time) != 44);
  9093. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9094. data.create_operational_oq.max_coalescing_time) != 48);
  9095. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  9096. data.delete_operational_queue.queue_id) != 12);
  9097. BUILD_BUG_ON(sizeof(struct pqi_general_admin_request) != 64);
  9098. BUILD_BUG_ON(sizeof_field(struct pqi_general_admin_request,
  9099. data.create_operational_iq) != 64 - 11);
  9100. BUILD_BUG_ON(sizeof_field(struct pqi_general_admin_request,
  9101. data.create_operational_oq) != 64 - 11);
  9102. BUILD_BUG_ON(sizeof_field(struct pqi_general_admin_request,
  9103. data.delete_operational_queue) != 64 - 11);
  9104. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  9105. header.iu_type) != 0);
  9106. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  9107. header.iu_length) != 2);
  9108. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  9109. header.driver_flags) != 6);
  9110. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  9111. request_id) != 8);
  9112. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  9113. function_code) != 10);
  9114. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  9115. status) != 11);
  9116. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  9117. data.create_operational_iq.status_descriptor) != 12);
  9118. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  9119. data.create_operational_iq.iq_pi_offset) != 16);
  9120. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  9121. data.create_operational_oq.status_descriptor) != 12);
  9122. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  9123. data.create_operational_oq.oq_ci_offset) != 16);
  9124. BUILD_BUG_ON(sizeof(struct pqi_general_admin_response) != 64);
  9125. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  9126. header.iu_type) != 0);
  9127. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  9128. header.iu_length) != 2);
  9129. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  9130. header.response_queue_id) != 4);
  9131. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  9132. header.driver_flags) != 6);
  9133. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  9134. request_id) != 8);
  9135. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  9136. nexus_id) != 10);
  9137. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  9138. buffer_length) != 12);
  9139. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  9140. lun_number) != 16);
  9141. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  9142. protocol_specific) != 24);
  9143. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  9144. error_index) != 27);
  9145. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  9146. cdb) != 32);
  9147. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  9148. timeout) != 60);
  9149. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  9150. sg_descriptors) != 64);
  9151. BUILD_BUG_ON(sizeof(struct pqi_raid_path_request) !=
  9152. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  9153. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9154. header.iu_type) != 0);
  9155. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9156. header.iu_length) != 2);
  9157. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9158. header.response_queue_id) != 4);
  9159. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9160. header.driver_flags) != 6);
  9161. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9162. request_id) != 8);
  9163. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9164. nexus_id) != 12);
  9165. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9166. buffer_length) != 16);
  9167. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9168. data_encryption_key_index) != 22);
  9169. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9170. encrypt_tweak_lower) != 24);
  9171. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9172. encrypt_tweak_upper) != 28);
  9173. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9174. cdb) != 32);
  9175. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9176. error_index) != 48);
  9177. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9178. num_sg_descriptors) != 50);
  9179. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9180. cdb_length) != 51);
  9181. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9182. lun_number) != 52);
  9183. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  9184. sg_descriptors) != 64);
  9185. BUILD_BUG_ON(sizeof(struct pqi_aio_path_request) !=
  9186. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  9187. BUILD_BUG_ON(offsetof(struct pqi_io_response,
  9188. header.iu_type) != 0);
  9189. BUILD_BUG_ON(offsetof(struct pqi_io_response,
  9190. header.iu_length) != 2);
  9191. BUILD_BUG_ON(offsetof(struct pqi_io_response,
  9192. request_id) != 8);
  9193. BUILD_BUG_ON(offsetof(struct pqi_io_response,
  9194. error_index) != 10);
  9195. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  9196. header.iu_type) != 0);
  9197. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  9198. header.iu_length) != 2);
  9199. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  9200. header.response_queue_id) != 4);
  9201. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  9202. request_id) != 8);
  9203. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  9204. data.report_event_configuration.buffer_length) != 12);
  9205. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  9206. data.report_event_configuration.sg_descriptors) != 16);
  9207. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  9208. data.set_event_configuration.global_event_oq_id) != 10);
  9209. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  9210. data.set_event_configuration.buffer_length) != 12);
  9211. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  9212. data.set_event_configuration.sg_descriptors) != 16);
  9213. BUILD_BUG_ON(offsetof(struct pqi_iu_layer_descriptor,
  9214. max_inbound_iu_length) != 6);
  9215. BUILD_BUG_ON(offsetof(struct pqi_iu_layer_descriptor,
  9216. max_outbound_iu_length) != 14);
  9217. BUILD_BUG_ON(sizeof(struct pqi_iu_layer_descriptor) != 16);
  9218. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9219. data_length) != 0);
  9220. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9221. iq_arbitration_priority_support_bitmask) != 8);
  9222. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9223. maximum_aw_a) != 9);
  9224. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9225. maximum_aw_b) != 10);
  9226. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9227. maximum_aw_c) != 11);
  9228. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9229. max_inbound_queues) != 16);
  9230. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9231. max_elements_per_iq) != 18);
  9232. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9233. max_iq_element_length) != 24);
  9234. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9235. min_iq_element_length) != 26);
  9236. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9237. max_outbound_queues) != 30);
  9238. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9239. max_elements_per_oq) != 32);
  9240. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9241. intr_coalescing_time_granularity) != 34);
  9242. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9243. max_oq_element_length) != 36);
  9244. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9245. min_oq_element_length) != 38);
  9246. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  9247. iu_layer_descriptors) != 64);
  9248. BUILD_BUG_ON(sizeof(struct pqi_device_capability) != 576);
  9249. BUILD_BUG_ON(offsetof(struct pqi_event_descriptor,
  9250. event_type) != 0);
  9251. BUILD_BUG_ON(offsetof(struct pqi_event_descriptor,
  9252. oq_id) != 2);
  9253. BUILD_BUG_ON(sizeof(struct pqi_event_descriptor) != 4);
  9254. BUILD_BUG_ON(offsetof(struct pqi_event_config,
  9255. num_event_descriptors) != 2);
  9256. BUILD_BUG_ON(offsetof(struct pqi_event_config,
  9257. descriptors) != 4);
  9258. BUILD_BUG_ON(PQI_NUM_SUPPORTED_EVENTS !=
  9259. ARRAY_SIZE(pqi_supported_event_types));
  9260. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  9261. header.iu_type) != 0);
  9262. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  9263. header.iu_length) != 2);
  9264. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  9265. event_type) != 8);
  9266. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  9267. event_id) != 10);
  9268. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  9269. additional_event_id) != 12);
  9270. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  9271. data) != 16);
  9272. BUILD_BUG_ON(sizeof(struct pqi_event_response) != 32);
  9273. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  9274. header.iu_type) != 0);
  9275. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  9276. header.iu_length) != 2);
  9277. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  9278. event_type) != 8);
  9279. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  9280. event_id) != 10);
  9281. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  9282. additional_event_id) != 12);
  9283. BUILD_BUG_ON(sizeof(struct pqi_event_acknowledge_request) != 16);
  9284. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  9285. header.iu_type) != 0);
  9286. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  9287. header.iu_length) != 2);
  9288. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  9289. request_id) != 8);
  9290. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  9291. nexus_id) != 10);
  9292. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  9293. timeout) != 14);
  9294. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  9295. lun_number) != 16);
  9296. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  9297. protocol_specific) != 24);
  9298. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  9299. outbound_queue_id_to_manage) != 26);
  9300. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  9301. request_id_to_manage) != 28);
  9302. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  9303. task_management_function) != 30);
  9304. BUILD_BUG_ON(sizeof(struct pqi_task_management_request) != 32);
  9305. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  9306. header.iu_type) != 0);
  9307. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  9308. header.iu_length) != 2);
  9309. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  9310. request_id) != 8);
  9311. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  9312. nexus_id) != 10);
  9313. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  9314. additional_response_info) != 12);
  9315. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  9316. response_code) != 15);
  9317. BUILD_BUG_ON(sizeof(struct pqi_task_management_response) != 16);
  9318. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  9319. configured_logical_drive_count) != 0);
  9320. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  9321. configuration_signature) != 1);
  9322. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  9323. firmware_version_short) != 5);
  9324. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  9325. extended_logical_unit_count) != 154);
  9326. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  9327. firmware_build_number) != 190);
  9328. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  9329. vendor_id) != 200);
  9330. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  9331. product_id) != 208);
  9332. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  9333. extra_controller_flags) != 286);
  9334. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  9335. controller_mode) != 292);
  9336. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  9337. spare_part_number) != 293);
  9338. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  9339. firmware_version_long) != 325);
  9340. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  9341. phys_bay_in_box) != 115);
  9342. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  9343. device_type) != 120);
  9344. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  9345. redundant_path_present_map) != 1736);
  9346. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  9347. active_path_number) != 1738);
  9348. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  9349. alternate_paths_phys_connector) != 1739);
  9350. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  9351. alternate_paths_phys_box_on_port) != 1755);
  9352. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  9353. current_queue_depth_limit) != 1796);
  9354. BUILD_BUG_ON(sizeof(struct bmic_identify_physical_device) != 2560);
  9355. BUILD_BUG_ON(sizeof(struct bmic_sense_feature_buffer_header) != 4);
  9356. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_buffer_header,
  9357. page_code) != 0);
  9358. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_buffer_header,
  9359. subpage_code) != 1);
  9360. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_buffer_header,
  9361. buffer_length) != 2);
  9362. BUILD_BUG_ON(sizeof(struct bmic_sense_feature_page_header) != 4);
  9363. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_page_header,
  9364. page_code) != 0);
  9365. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_page_header,
  9366. subpage_code) != 1);
  9367. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_page_header,
  9368. page_length) != 2);
  9369. BUILD_BUG_ON(sizeof(struct bmic_sense_feature_io_page_aio_subpage)
  9370. != 18);
  9371. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  9372. header) != 0);
  9373. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  9374. firmware_read_support) != 4);
  9375. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  9376. driver_read_support) != 5);
  9377. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  9378. firmware_write_support) != 6);
  9379. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  9380. driver_write_support) != 7);
  9381. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  9382. max_transfer_encrypted_sas_sata) != 8);
  9383. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  9384. max_transfer_encrypted_nvme) != 10);
  9385. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  9386. max_write_raid_5_6) != 12);
  9387. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  9388. max_write_raid_1_10_2drive) != 14);
  9389. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  9390. max_write_raid_1_10_3drive) != 16);
  9391. BUILD_BUG_ON(PQI_ADMIN_IQ_NUM_ELEMENTS > 255);
  9392. BUILD_BUG_ON(PQI_ADMIN_OQ_NUM_ELEMENTS > 255);
  9393. BUILD_BUG_ON(PQI_ADMIN_IQ_ELEMENT_LENGTH %
  9394. PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT != 0);
  9395. BUILD_BUG_ON(PQI_ADMIN_OQ_ELEMENT_LENGTH %
  9396. PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT != 0);
  9397. BUILD_BUG_ON(PQI_OPERATIONAL_IQ_ELEMENT_LENGTH > 1048560);
  9398. BUILD_BUG_ON(PQI_OPERATIONAL_IQ_ELEMENT_LENGTH %
  9399. PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT != 0);
  9400. BUILD_BUG_ON(PQI_OPERATIONAL_OQ_ELEMENT_LENGTH > 1048560);
  9401. BUILD_BUG_ON(PQI_OPERATIONAL_OQ_ELEMENT_LENGTH %
  9402. PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT != 0);
  9403. BUILD_BUG_ON(PQI_RESERVED_IO_SLOTS >= PQI_MAX_OUTSTANDING_REQUESTS);
  9404. BUILD_BUG_ON(PQI_RESERVED_IO_SLOTS >=
  9405. PQI_MAX_OUTSTANDING_REQUESTS_KDUMP);
  9406. }