xhci-rcar.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * xHCI host controller driver for R-Car SoCs
  4. *
  5. * Copyright (C) 2014 Renesas Electronics Corporation
  6. */
  7. #include <linux/firmware.h>
  8. #include <linux/iopoll.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/of.h>
  12. #include <linux/usb/phy.h>
  13. #include "xhci.h"
  14. #include "xhci-plat.h"
  15. #include "xhci-rzv2m.h"
  16. #define XHCI_RCAR_FIRMWARE_NAME_V1 "r8a779x_usb3_v1.dlmem"
  17. #define XHCI_RCAR_FIRMWARE_NAME_V3 "r8a779x_usb3_v3.dlmem"
  18. /*
  19. * - The V3 firmware is for all R-Car Gen3
  20. * - The V2 firmware is possible to use on R-Car Gen2. However, the V2 causes
  21. * performance degradation. So, this driver continues to use the V1 if R-Car
  22. * Gen2.
  23. * - The V1 firmware is impossible to use on R-Car Gen3.
  24. */
  25. MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V1);
  26. MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3);
  27. /*** Register Offset ***/
  28. #define RCAR_USB3_AXH_STA 0x104 /* AXI Host Control Status */
  29. #define RCAR_USB3_INT_ENA 0x224 /* Interrupt Enable */
  30. #define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */
  31. #define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */
  32. #define RCAR_USB3_LCLK 0xa44 /* LCLK Select */
  33. #define RCAR_USB3_CONF1 0xa48 /* USB3.0 Configuration1 */
  34. #define RCAR_USB3_CONF2 0xa5c /* USB3.0 Configuration2 */
  35. #define RCAR_USB3_CONF3 0xaa8 /* USB3.0 Configuration3 */
  36. #define RCAR_USB3_RX_POL 0xab0 /* USB3.0 RX Polarity */
  37. #define RCAR_USB3_TX_POL 0xab8 /* USB3.0 TX Polarity */
  38. /*** Register Settings ***/
  39. /* AXI Host Control Status */
  40. #define RCAR_USB3_AXH_STA_B3_PLL_ACTIVE 0x00010000
  41. #define RCAR_USB3_AXH_STA_B2_PLL_ACTIVE 0x00000001
  42. #define RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK (RCAR_USB3_AXH_STA_B3_PLL_ACTIVE | \
  43. RCAR_USB3_AXH_STA_B2_PLL_ACTIVE)
  44. /* Interrupt Enable */
  45. #define RCAR_USB3_INT_XHC_ENA 0x00000001
  46. #define RCAR_USB3_INT_PME_ENA 0x00000002
  47. #define RCAR_USB3_INT_HSE_ENA 0x00000004
  48. #define RCAR_USB3_INT_ENA_VAL (RCAR_USB3_INT_XHC_ENA | \
  49. RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA)
  50. /* FW Download Control & Status */
  51. #define RCAR_USB3_DL_CTRL_ENABLE 0x00000001
  52. #define RCAR_USB3_DL_CTRL_FW_SUCCESS 0x00000010
  53. #define RCAR_USB3_DL_CTRL_FW_SET_DATA0 0x00000100
  54. /* LCLK Select */
  55. #define RCAR_USB3_LCLK_ENA_VAL 0x01030001
  56. /* USB3.0 Configuration */
  57. #define RCAR_USB3_CONF1_VAL 0x00030204
  58. #define RCAR_USB3_CONF2_VAL 0x00030300
  59. #define RCAR_USB3_CONF3_VAL 0x13802007
  60. /* USB3.0 Polarity */
  61. #define RCAR_USB3_RX_POL_VAL BIT(21)
  62. #define RCAR_USB3_TX_POL_VAL BIT(4)
  63. static void xhci_rcar_start_gen2(struct usb_hcd *hcd)
  64. {
  65. /* LCLK Select */
  66. writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK);
  67. /* USB3.0 Configuration */
  68. writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1);
  69. writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2);
  70. writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3);
  71. /* USB3.0 Polarity */
  72. writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL);
  73. writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL);
  74. }
  75. static int xhci_rcar_is_gen2(struct device *dev)
  76. {
  77. struct device_node *node = dev->of_node;
  78. return of_device_is_compatible(node, "renesas,xhci-r8a7790") ||
  79. of_device_is_compatible(node, "renesas,xhci-r8a7791") ||
  80. of_device_is_compatible(node, "renesas,xhci-r8a7793") ||
  81. of_device_is_compatible(node, "renesas,rcar-gen2-xhci");
  82. }
  83. static void xhci_rcar_start(struct usb_hcd *hcd)
  84. {
  85. u32 temp;
  86. if (hcd->regs != NULL) {
  87. /* Interrupt Enable */
  88. temp = readl(hcd->regs + RCAR_USB3_INT_ENA);
  89. temp |= RCAR_USB3_INT_ENA_VAL;
  90. writel(temp, hcd->regs + RCAR_USB3_INT_ENA);
  91. if (xhci_rcar_is_gen2(hcd->self.controller))
  92. xhci_rcar_start_gen2(hcd);
  93. }
  94. }
  95. static int xhci_rcar_download_firmware(struct usb_hcd *hcd)
  96. {
  97. struct device *dev = hcd->self.controller;
  98. void __iomem *regs = hcd->regs;
  99. struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
  100. const struct firmware *fw;
  101. int retval, index, j;
  102. u32 data, val, temp;
  103. /*
  104. * According to the datasheet, "Upon the completion of FW Download,
  105. * there is no need to write or reload FW".
  106. */
  107. if (readl(regs + RCAR_USB3_DL_CTRL) & RCAR_USB3_DL_CTRL_FW_SUCCESS)
  108. return 0;
  109. /* request R-Car USB3.0 firmware */
  110. retval = request_firmware(&fw, priv->firmware_name, dev);
  111. if (retval)
  112. return retval;
  113. /* download R-Car USB3.0 firmware */
  114. temp = readl(regs + RCAR_USB3_DL_CTRL);
  115. temp |= RCAR_USB3_DL_CTRL_ENABLE;
  116. writel(temp, regs + RCAR_USB3_DL_CTRL);
  117. for (index = 0; index < fw->size; index += 4) {
  118. /* to avoid reading beyond the end of the buffer */
  119. for (data = 0, j = 3; j >= 0; j--) {
  120. if ((j + index) < fw->size)
  121. data |= fw->data[index + j] << (8 * j);
  122. }
  123. writel(data, regs + RCAR_USB3_FW_DATA0);
  124. temp = readl(regs + RCAR_USB3_DL_CTRL);
  125. temp |= RCAR_USB3_DL_CTRL_FW_SET_DATA0;
  126. writel(temp, regs + RCAR_USB3_DL_CTRL);
  127. retval = readl_poll_timeout_atomic(regs + RCAR_USB3_DL_CTRL,
  128. val, !(val & RCAR_USB3_DL_CTRL_FW_SET_DATA0),
  129. 1, 10000);
  130. if (retval < 0)
  131. break;
  132. }
  133. temp = readl(regs + RCAR_USB3_DL_CTRL);
  134. temp &= ~RCAR_USB3_DL_CTRL_ENABLE;
  135. writel(temp, regs + RCAR_USB3_DL_CTRL);
  136. retval = readl_poll_timeout_atomic((regs + RCAR_USB3_DL_CTRL),
  137. val, val & RCAR_USB3_DL_CTRL_FW_SUCCESS, 1, 10000);
  138. release_firmware(fw);
  139. return retval;
  140. }
  141. static bool xhci_rcar_wait_for_pll_active(struct usb_hcd *hcd)
  142. {
  143. int retval;
  144. u32 val, mask = RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK;
  145. retval = readl_poll_timeout_atomic(hcd->regs + RCAR_USB3_AXH_STA,
  146. val, (val & mask) == mask, 1, 1000);
  147. return !retval;
  148. }
  149. /* This function needs to initialize a "phy" of usb before */
  150. static int xhci_rcar_init_quirk(struct usb_hcd *hcd)
  151. {
  152. /* If hcd->regs is NULL, we don't just call the following function */
  153. if (!hcd->regs)
  154. return 0;
  155. if (!xhci_rcar_wait_for_pll_active(hcd))
  156. return -ETIMEDOUT;
  157. return xhci_rcar_download_firmware(hcd);
  158. }
  159. static int xhci_rcar_resume_quirk(struct usb_hcd *hcd)
  160. {
  161. int ret;
  162. ret = xhci_rcar_download_firmware(hcd);
  163. if (!ret)
  164. xhci_rcar_start(hcd);
  165. return ret;
  166. }
  167. /*
  168. * On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set
  169. * to 1. However, these SoCs don't support 64-bit address memory
  170. * pointers. So, this driver clears the AC64 bit of xhci->hcc_params
  171. * to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in
  172. * xhci_gen_setup() by using the XHCI_NO_64BIT_SUPPORT quirk.
  173. *
  174. * And, since the firmware/internal CPU control the USBSTS.STS_HALT
  175. * and the process speed is down when the roothub port enters U3,
  176. * long delay for the handshake of STS_HALT is neeed in xhci_suspend()
  177. * by using the XHCI_SLOW_SUSPEND quirk.
  178. */
  179. #define SET_XHCI_PLAT_PRIV_FOR_RCAR(firmware) \
  180. .firmware_name = firmware, \
  181. .quirks = XHCI_NO_64BIT_SUPPORT | XHCI_SLOW_SUSPEND, \
  182. .init_quirk = xhci_rcar_init_quirk, \
  183. .plat_start = xhci_rcar_start, \
  184. .resume_quirk = xhci_rcar_resume_quirk,
  185. static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen2 = {
  186. SET_XHCI_PLAT_PRIV_FOR_RCAR(XHCI_RCAR_FIRMWARE_NAME_V1)
  187. };
  188. static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen3 = {
  189. SET_XHCI_PLAT_PRIV_FOR_RCAR(XHCI_RCAR_FIRMWARE_NAME_V3)
  190. };
  191. static const struct xhci_plat_priv xhci_plat_renesas_rzv2m = {
  192. .quirks = XHCI_NO_64BIT_SUPPORT | XHCI_SLOW_SUSPEND,
  193. .init_quirk = xhci_rzv2m_init_quirk,
  194. .plat_start = xhci_rzv2m_start,
  195. };
  196. static const struct of_device_id usb_xhci_of_match[] = {
  197. {
  198. .compatible = "renesas,xhci-r8a7790",
  199. .data = &xhci_plat_renesas_rcar_gen2,
  200. }, {
  201. .compatible = "renesas,xhci-r8a7791",
  202. .data = &xhci_plat_renesas_rcar_gen2,
  203. }, {
  204. .compatible = "renesas,xhci-r8a7793",
  205. .data = &xhci_plat_renesas_rcar_gen2,
  206. }, {
  207. .compatible = "renesas,xhci-r8a7795",
  208. .data = &xhci_plat_renesas_rcar_gen3,
  209. }, {
  210. .compatible = "renesas,xhci-r8a7796",
  211. .data = &xhci_plat_renesas_rcar_gen3,
  212. }, {
  213. .compatible = "renesas,rcar-gen2-xhci",
  214. .data = &xhci_plat_renesas_rcar_gen2,
  215. }, {
  216. .compatible = "renesas,rcar-gen3-xhci",
  217. .data = &xhci_plat_renesas_rcar_gen3,
  218. }, {
  219. .compatible = "renesas,rzv2m-xhci",
  220. .data = &xhci_plat_renesas_rzv2m,
  221. },
  222. { },
  223. };
  224. MODULE_DEVICE_TABLE(of, usb_xhci_of_match);
  225. static int xhci_renesas_probe(struct platform_device *pdev)
  226. {
  227. const struct xhci_plat_priv *priv_match;
  228. priv_match = of_device_get_match_data(&pdev->dev);
  229. return xhci_plat_probe(pdev, NULL, priv_match);
  230. }
  231. static struct platform_driver usb_xhci_renesas_driver = {
  232. .probe = xhci_renesas_probe,
  233. .remove_new = xhci_plat_remove,
  234. .shutdown = usb_hcd_platform_shutdown,
  235. .driver = {
  236. .name = "xhci-renesas-hcd",
  237. .pm = &xhci_plat_pm_ops,
  238. .of_match_table = usb_xhci_of_match,
  239. },
  240. };
  241. module_platform_driver(usb_xhci_renesas_driver);
  242. MODULE_DESCRIPTION("xHCI Platform Host Controller Driver for Renesas R-Car and RZ");
  243. MODULE_LICENSE("GPL");