main.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved
  4. */
  5. #include <linux/device.h>
  6. #include <linux/module.h>
  7. #include <linux/mutex.h>
  8. #include <linux/pci.h>
  9. #include <linux/pm_runtime.h>
  10. #include <linux/types.h>
  11. #include <linux/uaccess.h>
  12. #include <linux/vfio.h>
  13. #include <linux/vfio_pci_core.h>
  14. #include <linux/virtio_pci.h>
  15. #include <linux/virtio_net.h>
  16. #include <linux/virtio_pci_admin.h>
  17. struct virtiovf_pci_core_device {
  18. struct vfio_pci_core_device core_device;
  19. u8 *bar0_virtual_buf;
  20. /* synchronize access to the virtual buf */
  21. struct mutex bar_mutex;
  22. void __iomem *notify_addr;
  23. u64 notify_offset;
  24. __le32 pci_base_addr_0;
  25. __le16 pci_cmd;
  26. u8 bar0_virtual_buf_size;
  27. u8 notify_bar;
  28. };
  29. static int
  30. virtiovf_issue_legacy_rw_cmd(struct virtiovf_pci_core_device *virtvdev,
  31. loff_t pos, char __user *buf,
  32. size_t count, bool read)
  33. {
  34. bool msix_enabled =
  35. (virtvdev->core_device.irq_type == VFIO_PCI_MSIX_IRQ_INDEX);
  36. struct pci_dev *pdev = virtvdev->core_device.pdev;
  37. u8 *bar0_buf = virtvdev->bar0_virtual_buf;
  38. bool common;
  39. u8 offset;
  40. int ret;
  41. common = pos < VIRTIO_PCI_CONFIG_OFF(msix_enabled);
  42. /* offset within the relevant configuration area */
  43. offset = common ? pos : pos - VIRTIO_PCI_CONFIG_OFF(msix_enabled);
  44. mutex_lock(&virtvdev->bar_mutex);
  45. if (read) {
  46. if (common)
  47. ret = virtio_pci_admin_legacy_common_io_read(pdev, offset,
  48. count, bar0_buf + pos);
  49. else
  50. ret = virtio_pci_admin_legacy_device_io_read(pdev, offset,
  51. count, bar0_buf + pos);
  52. if (ret)
  53. goto out;
  54. if (copy_to_user(buf, bar0_buf + pos, count))
  55. ret = -EFAULT;
  56. } else {
  57. if (copy_from_user(bar0_buf + pos, buf, count)) {
  58. ret = -EFAULT;
  59. goto out;
  60. }
  61. if (common)
  62. ret = virtio_pci_admin_legacy_common_io_write(pdev, offset,
  63. count, bar0_buf + pos);
  64. else
  65. ret = virtio_pci_admin_legacy_device_io_write(pdev, offset,
  66. count, bar0_buf + pos);
  67. }
  68. out:
  69. mutex_unlock(&virtvdev->bar_mutex);
  70. return ret;
  71. }
  72. static int
  73. virtiovf_pci_bar0_rw(struct virtiovf_pci_core_device *virtvdev,
  74. loff_t pos, char __user *buf,
  75. size_t count, bool read)
  76. {
  77. struct vfio_pci_core_device *core_device = &virtvdev->core_device;
  78. struct pci_dev *pdev = core_device->pdev;
  79. u16 queue_notify;
  80. int ret;
  81. if (!(le16_to_cpu(virtvdev->pci_cmd) & PCI_COMMAND_IO))
  82. return -EIO;
  83. if (pos + count > virtvdev->bar0_virtual_buf_size)
  84. return -EINVAL;
  85. ret = pm_runtime_resume_and_get(&pdev->dev);
  86. if (ret) {
  87. pci_info_ratelimited(pdev, "runtime resume failed %d\n", ret);
  88. return -EIO;
  89. }
  90. switch (pos) {
  91. case VIRTIO_PCI_QUEUE_NOTIFY:
  92. if (count != sizeof(queue_notify)) {
  93. ret = -EINVAL;
  94. goto end;
  95. }
  96. if (read) {
  97. ret = vfio_pci_core_ioread16(core_device, true, &queue_notify,
  98. virtvdev->notify_addr);
  99. if (ret)
  100. goto end;
  101. if (copy_to_user(buf, &queue_notify,
  102. sizeof(queue_notify))) {
  103. ret = -EFAULT;
  104. goto end;
  105. }
  106. } else {
  107. if (copy_from_user(&queue_notify, buf, count)) {
  108. ret = -EFAULT;
  109. goto end;
  110. }
  111. ret = vfio_pci_core_iowrite16(core_device, true, queue_notify,
  112. virtvdev->notify_addr);
  113. }
  114. break;
  115. default:
  116. ret = virtiovf_issue_legacy_rw_cmd(virtvdev, pos, buf, count,
  117. read);
  118. }
  119. end:
  120. pm_runtime_put(&pdev->dev);
  121. return ret ? ret : count;
  122. }
  123. static ssize_t virtiovf_pci_read_config(struct vfio_device *core_vdev,
  124. char __user *buf, size_t count,
  125. loff_t *ppos)
  126. {
  127. struct virtiovf_pci_core_device *virtvdev = container_of(
  128. core_vdev, struct virtiovf_pci_core_device, core_device.vdev);
  129. loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
  130. size_t register_offset;
  131. loff_t copy_offset;
  132. size_t copy_count;
  133. __le32 val32;
  134. __le16 val16;
  135. u8 val8;
  136. int ret;
  137. ret = vfio_pci_core_read(core_vdev, buf, count, ppos);
  138. if (ret < 0)
  139. return ret;
  140. if (vfio_pci_core_range_intersect_range(pos, count, PCI_DEVICE_ID,
  141. sizeof(val16), &copy_offset,
  142. &copy_count, &register_offset)) {
  143. val16 = cpu_to_le16(VIRTIO_TRANS_ID_NET);
  144. if (copy_to_user(buf + copy_offset, (void *)&val16 + register_offset, copy_count))
  145. return -EFAULT;
  146. }
  147. if ((le16_to_cpu(virtvdev->pci_cmd) & PCI_COMMAND_IO) &&
  148. vfio_pci_core_range_intersect_range(pos, count, PCI_COMMAND,
  149. sizeof(val16), &copy_offset,
  150. &copy_count, &register_offset)) {
  151. if (copy_from_user((void *)&val16 + register_offset, buf + copy_offset,
  152. copy_count))
  153. return -EFAULT;
  154. val16 |= cpu_to_le16(PCI_COMMAND_IO);
  155. if (copy_to_user(buf + copy_offset, (void *)&val16 + register_offset,
  156. copy_count))
  157. return -EFAULT;
  158. }
  159. if (vfio_pci_core_range_intersect_range(pos, count, PCI_REVISION_ID,
  160. sizeof(val8), &copy_offset,
  161. &copy_count, &register_offset)) {
  162. /* Transional needs to have revision 0 */
  163. val8 = 0;
  164. if (copy_to_user(buf + copy_offset, &val8, copy_count))
  165. return -EFAULT;
  166. }
  167. if (vfio_pci_core_range_intersect_range(pos, count, PCI_BASE_ADDRESS_0,
  168. sizeof(val32), &copy_offset,
  169. &copy_count, &register_offset)) {
  170. u32 bar_mask = ~(virtvdev->bar0_virtual_buf_size - 1);
  171. u32 pci_base_addr_0 = le32_to_cpu(virtvdev->pci_base_addr_0);
  172. val32 = cpu_to_le32((pci_base_addr_0 & bar_mask) | PCI_BASE_ADDRESS_SPACE_IO);
  173. if (copy_to_user(buf + copy_offset, (void *)&val32 + register_offset, copy_count))
  174. return -EFAULT;
  175. }
  176. if (vfio_pci_core_range_intersect_range(pos, count, PCI_SUBSYSTEM_ID,
  177. sizeof(val16), &copy_offset,
  178. &copy_count, &register_offset)) {
  179. /*
  180. * Transitional devices use the PCI subsystem device id as
  181. * virtio device id, same as legacy driver always did.
  182. */
  183. val16 = cpu_to_le16(VIRTIO_ID_NET);
  184. if (copy_to_user(buf + copy_offset, (void *)&val16 + register_offset,
  185. copy_count))
  186. return -EFAULT;
  187. }
  188. if (vfio_pci_core_range_intersect_range(pos, count, PCI_SUBSYSTEM_VENDOR_ID,
  189. sizeof(val16), &copy_offset,
  190. &copy_count, &register_offset)) {
  191. val16 = cpu_to_le16(PCI_VENDOR_ID_REDHAT_QUMRANET);
  192. if (copy_to_user(buf + copy_offset, (void *)&val16 + register_offset,
  193. copy_count))
  194. return -EFAULT;
  195. }
  196. return count;
  197. }
  198. static ssize_t
  199. virtiovf_pci_core_read(struct vfio_device *core_vdev, char __user *buf,
  200. size_t count, loff_t *ppos)
  201. {
  202. struct virtiovf_pci_core_device *virtvdev = container_of(
  203. core_vdev, struct virtiovf_pci_core_device, core_device.vdev);
  204. unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos);
  205. loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
  206. if (!count)
  207. return 0;
  208. if (index == VFIO_PCI_CONFIG_REGION_INDEX)
  209. return virtiovf_pci_read_config(core_vdev, buf, count, ppos);
  210. if (index == VFIO_PCI_BAR0_REGION_INDEX)
  211. return virtiovf_pci_bar0_rw(virtvdev, pos, buf, count, true);
  212. return vfio_pci_core_read(core_vdev, buf, count, ppos);
  213. }
  214. static ssize_t virtiovf_pci_write_config(struct vfio_device *core_vdev,
  215. const char __user *buf, size_t count,
  216. loff_t *ppos)
  217. {
  218. struct virtiovf_pci_core_device *virtvdev = container_of(
  219. core_vdev, struct virtiovf_pci_core_device, core_device.vdev);
  220. loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
  221. size_t register_offset;
  222. loff_t copy_offset;
  223. size_t copy_count;
  224. if (vfio_pci_core_range_intersect_range(pos, count, PCI_COMMAND,
  225. sizeof(virtvdev->pci_cmd),
  226. &copy_offset, &copy_count,
  227. &register_offset)) {
  228. if (copy_from_user((void *)&virtvdev->pci_cmd + register_offset,
  229. buf + copy_offset,
  230. copy_count))
  231. return -EFAULT;
  232. }
  233. if (vfio_pci_core_range_intersect_range(pos, count, PCI_BASE_ADDRESS_0,
  234. sizeof(virtvdev->pci_base_addr_0),
  235. &copy_offset, &copy_count,
  236. &register_offset)) {
  237. if (copy_from_user((void *)&virtvdev->pci_base_addr_0 + register_offset,
  238. buf + copy_offset,
  239. copy_count))
  240. return -EFAULT;
  241. }
  242. return vfio_pci_core_write(core_vdev, buf, count, ppos);
  243. }
  244. static ssize_t
  245. virtiovf_pci_core_write(struct vfio_device *core_vdev, const char __user *buf,
  246. size_t count, loff_t *ppos)
  247. {
  248. struct virtiovf_pci_core_device *virtvdev = container_of(
  249. core_vdev, struct virtiovf_pci_core_device, core_device.vdev);
  250. unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos);
  251. loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
  252. if (!count)
  253. return 0;
  254. if (index == VFIO_PCI_CONFIG_REGION_INDEX)
  255. return virtiovf_pci_write_config(core_vdev, buf, count, ppos);
  256. if (index == VFIO_PCI_BAR0_REGION_INDEX)
  257. return virtiovf_pci_bar0_rw(virtvdev, pos, (char __user *)buf, count, false);
  258. return vfio_pci_core_write(core_vdev, buf, count, ppos);
  259. }
  260. static int
  261. virtiovf_pci_ioctl_get_region_info(struct vfio_device *core_vdev,
  262. unsigned int cmd, unsigned long arg)
  263. {
  264. struct virtiovf_pci_core_device *virtvdev = container_of(
  265. core_vdev, struct virtiovf_pci_core_device, core_device.vdev);
  266. unsigned long minsz = offsetofend(struct vfio_region_info, offset);
  267. void __user *uarg = (void __user *)arg;
  268. struct vfio_region_info info = {};
  269. if (copy_from_user(&info, uarg, minsz))
  270. return -EFAULT;
  271. if (info.argsz < minsz)
  272. return -EINVAL;
  273. switch (info.index) {
  274. case VFIO_PCI_BAR0_REGION_INDEX:
  275. info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index);
  276. info.size = virtvdev->bar0_virtual_buf_size;
  277. info.flags = VFIO_REGION_INFO_FLAG_READ |
  278. VFIO_REGION_INFO_FLAG_WRITE;
  279. return copy_to_user(uarg, &info, minsz) ? -EFAULT : 0;
  280. default:
  281. return vfio_pci_core_ioctl(core_vdev, cmd, arg);
  282. }
  283. }
  284. static long
  285. virtiovf_vfio_pci_core_ioctl(struct vfio_device *core_vdev, unsigned int cmd,
  286. unsigned long arg)
  287. {
  288. switch (cmd) {
  289. case VFIO_DEVICE_GET_REGION_INFO:
  290. return virtiovf_pci_ioctl_get_region_info(core_vdev, cmd, arg);
  291. default:
  292. return vfio_pci_core_ioctl(core_vdev, cmd, arg);
  293. }
  294. }
  295. static int
  296. virtiovf_set_notify_addr(struct virtiovf_pci_core_device *virtvdev)
  297. {
  298. struct vfio_pci_core_device *core_device = &virtvdev->core_device;
  299. int ret;
  300. /*
  301. * Setup the BAR where the 'notify' exists to be used by vfio as well
  302. * This will let us mmap it only once and use it when needed.
  303. */
  304. ret = vfio_pci_core_setup_barmap(core_device,
  305. virtvdev->notify_bar);
  306. if (ret)
  307. return ret;
  308. virtvdev->notify_addr = core_device->barmap[virtvdev->notify_bar] +
  309. virtvdev->notify_offset;
  310. return 0;
  311. }
  312. static int virtiovf_pci_open_device(struct vfio_device *core_vdev)
  313. {
  314. struct virtiovf_pci_core_device *virtvdev = container_of(
  315. core_vdev, struct virtiovf_pci_core_device, core_device.vdev);
  316. struct vfio_pci_core_device *vdev = &virtvdev->core_device;
  317. int ret;
  318. ret = vfio_pci_core_enable(vdev);
  319. if (ret)
  320. return ret;
  321. if (virtvdev->bar0_virtual_buf) {
  322. /*
  323. * Upon close_device() the vfio_pci_core_disable() is called
  324. * and will close all the previous mmaps, so it seems that the
  325. * valid life cycle for the 'notify' addr is per open/close.
  326. */
  327. ret = virtiovf_set_notify_addr(virtvdev);
  328. if (ret) {
  329. vfio_pci_core_disable(vdev);
  330. return ret;
  331. }
  332. }
  333. vfio_pci_core_finish_enable(vdev);
  334. return 0;
  335. }
  336. static int virtiovf_get_device_config_size(unsigned short device)
  337. {
  338. /* Network card */
  339. return offsetofend(struct virtio_net_config, status);
  340. }
  341. static int virtiovf_read_notify_info(struct virtiovf_pci_core_device *virtvdev)
  342. {
  343. u64 offset;
  344. int ret;
  345. u8 bar;
  346. ret = virtio_pci_admin_legacy_io_notify_info(virtvdev->core_device.pdev,
  347. VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_MEM,
  348. &bar, &offset);
  349. if (ret)
  350. return ret;
  351. virtvdev->notify_bar = bar;
  352. virtvdev->notify_offset = offset;
  353. return 0;
  354. }
  355. static int virtiovf_pci_init_device(struct vfio_device *core_vdev)
  356. {
  357. struct virtiovf_pci_core_device *virtvdev = container_of(
  358. core_vdev, struct virtiovf_pci_core_device, core_device.vdev);
  359. struct pci_dev *pdev;
  360. int ret;
  361. ret = vfio_pci_core_init_dev(core_vdev);
  362. if (ret)
  363. return ret;
  364. pdev = virtvdev->core_device.pdev;
  365. ret = virtiovf_read_notify_info(virtvdev);
  366. if (ret)
  367. return ret;
  368. virtvdev->bar0_virtual_buf_size = VIRTIO_PCI_CONFIG_OFF(true) +
  369. virtiovf_get_device_config_size(pdev->device);
  370. BUILD_BUG_ON(!is_power_of_2(virtvdev->bar0_virtual_buf_size));
  371. virtvdev->bar0_virtual_buf = kzalloc(virtvdev->bar0_virtual_buf_size,
  372. GFP_KERNEL);
  373. if (!virtvdev->bar0_virtual_buf)
  374. return -ENOMEM;
  375. mutex_init(&virtvdev->bar_mutex);
  376. return 0;
  377. }
  378. static void virtiovf_pci_core_release_dev(struct vfio_device *core_vdev)
  379. {
  380. struct virtiovf_pci_core_device *virtvdev = container_of(
  381. core_vdev, struct virtiovf_pci_core_device, core_device.vdev);
  382. kfree(virtvdev->bar0_virtual_buf);
  383. vfio_pci_core_release_dev(core_vdev);
  384. }
  385. static const struct vfio_device_ops virtiovf_vfio_pci_tran_ops = {
  386. .name = "virtio-vfio-pci-trans",
  387. .init = virtiovf_pci_init_device,
  388. .release = virtiovf_pci_core_release_dev,
  389. .open_device = virtiovf_pci_open_device,
  390. .close_device = vfio_pci_core_close_device,
  391. .ioctl = virtiovf_vfio_pci_core_ioctl,
  392. .device_feature = vfio_pci_core_ioctl_feature,
  393. .read = virtiovf_pci_core_read,
  394. .write = virtiovf_pci_core_write,
  395. .mmap = vfio_pci_core_mmap,
  396. .request = vfio_pci_core_request,
  397. .match = vfio_pci_core_match,
  398. .bind_iommufd = vfio_iommufd_physical_bind,
  399. .unbind_iommufd = vfio_iommufd_physical_unbind,
  400. .attach_ioas = vfio_iommufd_physical_attach_ioas,
  401. .detach_ioas = vfio_iommufd_physical_detach_ioas,
  402. };
  403. static const struct vfio_device_ops virtiovf_vfio_pci_ops = {
  404. .name = "virtio-vfio-pci",
  405. .init = vfio_pci_core_init_dev,
  406. .release = vfio_pci_core_release_dev,
  407. .open_device = virtiovf_pci_open_device,
  408. .close_device = vfio_pci_core_close_device,
  409. .ioctl = vfio_pci_core_ioctl,
  410. .device_feature = vfio_pci_core_ioctl_feature,
  411. .read = vfio_pci_core_read,
  412. .write = vfio_pci_core_write,
  413. .mmap = vfio_pci_core_mmap,
  414. .request = vfio_pci_core_request,
  415. .match = vfio_pci_core_match,
  416. .bind_iommufd = vfio_iommufd_physical_bind,
  417. .unbind_iommufd = vfio_iommufd_physical_unbind,
  418. .attach_ioas = vfio_iommufd_physical_attach_ioas,
  419. .detach_ioas = vfio_iommufd_physical_detach_ioas,
  420. };
  421. static bool virtiovf_bar0_exists(struct pci_dev *pdev)
  422. {
  423. struct resource *res = pdev->resource;
  424. return res->flags;
  425. }
  426. static int virtiovf_pci_probe(struct pci_dev *pdev,
  427. const struct pci_device_id *id)
  428. {
  429. const struct vfio_device_ops *ops = &virtiovf_vfio_pci_ops;
  430. struct virtiovf_pci_core_device *virtvdev;
  431. int ret;
  432. if (pdev->is_virtfn && virtio_pci_admin_has_legacy_io(pdev) &&
  433. !virtiovf_bar0_exists(pdev))
  434. ops = &virtiovf_vfio_pci_tran_ops;
  435. virtvdev = vfio_alloc_device(virtiovf_pci_core_device, core_device.vdev,
  436. &pdev->dev, ops);
  437. if (IS_ERR(virtvdev))
  438. return PTR_ERR(virtvdev);
  439. dev_set_drvdata(&pdev->dev, &virtvdev->core_device);
  440. ret = vfio_pci_core_register_device(&virtvdev->core_device);
  441. if (ret)
  442. goto out;
  443. return 0;
  444. out:
  445. vfio_put_device(&virtvdev->core_device.vdev);
  446. return ret;
  447. }
  448. static void virtiovf_pci_remove(struct pci_dev *pdev)
  449. {
  450. struct virtiovf_pci_core_device *virtvdev = dev_get_drvdata(&pdev->dev);
  451. vfio_pci_core_unregister_device(&virtvdev->core_device);
  452. vfio_put_device(&virtvdev->core_device.vdev);
  453. }
  454. static const struct pci_device_id virtiovf_pci_table[] = {
  455. /* Only virtio-net is supported/tested so far */
  456. { PCI_DRIVER_OVERRIDE_DEVICE_VFIO(PCI_VENDOR_ID_REDHAT_QUMRANET, 0x1041) },
  457. {}
  458. };
  459. MODULE_DEVICE_TABLE(pci, virtiovf_pci_table);
  460. static void virtiovf_pci_aer_reset_done(struct pci_dev *pdev)
  461. {
  462. struct virtiovf_pci_core_device *virtvdev = dev_get_drvdata(&pdev->dev);
  463. virtvdev->pci_cmd = 0;
  464. }
  465. static const struct pci_error_handlers virtiovf_err_handlers = {
  466. .reset_done = virtiovf_pci_aer_reset_done,
  467. .error_detected = vfio_pci_core_aer_err_detected,
  468. };
  469. static struct pci_driver virtiovf_pci_driver = {
  470. .name = KBUILD_MODNAME,
  471. .id_table = virtiovf_pci_table,
  472. .probe = virtiovf_pci_probe,
  473. .remove = virtiovf_pci_remove,
  474. .err_handler = &virtiovf_err_handlers,
  475. .driver_managed_dma = true,
  476. };
  477. module_pci_driver(virtiovf_pci_driver);
  478. MODULE_LICENSE("GPL");
  479. MODULE_AUTHOR("Yishai Hadas <yishaih@nvidia.com>");
  480. MODULE_DESCRIPTION(
  481. "VIRTIO VFIO PCI - User Level meta-driver for VIRTIO NET devices");