ili922x.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * (C) Copyright 2008
  4. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  5. *
  6. * This driver implements a lcd device for the ILITEK 922x display
  7. * controller. The interface to the display is SPI and the display's
  8. * memory is cyclically updated over the RGB interface.
  9. */
  10. #include <linux/fb.h>
  11. #include <linux/delay.h>
  12. #include <linux/errno.h>
  13. #include <linux/init.h>
  14. #include <linux/kernel.h>
  15. #include <linux/lcd.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/slab.h>
  19. #include <linux/spi/spi.h>
  20. #include <linux/string.h>
  21. /* Register offset, see manual section 8.2 */
  22. #define REG_START_OSCILLATION 0x00
  23. #define REG_DRIVER_CODE_READ 0x00
  24. #define REG_DRIVER_OUTPUT_CONTROL 0x01
  25. #define REG_LCD_AC_DRIVEING_CONTROL 0x02
  26. #define REG_ENTRY_MODE 0x03
  27. #define REG_COMPARE_1 0x04
  28. #define REG_COMPARE_2 0x05
  29. #define REG_DISPLAY_CONTROL_1 0x07
  30. #define REG_DISPLAY_CONTROL_2 0x08
  31. #define REG_DISPLAY_CONTROL_3 0x09
  32. #define REG_FRAME_CYCLE_CONTROL 0x0B
  33. #define REG_EXT_INTF_CONTROL 0x0C
  34. #define REG_POWER_CONTROL_1 0x10
  35. #define REG_POWER_CONTROL_2 0x11
  36. #define REG_POWER_CONTROL_3 0x12
  37. #define REG_POWER_CONTROL_4 0x13
  38. #define REG_RAM_ADDRESS_SET 0x21
  39. #define REG_WRITE_DATA_TO_GRAM 0x22
  40. #define REG_RAM_WRITE_MASK1 0x23
  41. #define REG_RAM_WRITE_MASK2 0x24
  42. #define REG_GAMMA_CONTROL_1 0x30
  43. #define REG_GAMMA_CONTROL_2 0x31
  44. #define REG_GAMMA_CONTROL_3 0x32
  45. #define REG_GAMMA_CONTROL_4 0x33
  46. #define REG_GAMMA_CONTROL_5 0x34
  47. #define REG_GAMMA_CONTROL_6 0x35
  48. #define REG_GAMMA_CONTROL_7 0x36
  49. #define REG_GAMMA_CONTROL_8 0x37
  50. #define REG_GAMMA_CONTROL_9 0x38
  51. #define REG_GAMMA_CONTROL_10 0x39
  52. #define REG_GATE_SCAN_CONTROL 0x40
  53. #define REG_VERT_SCROLL_CONTROL 0x41
  54. #define REG_FIRST_SCREEN_DRIVE_POS 0x42
  55. #define REG_SECOND_SCREEN_DRIVE_POS 0x43
  56. #define REG_RAM_ADDR_POS_H 0x44
  57. #define REG_RAM_ADDR_POS_V 0x45
  58. #define REG_OSCILLATOR_CONTROL 0x4F
  59. #define REG_GPIO 0x60
  60. #define REG_OTP_VCM_PROGRAMMING 0x61
  61. #define REG_OTP_VCM_STATUS_ENABLE 0x62
  62. #define REG_OTP_PROGRAMMING_ID_KEY 0x65
  63. /*
  64. * maximum frequency for register access
  65. * (not for the GRAM access)
  66. */
  67. #define ILITEK_MAX_FREQ_REG 4000000
  68. /*
  69. * Device ID as found in the datasheet (supports 9221 and 9222)
  70. */
  71. #define ILITEK_DEVICE_ID 0x9220
  72. #define ILITEK_DEVICE_ID_MASK 0xFFF0
  73. /* Last two bits in the START BYTE */
  74. #define START_RS_INDEX 0
  75. #define START_RS_REG 1
  76. #define START_RW_WRITE 0
  77. #define START_RW_READ 1
  78. /*
  79. * START_BYTE(id, rs, rw)
  80. *
  81. * Set the start byte according to the required operation.
  82. * The start byte is defined as:
  83. * ----------------------------------
  84. * | 0 | 1 | 1 | 1 | 0 | ID | RS | RW |
  85. * ----------------------------------
  86. * @id: display's id as set by the manufacturer
  87. * @rs: operation type bit, one of:
  88. * - START_RS_INDEX set the index register
  89. * - START_RS_REG write/read registers/GRAM
  90. * @rw: read/write operation
  91. * - START_RW_WRITE write
  92. * - START_RW_READ read
  93. */
  94. #define START_BYTE(id, rs, rw) \
  95. (0x70 | (((id) & 0x01) << 2) | (((rs) & 0x01) << 1) | ((rw) & 0x01))
  96. /*
  97. * CHECK_FREQ_REG(spi_device s, spi_transfer x) - Check the frequency
  98. * for the SPI transfer. According to the datasheet, the controller
  99. * accept higher frequency for the GRAM transfer, but it requires
  100. * lower frequency when the registers are read/written.
  101. * The macro sets the frequency in the spi_transfer structure if
  102. * the frequency exceeds the maximum value.
  103. * @s: pointer to an SPI device
  104. * @x: pointer to the read/write buffer pair
  105. */
  106. #define CHECK_FREQ_REG(s, x) \
  107. do { \
  108. if (s->max_speed_hz > ILITEK_MAX_FREQ_REG) \
  109. ((struct spi_transfer *)x)->speed_hz = \
  110. ILITEK_MAX_FREQ_REG; \
  111. } while (0)
  112. #define CMD_BUFSIZE 16
  113. #define POWER_IS_ON(pwr) ((pwr) <= FB_BLANK_NORMAL)
  114. #define set_tx_byte(b) (tx_invert ? ~(b) : b)
  115. /*
  116. * ili922x_id - id as set by manufacturer
  117. */
  118. static int ili922x_id = 1;
  119. module_param(ili922x_id, int, 0);
  120. static int tx_invert;
  121. module_param(tx_invert, int, 0);
  122. /*
  123. * driver's private structure
  124. */
  125. struct ili922x {
  126. struct spi_device *spi;
  127. struct lcd_device *ld;
  128. int power;
  129. };
  130. /**
  131. * ili922x_read_status - read status register from display
  132. * @spi: spi device
  133. * @rs: output value
  134. */
  135. static int ili922x_read_status(struct spi_device *spi, u16 *rs)
  136. {
  137. struct spi_message msg;
  138. struct spi_transfer xfer;
  139. unsigned char tbuf[CMD_BUFSIZE];
  140. unsigned char rbuf[CMD_BUFSIZE];
  141. int ret, i;
  142. memset(&xfer, 0, sizeof(struct spi_transfer));
  143. spi_message_init(&msg);
  144. xfer.tx_buf = tbuf;
  145. xfer.rx_buf = rbuf;
  146. xfer.cs_change = 1;
  147. CHECK_FREQ_REG(spi, &xfer);
  148. tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
  149. START_RW_READ));
  150. /*
  151. * we need 4-byte xfer here due to invalid dummy byte
  152. * received after start byte
  153. */
  154. for (i = 1; i < 4; i++)
  155. tbuf[i] = set_tx_byte(0); /* dummy */
  156. xfer.bits_per_word = 8;
  157. xfer.len = 4;
  158. spi_message_add_tail(&xfer, &msg);
  159. ret = spi_sync(spi, &msg);
  160. if (ret < 0) {
  161. dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret);
  162. return ret;
  163. }
  164. *rs = (rbuf[2] << 8) + rbuf[3];
  165. return 0;
  166. }
  167. /**
  168. * ili922x_read - read register from display
  169. * @spi: spi device
  170. * @reg: offset of the register to be read
  171. * @rx: output value
  172. */
  173. static int ili922x_read(struct spi_device *spi, u8 reg, u16 *rx)
  174. {
  175. struct spi_message msg;
  176. struct spi_transfer xfer_regindex, xfer_regvalue;
  177. unsigned char tbuf[CMD_BUFSIZE];
  178. unsigned char rbuf[CMD_BUFSIZE];
  179. int ret, len = 0, send_bytes;
  180. memset(&xfer_regindex, 0, sizeof(struct spi_transfer));
  181. memset(&xfer_regvalue, 0, sizeof(struct spi_transfer));
  182. spi_message_init(&msg);
  183. xfer_regindex.tx_buf = tbuf;
  184. xfer_regindex.rx_buf = rbuf;
  185. xfer_regindex.cs_change = 1;
  186. CHECK_FREQ_REG(spi, &xfer_regindex);
  187. tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
  188. START_RW_WRITE));
  189. tbuf[1] = set_tx_byte(0);
  190. tbuf[2] = set_tx_byte(reg);
  191. xfer_regindex.bits_per_word = 8;
  192. len = xfer_regindex.len = 3;
  193. spi_message_add_tail(&xfer_regindex, &msg);
  194. send_bytes = len;
  195. tbuf[len++] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
  196. START_RW_READ));
  197. tbuf[len++] = set_tx_byte(0);
  198. tbuf[len] = set_tx_byte(0);
  199. xfer_regvalue.cs_change = 1;
  200. xfer_regvalue.len = 3;
  201. xfer_regvalue.tx_buf = &tbuf[send_bytes];
  202. xfer_regvalue.rx_buf = &rbuf[send_bytes];
  203. CHECK_FREQ_REG(spi, &xfer_regvalue);
  204. spi_message_add_tail(&xfer_regvalue, &msg);
  205. ret = spi_sync(spi, &msg);
  206. if (ret < 0) {
  207. dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret);
  208. return ret;
  209. }
  210. *rx = (rbuf[1 + send_bytes] << 8) + rbuf[2 + send_bytes];
  211. return 0;
  212. }
  213. /**
  214. * ili922x_write - write a controller register
  215. * @spi: struct spi_device *
  216. * @reg: offset of the register to be written
  217. * @value: value to be written
  218. */
  219. static int ili922x_write(struct spi_device *spi, u8 reg, u16 value)
  220. {
  221. struct spi_message msg;
  222. struct spi_transfer xfer_regindex, xfer_regvalue;
  223. unsigned char tbuf[CMD_BUFSIZE];
  224. unsigned char rbuf[CMD_BUFSIZE];
  225. int ret;
  226. memset(&xfer_regindex, 0, sizeof(struct spi_transfer));
  227. memset(&xfer_regvalue, 0, sizeof(struct spi_transfer));
  228. spi_message_init(&msg);
  229. xfer_regindex.tx_buf = tbuf;
  230. xfer_regindex.rx_buf = rbuf;
  231. xfer_regindex.cs_change = 1;
  232. CHECK_FREQ_REG(spi, &xfer_regindex);
  233. tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
  234. START_RW_WRITE));
  235. tbuf[1] = set_tx_byte(0);
  236. tbuf[2] = set_tx_byte(reg);
  237. xfer_regindex.bits_per_word = 8;
  238. xfer_regindex.len = 3;
  239. spi_message_add_tail(&xfer_regindex, &msg);
  240. ret = spi_sync(spi, &msg);
  241. if (ret < 0) {
  242. dev_err(&spi->dev, "Error sending SPI message 0x%x", ret);
  243. return ret;
  244. }
  245. spi_message_init(&msg);
  246. tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
  247. START_RW_WRITE));
  248. tbuf[1] = set_tx_byte((value & 0xFF00) >> 8);
  249. tbuf[2] = set_tx_byte(value & 0x00FF);
  250. xfer_regvalue.cs_change = 1;
  251. xfer_regvalue.len = 3;
  252. xfer_regvalue.tx_buf = tbuf;
  253. xfer_regvalue.rx_buf = rbuf;
  254. CHECK_FREQ_REG(spi, &xfer_regvalue);
  255. spi_message_add_tail(&xfer_regvalue, &msg);
  256. ret = spi_sync(spi, &msg);
  257. if (ret < 0) {
  258. dev_err(&spi->dev, "Error sending SPI message 0x%x", ret);
  259. return ret;
  260. }
  261. return 0;
  262. }
  263. #ifdef DEBUG
  264. /**
  265. * ili922x_reg_dump - dump all registers
  266. *
  267. * @spi: pointer to an SPI device
  268. */
  269. static void ili922x_reg_dump(struct spi_device *spi)
  270. {
  271. u8 reg;
  272. u16 rx;
  273. dev_dbg(&spi->dev, "ILI922x configuration registers:\n");
  274. for (reg = REG_START_OSCILLATION;
  275. reg <= REG_OTP_PROGRAMMING_ID_KEY; reg++) {
  276. ili922x_read(spi, reg, &rx);
  277. dev_dbg(&spi->dev, "reg @ 0x%02X: 0x%04X\n", reg, rx);
  278. }
  279. }
  280. #else
  281. static inline void ili922x_reg_dump(struct spi_device *spi) {}
  282. #endif
  283. /**
  284. * set_write_to_gram_reg - initialize the display to write the GRAM
  285. * @spi: spi device
  286. */
  287. static void set_write_to_gram_reg(struct spi_device *spi)
  288. {
  289. struct spi_message msg;
  290. struct spi_transfer xfer;
  291. unsigned char tbuf[CMD_BUFSIZE];
  292. memset(&xfer, 0, sizeof(struct spi_transfer));
  293. spi_message_init(&msg);
  294. xfer.tx_buf = tbuf;
  295. xfer.rx_buf = NULL;
  296. xfer.cs_change = 1;
  297. tbuf[0] = START_BYTE(ili922x_id, START_RS_INDEX, START_RW_WRITE);
  298. tbuf[1] = 0;
  299. tbuf[2] = REG_WRITE_DATA_TO_GRAM;
  300. xfer.bits_per_word = 8;
  301. xfer.len = 3;
  302. spi_message_add_tail(&xfer, &msg);
  303. spi_sync(spi, &msg);
  304. }
  305. /**
  306. * ili922x_poweron - turn the display on
  307. * @spi: spi device
  308. *
  309. * The sequence to turn on the display is taken from
  310. * the datasheet and/or the example code provided by the
  311. * manufacturer.
  312. */
  313. static int ili922x_poweron(struct spi_device *spi)
  314. {
  315. int ret;
  316. /* Power on */
  317. ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000);
  318. usleep_range(10000, 10500);
  319. ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
  320. ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000);
  321. msleep(40);
  322. ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000);
  323. msleep(40);
  324. /* register 0x56 is not documented in the datasheet */
  325. ret += ili922x_write(spi, 0x56, 0x080F);
  326. ret += ili922x_write(spi, REG_POWER_CONTROL_1, 0x4240);
  327. usleep_range(10000, 10500);
  328. ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
  329. ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0014);
  330. msleep(40);
  331. ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x1319);
  332. msleep(40);
  333. return ret;
  334. }
  335. /**
  336. * ili922x_poweroff - turn the display off
  337. * @spi: spi device
  338. */
  339. static int ili922x_poweroff(struct spi_device *spi)
  340. {
  341. int ret;
  342. /* Power off */
  343. ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000);
  344. usleep_range(10000, 10500);
  345. ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
  346. ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000);
  347. msleep(40);
  348. ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000);
  349. msleep(40);
  350. return ret;
  351. }
  352. /**
  353. * ili922x_display_init - initialize the display by setting
  354. * the configuration registers
  355. * @spi: spi device
  356. */
  357. static void ili922x_display_init(struct spi_device *spi)
  358. {
  359. ili922x_write(spi, REG_START_OSCILLATION, 1);
  360. usleep_range(10000, 10500);
  361. ili922x_write(spi, REG_DRIVER_OUTPUT_CONTROL, 0x691B);
  362. ili922x_write(spi, REG_LCD_AC_DRIVEING_CONTROL, 0x0700);
  363. ili922x_write(spi, REG_ENTRY_MODE, 0x1030);
  364. ili922x_write(spi, REG_COMPARE_1, 0x0000);
  365. ili922x_write(spi, REG_COMPARE_2, 0x0000);
  366. ili922x_write(spi, REG_DISPLAY_CONTROL_1, 0x0037);
  367. ili922x_write(spi, REG_DISPLAY_CONTROL_2, 0x0202);
  368. ili922x_write(spi, REG_DISPLAY_CONTROL_3, 0x0000);
  369. ili922x_write(spi, REG_FRAME_CYCLE_CONTROL, 0x0000);
  370. /* Set RGB interface */
  371. ili922x_write(spi, REG_EXT_INTF_CONTROL, 0x0110);
  372. ili922x_poweron(spi);
  373. ili922x_write(spi, REG_GAMMA_CONTROL_1, 0x0302);
  374. ili922x_write(spi, REG_GAMMA_CONTROL_2, 0x0407);
  375. ili922x_write(spi, REG_GAMMA_CONTROL_3, 0x0304);
  376. ili922x_write(spi, REG_GAMMA_CONTROL_4, 0x0203);
  377. ili922x_write(spi, REG_GAMMA_CONTROL_5, 0x0706);
  378. ili922x_write(spi, REG_GAMMA_CONTROL_6, 0x0407);
  379. ili922x_write(spi, REG_GAMMA_CONTROL_7, 0x0706);
  380. ili922x_write(spi, REG_GAMMA_CONTROL_8, 0x0000);
  381. ili922x_write(spi, REG_GAMMA_CONTROL_9, 0x0C06);
  382. ili922x_write(spi, REG_GAMMA_CONTROL_10, 0x0F00);
  383. ili922x_write(spi, REG_RAM_ADDRESS_SET, 0x0000);
  384. ili922x_write(spi, REG_GATE_SCAN_CONTROL, 0x0000);
  385. ili922x_write(spi, REG_VERT_SCROLL_CONTROL, 0x0000);
  386. ili922x_write(spi, REG_FIRST_SCREEN_DRIVE_POS, 0xDB00);
  387. ili922x_write(spi, REG_SECOND_SCREEN_DRIVE_POS, 0xDB00);
  388. ili922x_write(spi, REG_RAM_ADDR_POS_H, 0xAF00);
  389. ili922x_write(spi, REG_RAM_ADDR_POS_V, 0xDB00);
  390. ili922x_reg_dump(spi);
  391. set_write_to_gram_reg(spi);
  392. }
  393. static int ili922x_lcd_power(struct ili922x *lcd, int power)
  394. {
  395. int ret = 0;
  396. if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->power))
  397. ret = ili922x_poweron(lcd->spi);
  398. else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->power))
  399. ret = ili922x_poweroff(lcd->spi);
  400. if (!ret)
  401. lcd->power = power;
  402. return ret;
  403. }
  404. static int ili922x_set_power(struct lcd_device *ld, int power)
  405. {
  406. struct ili922x *ili = lcd_get_data(ld);
  407. return ili922x_lcd_power(ili, power);
  408. }
  409. static int ili922x_get_power(struct lcd_device *ld)
  410. {
  411. struct ili922x *ili = lcd_get_data(ld);
  412. return ili->power;
  413. }
  414. static const struct lcd_ops ili922x_ops = {
  415. .get_power = ili922x_get_power,
  416. .set_power = ili922x_set_power,
  417. };
  418. static int ili922x_probe(struct spi_device *spi)
  419. {
  420. struct ili922x *ili;
  421. struct lcd_device *lcd;
  422. int ret;
  423. u16 reg = 0;
  424. ili = devm_kzalloc(&spi->dev, sizeof(*ili), GFP_KERNEL);
  425. if (!ili)
  426. return -ENOMEM;
  427. ili->spi = spi;
  428. spi_set_drvdata(spi, ili);
  429. /* check if the device is connected */
  430. ret = ili922x_read(spi, REG_DRIVER_CODE_READ, &reg);
  431. if (ret || ((reg & ILITEK_DEVICE_ID_MASK) != ILITEK_DEVICE_ID)) {
  432. dev_err(&spi->dev,
  433. "no LCD found: Chip ID 0x%x, ret %d\n",
  434. reg, ret);
  435. return -ENODEV;
  436. }
  437. dev_info(&spi->dev, "ILI%x found, SPI freq %d, mode %d\n",
  438. reg, spi->max_speed_hz, spi->mode);
  439. ret = ili922x_read_status(spi, &reg);
  440. if (ret) {
  441. dev_err(&spi->dev, "reading RS failed...\n");
  442. return ret;
  443. }
  444. dev_dbg(&spi->dev, "status: 0x%x\n", reg);
  445. ili922x_display_init(spi);
  446. ili->power = FB_BLANK_POWERDOWN;
  447. lcd = devm_lcd_device_register(&spi->dev, "ili922xlcd", &spi->dev, ili,
  448. &ili922x_ops);
  449. if (IS_ERR(lcd)) {
  450. dev_err(&spi->dev, "cannot register LCD\n");
  451. return PTR_ERR(lcd);
  452. }
  453. ili->ld = lcd;
  454. spi_set_drvdata(spi, ili);
  455. ili922x_lcd_power(ili, FB_BLANK_UNBLANK);
  456. return 0;
  457. }
  458. static void ili922x_remove(struct spi_device *spi)
  459. {
  460. ili922x_poweroff(spi);
  461. }
  462. static struct spi_driver ili922x_driver = {
  463. .driver = {
  464. .name = "ili922x",
  465. },
  466. .probe = ili922x_probe,
  467. .remove = ili922x_remove,
  468. };
  469. module_spi_driver(ili922x_driver);
  470. MODULE_AUTHOR("Stefano Babic <sbabic@denx.de>");
  471. MODULE_DESCRIPTION("ILI9221/9222 LCD driver");
  472. MODULE_LICENSE("GPL");
  473. MODULE_PARM_DESC(ili922x_id, "set controller identifier (default=1)");
  474. MODULE_PARM_DESC(tx_invert, "invert bytes before sending");