motu-protocol-v2.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * motu-protocol-v2.c - a part of driver for MOTU FireWire series
  4. *
  5. * Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp>
  6. */
  7. #include "motu.h"
  8. #define V2_CLOCK_STATUS_OFFSET 0x0b14
  9. #define V2_CLOCK_RATE_MASK 0x00000038
  10. #define V2_CLOCK_RATE_SHIFT 3
  11. #define V2_CLOCK_SRC_MASK 0x00000007
  12. #define V2_CLOCK_SRC_SHIFT 0
  13. #define V2_CLOCK_SRC_AESEBU_ON_XLR 0x07 // In Traveler.
  14. #define V2_CLOCK_SRC_ADAT_ON_DSUB 0x05
  15. #define V2_CLOCK_SRC_WORD_ON_BNC 0x04
  16. #define V2_CLOCK_SRC_SPH 0x03
  17. #define V2_CLOCK_SRC_SPDIF 0x02 // on either coaxial or optical. AES/EBU in 896HD.
  18. #define V2_CLOCK_SRC_ADAT_ON_OPT 0x01
  19. #define V2_CLOCK_SRC_INTERNAL 0x00
  20. #define V2_CLOCK_FETCH_ENABLE 0x02000000
  21. #define V2_CLOCK_MODEL_SPECIFIC 0x04000000
  22. #define V2_IN_OUT_CONF_OFFSET 0x0c04
  23. #define V2_OPT_OUT_IFACE_MASK 0x00000c00
  24. #define V2_OPT_OUT_IFACE_SHIFT 10
  25. #define V2_OPT_IN_IFACE_MASK 0x00000300
  26. #define V2_OPT_IN_IFACE_SHIFT 8
  27. #define V2_OPT_IFACE_MODE_NONE 0
  28. #define V2_OPT_IFACE_MODE_ADAT 1
  29. #define V2_OPT_IFACE_MODE_SPDIF 2
  30. static int get_clock_rate(u32 data, unsigned int *rate)
  31. {
  32. unsigned int index = (data & V2_CLOCK_RATE_MASK) >> V2_CLOCK_RATE_SHIFT;
  33. if (index >= ARRAY_SIZE(snd_motu_clock_rates))
  34. return -EIO;
  35. *rate = snd_motu_clock_rates[index];
  36. return 0;
  37. }
  38. int snd_motu_protocol_v2_get_clock_rate(struct snd_motu *motu,
  39. unsigned int *rate)
  40. {
  41. __be32 reg;
  42. int err;
  43. err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, &reg,
  44. sizeof(reg));
  45. if (err < 0)
  46. return err;
  47. return get_clock_rate(be32_to_cpu(reg), rate);
  48. }
  49. int snd_motu_protocol_v2_set_clock_rate(struct snd_motu *motu,
  50. unsigned int rate)
  51. {
  52. __be32 reg;
  53. u32 data;
  54. int i;
  55. int err;
  56. for (i = 0; i < ARRAY_SIZE(snd_motu_clock_rates); ++i) {
  57. if (snd_motu_clock_rates[i] == rate)
  58. break;
  59. }
  60. if (i == ARRAY_SIZE(snd_motu_clock_rates))
  61. return -EINVAL;
  62. err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, &reg,
  63. sizeof(reg));
  64. if (err < 0)
  65. return err;
  66. data = be32_to_cpu(reg);
  67. data &= ~V2_CLOCK_RATE_MASK;
  68. data |= i << V2_CLOCK_RATE_SHIFT;
  69. reg = cpu_to_be32(data);
  70. return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, &reg,
  71. sizeof(reg));
  72. }
  73. static int get_clock_source(struct snd_motu *motu, u32 data,
  74. enum snd_motu_clock_source *src)
  75. {
  76. switch (data & V2_CLOCK_SRC_MASK) {
  77. case V2_CLOCK_SRC_INTERNAL:
  78. *src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
  79. break;
  80. case V2_CLOCK_SRC_ADAT_ON_OPT:
  81. *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT;
  82. break;
  83. case V2_CLOCK_SRC_SPDIF:
  84. {
  85. bool support_iec60958_on_opt = (motu->spec == &snd_motu_spec_828mk2 ||
  86. motu->spec == &snd_motu_spec_traveler);
  87. if (motu->spec == &snd_motu_spec_896hd) {
  88. *src = SND_MOTU_CLOCK_SOURCE_AESEBU_ON_XLR;
  89. } else if (!support_iec60958_on_opt) {
  90. *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
  91. } else {
  92. __be32 reg;
  93. // To check the configuration of optical interface.
  94. int err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, &reg,
  95. sizeof(reg));
  96. if (err < 0)
  97. return err;
  98. if (((data & V2_OPT_IN_IFACE_MASK) >> V2_OPT_IN_IFACE_SHIFT) ==
  99. V2_OPT_IFACE_MODE_SPDIF)
  100. *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT;
  101. else
  102. *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
  103. }
  104. break;
  105. }
  106. case V2_CLOCK_SRC_SPH:
  107. *src = SND_MOTU_CLOCK_SOURCE_SPH;
  108. break;
  109. case V2_CLOCK_SRC_WORD_ON_BNC:
  110. *src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
  111. break;
  112. case V2_CLOCK_SRC_ADAT_ON_DSUB:
  113. *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB;
  114. break;
  115. case V2_CLOCK_SRC_AESEBU_ON_XLR:
  116. // For Traveler.
  117. *src = SND_MOTU_CLOCK_SOURCE_AESEBU_ON_XLR;
  118. break;
  119. default:
  120. *src = SND_MOTU_CLOCK_SOURCE_UNKNOWN;
  121. break;
  122. }
  123. return 0;
  124. }
  125. int snd_motu_protocol_v2_get_clock_source(struct snd_motu *motu,
  126. enum snd_motu_clock_source *src)
  127. {
  128. __be32 reg;
  129. int err;
  130. err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, &reg,
  131. sizeof(reg));
  132. if (err < 0)
  133. return err;
  134. return get_clock_source(motu, be32_to_cpu(reg), src);
  135. }
  136. // Expected for Traveler, which implements Altera Cyclone EP1C3.
  137. static int switch_fetching_mode_cyclone(struct snd_motu *motu, u32 *data,
  138. bool enable)
  139. {
  140. *data |= V2_CLOCK_MODEL_SPECIFIC;
  141. return 0;
  142. }
  143. // For UltraLite and 8pre, which implements Xilinx Spartan XC3S200.
  144. static int switch_fetching_mode_spartan(struct snd_motu *motu, u32 *data,
  145. bool enable)
  146. {
  147. unsigned int rate;
  148. enum snd_motu_clock_source src;
  149. int err;
  150. err = get_clock_source(motu, *data, &src);
  151. if (err < 0)
  152. return err;
  153. err = get_clock_rate(*data, &rate);
  154. if (err < 0)
  155. return err;
  156. if (src == SND_MOTU_CLOCK_SOURCE_SPH && rate > 48000)
  157. *data |= V2_CLOCK_MODEL_SPECIFIC;
  158. return 0;
  159. }
  160. int snd_motu_protocol_v2_switch_fetching_mode(struct snd_motu *motu,
  161. bool enable)
  162. {
  163. if (motu->spec == &snd_motu_spec_828mk2) {
  164. // 828mkII implements Altera ACEX 1K EP1K30. Nothing to do.
  165. return 0;
  166. } else if (motu->spec == &snd_motu_spec_896hd) {
  167. // 896HD implements Altera Cyclone EP1C3 but nothing to do.
  168. return 0;
  169. } else {
  170. __be32 reg;
  171. u32 data;
  172. int err;
  173. err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET,
  174. &reg, sizeof(reg));
  175. if (err < 0)
  176. return err;
  177. data = be32_to_cpu(reg);
  178. data &= ~(V2_CLOCK_FETCH_ENABLE | V2_CLOCK_MODEL_SPECIFIC);
  179. if (enable)
  180. data |= V2_CLOCK_FETCH_ENABLE;
  181. if (motu->spec == &snd_motu_spec_traveler)
  182. err = switch_fetching_mode_cyclone(motu, &data, enable);
  183. else
  184. err = switch_fetching_mode_spartan(motu, &data, enable);
  185. if (err < 0)
  186. return err;
  187. reg = cpu_to_be32(data);
  188. return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET,
  189. &reg, sizeof(reg));
  190. }
  191. }
  192. int snd_motu_protocol_v2_cache_packet_formats(struct snd_motu *motu)
  193. {
  194. bool has_two_opt_ifaces = (motu->spec == &snd_motu_spec_8pre);
  195. __be32 reg;
  196. u32 data;
  197. int err;
  198. motu->tx_packet_formats.pcm_byte_offset = 10;
  199. motu->rx_packet_formats.pcm_byte_offset = 10;
  200. motu->tx_packet_formats.msg_chunks = 2;
  201. motu->rx_packet_formats.msg_chunks = 2;
  202. err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, &reg,
  203. sizeof(reg));
  204. if (err < 0)
  205. return err;
  206. data = be32_to_cpu(reg);
  207. memcpy(motu->tx_packet_formats.pcm_chunks,
  208. motu->spec->tx_fixed_pcm_chunks,
  209. sizeof(motu->tx_packet_formats.pcm_chunks));
  210. memcpy(motu->rx_packet_formats.pcm_chunks,
  211. motu->spec->rx_fixed_pcm_chunks,
  212. sizeof(motu->rx_packet_formats.pcm_chunks));
  213. if (((data & V2_OPT_IN_IFACE_MASK) >> V2_OPT_IN_IFACE_SHIFT) == V2_OPT_IFACE_MODE_ADAT) {
  214. motu->tx_packet_formats.pcm_chunks[0] += 8;
  215. if (!has_two_opt_ifaces)
  216. motu->tx_packet_formats.pcm_chunks[1] += 4;
  217. else
  218. motu->tx_packet_formats.pcm_chunks[1] += 8;
  219. }
  220. if (((data & V2_OPT_OUT_IFACE_MASK) >> V2_OPT_OUT_IFACE_SHIFT) == V2_OPT_IFACE_MODE_ADAT) {
  221. motu->rx_packet_formats.pcm_chunks[0] += 8;
  222. if (!has_two_opt_ifaces)
  223. motu->rx_packet_formats.pcm_chunks[1] += 4;
  224. else
  225. motu->rx_packet_formats.pcm_chunks[1] += 8;
  226. }
  227. return 0;
  228. }
  229. const struct snd_motu_spec snd_motu_spec_828mk2 = {
  230. .name = "828mk2",
  231. .protocol_version = SND_MOTU_PROTOCOL_V2,
  232. .flags = SND_MOTU_SPEC_RX_MIDI_2ND_Q |
  233. SND_MOTU_SPEC_TX_MIDI_2ND_Q |
  234. SND_MOTU_SPEC_REGISTER_DSP,
  235. .tx_fixed_pcm_chunks = {14, 14, 0},
  236. .rx_fixed_pcm_chunks = {14, 14, 0},
  237. };
  238. const struct snd_motu_spec snd_motu_spec_896hd = {
  239. .name = "896HD",
  240. .protocol_version = SND_MOTU_PROTOCOL_V2,
  241. .flags = SND_MOTU_SPEC_REGISTER_DSP,
  242. .tx_fixed_pcm_chunks = {14, 14, 8},
  243. .rx_fixed_pcm_chunks = {14, 14, 8},
  244. };
  245. const struct snd_motu_spec snd_motu_spec_traveler = {
  246. .name = "Traveler",
  247. .protocol_version = SND_MOTU_PROTOCOL_V2,
  248. .flags = SND_MOTU_SPEC_RX_MIDI_2ND_Q |
  249. SND_MOTU_SPEC_TX_MIDI_2ND_Q |
  250. SND_MOTU_SPEC_REGISTER_DSP,
  251. .tx_fixed_pcm_chunks = {14, 14, 8},
  252. .rx_fixed_pcm_chunks = {14, 14, 8},
  253. };
  254. const struct snd_motu_spec snd_motu_spec_ultralite = {
  255. .name = "UltraLite",
  256. .protocol_version = SND_MOTU_PROTOCOL_V2,
  257. .flags = SND_MOTU_SPEC_RX_MIDI_2ND_Q |
  258. SND_MOTU_SPEC_TX_MIDI_2ND_Q |
  259. SND_MOTU_SPEC_REGISTER_DSP,
  260. .tx_fixed_pcm_chunks = {14, 14, 0},
  261. .rx_fixed_pcm_chunks = {14, 14, 0},
  262. };
  263. const struct snd_motu_spec snd_motu_spec_8pre = {
  264. .name = "8pre",
  265. .protocol_version = SND_MOTU_PROTOCOL_V2,
  266. .flags = SND_MOTU_SPEC_RX_MIDI_2ND_Q |
  267. SND_MOTU_SPEC_TX_MIDI_2ND_Q |
  268. SND_MOTU_SPEC_REGISTER_DSP,
  269. // Two dummy chunks always in the end of data block.
  270. .tx_fixed_pcm_chunks = {10, 10, 0},
  271. .rx_fixed_pcm_chunks = {6, 6, 0},
  272. };