emufx.c 94 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  4. * James Courtier-Dutton <James@superbug.co.uk>
  5. * Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
  6. * Creative Labs, Inc.
  7. *
  8. * Routines for effect processor FX8010
  9. */
  10. #include <linux/pci.h>
  11. #include <linux/capability.h>
  12. #include <linux/delay.h>
  13. #include <linux/slab.h>
  14. #include <linux/vmalloc.h>
  15. #include <linux/init.h>
  16. #include <linux/mutex.h>
  17. #include <linux/moduleparam.h>
  18. #include <linux/nospec.h>
  19. #include <sound/core.h>
  20. #include <sound/tlv.h>
  21. #include <sound/emu10k1.h>
  22. #if 0 /* for testing purposes - digital out -> capture */
  23. #define EMU10K1_CAPTURE_DIGITAL_OUT
  24. #endif
  25. #if 0 /* for testing purposes - set S/PDIF to AC3 output */
  26. #define EMU10K1_SET_AC3_IEC958
  27. #endif
  28. #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */
  29. #define EMU10K1_CENTER_LFE_FROM_FRONT
  30. #endif
  31. static bool high_res_gpr_volume;
  32. module_param(high_res_gpr_volume, bool, 0444);
  33. MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range.");
  34. /*
  35. * Tables
  36. */
  37. // Playback channel labels; corresponds with the public FXBUS_* defines.
  38. // Unlike the tables below, this is not determined by the hardware.
  39. const char * const snd_emu10k1_fxbus[32] = {
  40. /* 0x00 */ "PCM Left",
  41. /* 0x01 */ "PCM Right",
  42. /* 0x02 */ "PCM Rear Left",
  43. /* 0x03 */ "PCM Rear Right",
  44. /* 0x04 */ "MIDI Left",
  45. /* 0x05 */ "MIDI Right",
  46. /* 0x06 */ "PCM Center",
  47. /* 0x07 */ "PCM LFE",
  48. /* 0x08 */ "PCM Front Left",
  49. /* 0x09 */ "PCM Front Right",
  50. /* 0x0a */ NULL,
  51. /* 0x0b */ NULL,
  52. /* 0x0c */ "MIDI Reverb",
  53. /* 0x0d */ "MIDI Chorus",
  54. /* 0x0e */ "PCM Side Left",
  55. /* 0x0f */ "PCM Side Right",
  56. /* 0x10 */ NULL,
  57. /* 0x11 */ NULL,
  58. /* 0x12 */ NULL,
  59. /* 0x13 */ NULL,
  60. /* 0x14 */ "Passthrough Left",
  61. /* 0x15 */ "Passthrough Right",
  62. /* 0x16 */ NULL,
  63. /* 0x17 */ NULL,
  64. /* 0x18 */ NULL,
  65. /* 0x19 */ NULL,
  66. /* 0x1a */ NULL,
  67. /* 0x1b */ NULL,
  68. /* 0x1c */ NULL,
  69. /* 0x1d */ NULL,
  70. /* 0x1e */ NULL,
  71. /* 0x1f */ NULL
  72. };
  73. // Physical inputs; corresponds with the public EXTIN_* defines.
  74. const char * const snd_emu10k1_sblive_ins[16] = {
  75. /* 0x00 */ "AC97 Left",
  76. /* 0x01 */ "AC97 Right",
  77. /* 0x02 */ "TTL IEC958 Left",
  78. /* 0x03 */ "TTL IEC958 Right",
  79. /* 0x04 */ "Zoom Video Left",
  80. /* 0x05 */ "Zoom Video Right",
  81. /* 0x06 */ "Optical IEC958 Left",
  82. /* 0x07 */ "Optical IEC958 Right",
  83. /* 0x08 */ "Line/Mic 1 Left",
  84. /* 0x09 */ "Line/Mic 1 Right",
  85. /* 0x0a */ "Coaxial IEC958 Left",
  86. /* 0x0b */ "Coaxial IEC958 Right",
  87. /* 0x0c */ "Line/Mic 2 Left",
  88. /* 0x0d */ "Line/Mic 2 Right",
  89. /* 0x0e */ NULL,
  90. /* 0x0f */ NULL
  91. };
  92. // Physical inputs; corresponds with the public A_EXTIN_* defines.
  93. const char * const snd_emu10k1_audigy_ins[16] = {
  94. /* 0x00 */ "AC97 Left",
  95. /* 0x01 */ "AC97 Right",
  96. /* 0x02 */ "Audigy CD Left",
  97. /* 0x03 */ "Audigy CD Right",
  98. /* 0x04 */ "Optical IEC958 Left",
  99. /* 0x05 */ "Optical IEC958 Right",
  100. /* 0x06 */ NULL,
  101. /* 0x07 */ NULL,
  102. /* 0x08 */ "Line/Mic 2 Left",
  103. /* 0x09 */ "Line/Mic 2 Right",
  104. /* 0x0a */ "SPDIF Left",
  105. /* 0x0b */ "SPDIF Right",
  106. /* 0x0c */ "Aux2 Left",
  107. /* 0x0d */ "Aux2 Right",
  108. /* 0x0e */ NULL,
  109. /* 0x0f */ NULL
  110. };
  111. // Physical outputs; corresponds with the public EXTOUT_* defines.
  112. const char * const snd_emu10k1_sblive_outs[32] = {
  113. /* 0x00 */ "AC97 Left",
  114. /* 0x01 */ "AC97 Right",
  115. /* 0x02 */ "Optical IEC958 Left",
  116. /* 0x03 */ "Optical IEC958 Right",
  117. /* 0x04 */ "Center",
  118. /* 0x05 */ "LFE",
  119. /* 0x06 */ "Headphone Left",
  120. /* 0x07 */ "Headphone Right",
  121. /* 0x08 */ "Surround Left",
  122. /* 0x09 */ "Surround Right",
  123. /* 0x0a */ "PCM Capture Left",
  124. /* 0x0b */ "PCM Capture Right",
  125. /* 0x0c */ "MIC Capture",
  126. /* 0x0d */ "AC97 Surround Left",
  127. /* 0x0e */ "AC97 Surround Right",
  128. /* 0x0f */ NULL,
  129. // This is actually the FXBUS2 range; SB Live! 5.1 only.
  130. /* 0x10 */ NULL,
  131. /* 0x11 */ "Analog Center",
  132. /* 0x12 */ "Analog LFE",
  133. /* 0x13 */ NULL,
  134. /* 0x14 */ NULL,
  135. /* 0x15 */ NULL,
  136. /* 0x16 */ NULL,
  137. /* 0x17 */ NULL,
  138. /* 0x18 */ NULL,
  139. /* 0x19 */ NULL,
  140. /* 0x1a */ NULL,
  141. /* 0x1b */ NULL,
  142. /* 0x1c */ NULL,
  143. /* 0x1d */ NULL,
  144. /* 0x1e */ NULL,
  145. /* 0x1f */ NULL,
  146. };
  147. // Physical outputs; corresponds with the public A_EXTOUT_* defines.
  148. const char * const snd_emu10k1_audigy_outs[32] = {
  149. /* 0x00 */ "Digital Front Left",
  150. /* 0x01 */ "Digital Front Right",
  151. /* 0x02 */ "Digital Center",
  152. /* 0x03 */ "Digital LEF",
  153. /* 0x04 */ "Headphone Left",
  154. /* 0x05 */ "Headphone Right",
  155. /* 0x06 */ "Digital Rear Left",
  156. /* 0x07 */ "Digital Rear Right",
  157. /* 0x08 */ "Front Left",
  158. /* 0x09 */ "Front Right",
  159. /* 0x0a */ "Center",
  160. /* 0x0b */ "LFE",
  161. /* 0x0c */ NULL,
  162. /* 0x0d */ NULL,
  163. /* 0x0e */ "Rear Left",
  164. /* 0x0f */ "Rear Right",
  165. /* 0x10 */ "AC97 Front Left",
  166. /* 0x11 */ "AC97 Front Right",
  167. /* 0x12 */ "ADC Capture Left",
  168. /* 0x13 */ "ADC Capture Right",
  169. /* 0x14 */ NULL,
  170. /* 0x15 */ NULL,
  171. /* 0x16 */ NULL,
  172. /* 0x17 */ NULL,
  173. /* 0x18 */ NULL,
  174. /* 0x19 */ NULL,
  175. /* 0x1a */ NULL,
  176. /* 0x1b */ NULL,
  177. /* 0x1c */ NULL,
  178. /* 0x1d */ NULL,
  179. /* 0x1e */ NULL,
  180. /* 0x1f */ NULL,
  181. };
  182. // On the SB Live! 5.1, FXBUS2[1] and FXBUS2[2] are occupied by EXTOUT_ACENTER
  183. // and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording.
  184. //
  185. // Since only 14 of the 16 EXTINs are used, this is not a big problem.
  186. // We route AC97 to FX capture 14 and 15, SPDIF_CD to FX capture 0 and 3,
  187. // and the rest of the EXTINs to the corresponding FX capture channel.
  188. // Multitrack recorders will still see the center/LFE output signal
  189. // on the second and third "input" channel.
  190. const s8 snd_emu10k1_sblive51_fxbus2_map[16] = {
  191. 2, -1, -1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0, 1
  192. };
  193. static const u32 bass_table[41][5] = {
  194. { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 },
  195. { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d },
  196. { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee },
  197. { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c },
  198. { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b },
  199. { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 },
  200. { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f },
  201. { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 },
  202. { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 },
  203. { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 },
  204. { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 },
  205. { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be },
  206. { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b },
  207. { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c },
  208. { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b },
  209. { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 },
  210. { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a },
  211. { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 },
  212. { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 },
  213. { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e },
  214. { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee },
  215. { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 },
  216. { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 },
  217. { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 },
  218. { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 },
  219. { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e },
  220. { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 },
  221. { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 },
  222. { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 },
  223. { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 },
  224. { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 },
  225. { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca },
  226. { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 },
  227. { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 },
  228. { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 },
  229. { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 },
  230. { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a },
  231. { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f },
  232. { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 },
  233. { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 },
  234. { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 }
  235. };
  236. static const u32 treble_table[41][5] = {
  237. { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 },
  238. { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 },
  239. { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 },
  240. { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca },
  241. { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 },
  242. { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 },
  243. { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 },
  244. { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 },
  245. { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 },
  246. { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df },
  247. { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff },
  248. { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 },
  249. { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c },
  250. { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 },
  251. { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 },
  252. { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 },
  253. { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 },
  254. { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d },
  255. { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 },
  256. { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 },
  257. { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f },
  258. { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb },
  259. { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 },
  260. { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 },
  261. { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd },
  262. { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 },
  263. { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad },
  264. { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 },
  265. { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 },
  266. { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c },
  267. { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 },
  268. { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 },
  269. { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 },
  270. { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 },
  271. { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 },
  272. { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 },
  273. { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d },
  274. { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b },
  275. { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 },
  276. { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd },
  277. { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 }
  278. };
  279. /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */
  280. static const u32 db_table[101] = {
  281. 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540,
  282. 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8,
  283. 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1,
  284. 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0,
  285. 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9,
  286. 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb,
  287. 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005,
  288. 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d,
  289. 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd,
  290. 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8,
  291. 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481,
  292. 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333,
  293. 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d,
  294. 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6,
  295. 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d,
  296. 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf,
  297. 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038,
  298. 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a,
  299. 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea,
  300. 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272,
  301. 0x7fffffff,
  302. };
  303. /* EMU10k1/EMU10k2 DSP control db gain */
  304. static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1);
  305. static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0);
  306. /* EMU10K1 bass/treble db gain */
  307. static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0);
  308. static const u32 onoff_table[2] = {
  309. 0x00000000, 0x00000001
  310. };
  311. /*
  312. * controls
  313. */
  314. static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  315. {
  316. struct snd_emu10k1_fx8010_ctl *ctl =
  317. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  318. if (ctl->min == 0 && ctl->max == 1)
  319. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  320. else
  321. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  322. uinfo->count = ctl->vcount;
  323. uinfo->value.integer.min = ctl->min;
  324. uinfo->value.integer.max = ctl->max;
  325. return 0;
  326. }
  327. static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  328. {
  329. struct snd_emu10k1_fx8010_ctl *ctl =
  330. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  331. unsigned int i;
  332. for (i = 0; i < ctl->vcount; i++)
  333. ucontrol->value.integer.value[i] = ctl->value[i];
  334. return 0;
  335. }
  336. static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  337. {
  338. struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
  339. struct snd_emu10k1_fx8010_ctl *ctl =
  340. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  341. int nval, val;
  342. unsigned int i, j;
  343. int change = 0;
  344. for (i = 0; i < ctl->vcount; i++) {
  345. nval = ucontrol->value.integer.value[i];
  346. if (nval < ctl->min)
  347. nval = ctl->min;
  348. if (nval > ctl->max)
  349. nval = ctl->max;
  350. if (nval != ctl->value[i])
  351. change = 1;
  352. val = ctl->value[i] = nval;
  353. switch (ctl->translation) {
  354. case EMU10K1_GPR_TRANSLATION_NONE:
  355. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val);
  356. break;
  357. case EMU10K1_GPR_TRANSLATION_NEGATE:
  358. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, ~val);
  359. break;
  360. case EMU10K1_GPR_TRANSLATION_TABLE100:
  361. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]);
  362. break;
  363. case EMU10K1_GPR_TRANSLATION_NEG_TABLE100:
  364. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0,
  365. val == 100 ? 0x80000000 : -(int)db_table[val]);
  366. break;
  367. case EMU10K1_GPR_TRANSLATION_BASS:
  368. if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
  369. change = -EIO;
  370. goto __error;
  371. }
  372. for (j = 0; j < 5; j++)
  373. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]);
  374. break;
  375. case EMU10K1_GPR_TRANSLATION_TREBLE:
  376. if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
  377. change = -EIO;
  378. goto __error;
  379. }
  380. for (j = 0; j < 5; j++)
  381. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]);
  382. break;
  383. case EMU10K1_GPR_TRANSLATION_ONOFF:
  384. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]);
  385. break;
  386. }
  387. }
  388. __error:
  389. return change;
  390. }
  391. /*
  392. * Interrupt handler
  393. */
  394. static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu)
  395. {
  396. struct snd_emu10k1_fx8010_irq *irq, *nirq;
  397. irq = emu->fx8010.irq_handlers;
  398. while (irq) {
  399. nirq = irq->next; /* irq ptr can be removed from list */
  400. if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) {
  401. if (irq->handler)
  402. irq->handler(emu, irq->private_data);
  403. snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1);
  404. }
  405. irq = nirq;
  406. }
  407. }
  408. int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
  409. snd_fx8010_irq_handler_t *handler,
  410. unsigned char gpr_running,
  411. void *private_data,
  412. struct snd_emu10k1_fx8010_irq *irq)
  413. {
  414. unsigned long flags;
  415. irq->handler = handler;
  416. irq->gpr_running = gpr_running;
  417. irq->private_data = private_data;
  418. irq->next = NULL;
  419. spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
  420. if (emu->fx8010.irq_handlers == NULL) {
  421. emu->fx8010.irq_handlers = irq;
  422. emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt;
  423. snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE);
  424. } else {
  425. irq->next = emu->fx8010.irq_handlers;
  426. emu->fx8010.irq_handlers = irq;
  427. }
  428. spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
  429. return 0;
  430. }
  431. int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
  432. struct snd_emu10k1_fx8010_irq *irq)
  433. {
  434. struct snd_emu10k1_fx8010_irq *tmp;
  435. unsigned long flags;
  436. spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
  437. tmp = emu->fx8010.irq_handlers;
  438. if (tmp == irq) {
  439. emu->fx8010.irq_handlers = tmp->next;
  440. if (emu->fx8010.irq_handlers == NULL) {
  441. snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE);
  442. emu->dsp_interrupt = NULL;
  443. }
  444. } else {
  445. while (tmp && tmp->next != irq)
  446. tmp = tmp->next;
  447. if (tmp)
  448. tmp->next = tmp->next->next;
  449. }
  450. spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
  451. return 0;
  452. }
  453. /*************************************************************************
  454. * EMU10K1 effect manager
  455. *************************************************************************/
  456. static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode,
  457. unsigned int *ptr,
  458. u32 op, u32 r, u32 a, u32 x, u32 y)
  459. {
  460. u_int32_t *code;
  461. if (snd_BUG_ON(*ptr >= 512))
  462. return;
  463. code = icode->code + (*ptr) * 2;
  464. set_bit(*ptr, icode->code_valid);
  465. code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff);
  466. code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff);
  467. (*ptr)++;
  468. }
  469. #define OP(icode, ptr, op, r, a, x, y) \
  470. snd_emu10k1_write_op(icode, ptr, op, r, a, x, y)
  471. static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode,
  472. unsigned int *ptr,
  473. u32 op, u32 r, u32 a, u32 x, u32 y)
  474. {
  475. u_int32_t *code;
  476. if (snd_BUG_ON(*ptr >= 1024))
  477. return;
  478. code = icode->code + (*ptr) * 2;
  479. set_bit(*ptr, icode->code_valid);
  480. code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff);
  481. code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff);
  482. (*ptr)++;
  483. }
  484. #define A_OP(icode, ptr, op, r, a, x, y) \
  485. snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y)
  486. static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data)
  487. {
  488. pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
  489. snd_emu10k1_ptr_write(emu, pc, 0, data);
  490. }
  491. unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc)
  492. {
  493. pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
  494. return snd_emu10k1_ptr_read(emu, pc, 0);
  495. }
  496. static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu,
  497. struct snd_emu10k1_fx8010_code *icode,
  498. bool in_kernel)
  499. {
  500. int gpr;
  501. u32 val;
  502. for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
  503. if (!test_bit(gpr, icode->gpr_valid))
  504. continue;
  505. if (in_kernel)
  506. val = icode->gpr_map[gpr];
  507. else if (get_user(val, (__user u32 *)&icode->gpr_map[gpr]))
  508. return -EFAULT;
  509. snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val);
  510. }
  511. return 0;
  512. }
  513. static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu,
  514. struct snd_emu10k1_fx8010_code *icode)
  515. {
  516. int gpr;
  517. u32 val;
  518. for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
  519. set_bit(gpr, icode->gpr_valid);
  520. val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0);
  521. if (put_user(val, (__user u32 *)&icode->gpr_map[gpr]))
  522. return -EFAULT;
  523. }
  524. return 0;
  525. }
  526. static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu,
  527. struct snd_emu10k1_fx8010_code *icode,
  528. bool in_kernel)
  529. {
  530. int tram;
  531. u32 addr, val;
  532. for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
  533. if (!test_bit(tram, icode->tram_valid))
  534. continue;
  535. if (in_kernel) {
  536. val = icode->tram_data_map[tram];
  537. addr = icode->tram_addr_map[tram];
  538. } else {
  539. if (get_user(val, (__user __u32 *)&icode->tram_data_map[tram]) ||
  540. get_user(addr, (__user __u32 *)&icode->tram_addr_map[tram]))
  541. return -EFAULT;
  542. }
  543. snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val);
  544. if (!emu->audigy) {
  545. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr);
  546. } else {
  547. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12);
  548. snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20);
  549. }
  550. }
  551. return 0;
  552. }
  553. static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu,
  554. struct snd_emu10k1_fx8010_code *icode)
  555. {
  556. int tram;
  557. u32 val, addr;
  558. memset(icode->tram_valid, 0, sizeof(icode->tram_valid));
  559. for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
  560. set_bit(tram, icode->tram_valid);
  561. val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0);
  562. if (!emu->audigy) {
  563. addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0);
  564. } else {
  565. addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12;
  566. addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20;
  567. }
  568. if (put_user(val, (__user u32 *)&icode->tram_data_map[tram]) ||
  569. put_user(addr, (__user u32 *)&icode->tram_addr_map[tram]))
  570. return -EFAULT;
  571. }
  572. return 0;
  573. }
  574. static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu,
  575. struct snd_emu10k1_fx8010_code *icode,
  576. bool in_kernel)
  577. {
  578. u32 pc, lo, hi;
  579. for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
  580. if (!test_bit(pc / 2, icode->code_valid))
  581. continue;
  582. if (in_kernel) {
  583. lo = icode->code[pc + 0];
  584. hi = icode->code[pc + 1];
  585. } else {
  586. if (get_user(lo, (__user u32 *)&icode->code[pc + 0]) ||
  587. get_user(hi, (__user u32 *)&icode->code[pc + 1]))
  588. return -EFAULT;
  589. }
  590. snd_emu10k1_efx_write(emu, pc + 0, lo);
  591. snd_emu10k1_efx_write(emu, pc + 1, hi);
  592. }
  593. return 0;
  594. }
  595. static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu,
  596. struct snd_emu10k1_fx8010_code *icode)
  597. {
  598. u32 pc;
  599. memset(icode->code_valid, 0, sizeof(icode->code_valid));
  600. for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
  601. set_bit(pc / 2, icode->code_valid);
  602. if (put_user(snd_emu10k1_efx_read(emu, pc + 0),
  603. (__user u32 *)&icode->code[pc + 0]))
  604. return -EFAULT;
  605. if (put_user(snd_emu10k1_efx_read(emu, pc + 1),
  606. (__user u32 *)&icode->code[pc + 1]))
  607. return -EFAULT;
  608. }
  609. return 0;
  610. }
  611. static struct snd_emu10k1_fx8010_ctl *
  612. snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu,
  613. struct emu10k1_ctl_elem_id *_id)
  614. {
  615. struct snd_ctl_elem_id *id = (struct snd_ctl_elem_id *)_id;
  616. struct snd_emu10k1_fx8010_ctl *ctl;
  617. struct snd_kcontrol *kcontrol;
  618. list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
  619. kcontrol = ctl->kcontrol;
  620. if (kcontrol->id.iface == id->iface &&
  621. kcontrol->id.index == id->index &&
  622. !strcmp(kcontrol->id.name, id->name))
  623. return ctl;
  624. }
  625. return NULL;
  626. }
  627. #define MAX_TLV_SIZE 256
  628. static unsigned int *copy_tlv(const unsigned int __user *_tlv, bool in_kernel)
  629. {
  630. unsigned int data[2];
  631. unsigned int *tlv;
  632. if (!_tlv)
  633. return NULL;
  634. if (in_kernel)
  635. memcpy(data, (__force void *)_tlv, sizeof(data));
  636. else if (copy_from_user(data, _tlv, sizeof(data)))
  637. return NULL;
  638. if (data[1] >= MAX_TLV_SIZE)
  639. return NULL;
  640. tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL);
  641. if (!tlv)
  642. return NULL;
  643. memcpy(tlv, data, sizeof(data));
  644. if (in_kernel) {
  645. memcpy(tlv + 2, (__force void *)(_tlv + 2), data[1]);
  646. } else if (copy_from_user(tlv + 2, _tlv + 2, data[1])) {
  647. kfree(tlv);
  648. return NULL;
  649. }
  650. return tlv;
  651. }
  652. static int copy_gctl(struct snd_emu10k1 *emu,
  653. struct snd_emu10k1_fx8010_control_gpr *dst,
  654. struct snd_emu10k1_fx8010_control_gpr *src,
  655. int idx, bool in_kernel)
  656. {
  657. struct snd_emu10k1_fx8010_control_gpr __user *_src;
  658. struct snd_emu10k1_fx8010_control_old_gpr *octl;
  659. struct snd_emu10k1_fx8010_control_old_gpr __user *_octl;
  660. _src = (struct snd_emu10k1_fx8010_control_gpr __user *)src;
  661. if (emu->support_tlv) {
  662. if (in_kernel)
  663. *dst = src[idx];
  664. else if (copy_from_user(dst, &_src[idx], sizeof(*src)))
  665. return -EFAULT;
  666. return 0;
  667. }
  668. octl = (struct snd_emu10k1_fx8010_control_old_gpr *)src;
  669. _octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)octl;
  670. if (in_kernel)
  671. memcpy(dst, &octl[idx], sizeof(*octl));
  672. else if (copy_from_user(dst, &_octl[idx], sizeof(*octl)))
  673. return -EFAULT;
  674. dst->tlv = NULL;
  675. return 0;
  676. }
  677. static int copy_gctl_to_user(struct snd_emu10k1 *emu,
  678. struct snd_emu10k1_fx8010_control_gpr *dst,
  679. struct snd_emu10k1_fx8010_control_gpr *src,
  680. int idx)
  681. {
  682. struct snd_emu10k1_fx8010_control_gpr __user *_dst;
  683. struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
  684. _dst = (struct snd_emu10k1_fx8010_control_gpr __user *)dst;
  685. if (emu->support_tlv)
  686. return copy_to_user(&_dst[idx], src, sizeof(*src));
  687. octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)dst;
  688. return copy_to_user(&octl[idx], src, sizeof(*octl));
  689. }
  690. static int copy_ctl_elem_id(const struct emu10k1_ctl_elem_id *list, int i,
  691. struct emu10k1_ctl_elem_id *ret, bool in_kernel)
  692. {
  693. struct emu10k1_ctl_elem_id __user *_id =
  694. (struct emu10k1_ctl_elem_id __user *)&list[i];
  695. if (in_kernel)
  696. *ret = list[i];
  697. else if (copy_from_user(ret, _id, sizeof(*ret)))
  698. return -EFAULT;
  699. return 0;
  700. }
  701. static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu,
  702. struct snd_emu10k1_fx8010_code *icode,
  703. bool in_kernel)
  704. {
  705. unsigned int i;
  706. struct emu10k1_ctl_elem_id id;
  707. struct snd_emu10k1_fx8010_control_gpr *gctl;
  708. struct snd_ctl_elem_id *gctl_id;
  709. int err;
  710. for (i = 0; i < icode->gpr_del_control_count; i++) {
  711. err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id,
  712. in_kernel);
  713. if (err < 0)
  714. return err;
  715. if (snd_emu10k1_look_for_ctl(emu, &id) == NULL)
  716. return -ENOENT;
  717. }
  718. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  719. if (! gctl)
  720. return -ENOMEM;
  721. err = 0;
  722. for (i = 0; i < icode->gpr_add_control_count; i++) {
  723. if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
  724. in_kernel)) {
  725. err = -EFAULT;
  726. goto __error;
  727. }
  728. if (snd_emu10k1_look_for_ctl(emu, &gctl->id))
  729. continue;
  730. gctl_id = (struct snd_ctl_elem_id *)&gctl->id;
  731. if (snd_ctl_find_id(emu->card, gctl_id)) {
  732. err = -EEXIST;
  733. goto __error;
  734. }
  735. if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
  736. gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) {
  737. err = -EINVAL;
  738. goto __error;
  739. }
  740. switch (gctl->translation) {
  741. case EMU10K1_GPR_TRANSLATION_NONE:
  742. case EMU10K1_GPR_TRANSLATION_NEGATE:
  743. break;
  744. case EMU10K1_GPR_TRANSLATION_TABLE100:
  745. case EMU10K1_GPR_TRANSLATION_NEG_TABLE100:
  746. if (gctl->min != 0 || gctl->max != 100) {
  747. err = -EINVAL;
  748. goto __error;
  749. }
  750. break;
  751. case EMU10K1_GPR_TRANSLATION_BASS:
  752. case EMU10K1_GPR_TRANSLATION_TREBLE:
  753. if (gctl->min != 0 || gctl->max != 40) {
  754. err = -EINVAL;
  755. goto __error;
  756. }
  757. break;
  758. case EMU10K1_GPR_TRANSLATION_ONOFF:
  759. if (gctl->min != 0 || gctl->max != 1) {
  760. err = -EINVAL;
  761. goto __error;
  762. }
  763. break;
  764. default:
  765. err = -EINVAL;
  766. goto __error;
  767. }
  768. }
  769. for (i = 0; i < icode->gpr_list_control_count; i++) {
  770. /* FIXME: we need to check the WRITE access */
  771. if (copy_gctl(emu, gctl, icode->gpr_list_controls, i,
  772. in_kernel)) {
  773. err = -EFAULT;
  774. goto __error;
  775. }
  776. }
  777. __error:
  778. kfree(gctl);
  779. return err;
  780. }
  781. static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl)
  782. {
  783. struct snd_emu10k1_fx8010_ctl *ctl;
  784. ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value;
  785. kctl->private_value = 0;
  786. list_del(&ctl->list);
  787. kfree(ctl);
  788. kfree(kctl->tlv.p);
  789. }
  790. static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu,
  791. struct snd_emu10k1_fx8010_code *icode,
  792. bool in_kernel)
  793. {
  794. unsigned int i, j;
  795. struct snd_emu10k1_fx8010_control_gpr *gctl;
  796. struct snd_ctl_elem_id *gctl_id;
  797. struct snd_emu10k1_fx8010_ctl *ctl, *nctl;
  798. struct snd_kcontrol_new knew;
  799. struct snd_kcontrol *kctl;
  800. struct snd_ctl_elem_value *val;
  801. int err = 0;
  802. val = kmalloc(sizeof(*val), GFP_KERNEL);
  803. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  804. nctl = kmalloc(sizeof(*nctl), GFP_KERNEL);
  805. if (!val || !gctl || !nctl) {
  806. err = -ENOMEM;
  807. goto __error;
  808. }
  809. for (i = 0; i < icode->gpr_add_control_count; i++) {
  810. if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
  811. in_kernel)) {
  812. err = -EFAULT;
  813. goto __error;
  814. }
  815. gctl_id = (struct snd_ctl_elem_id *)&gctl->id;
  816. if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
  817. gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) {
  818. err = -EINVAL;
  819. goto __error;
  820. }
  821. if (!*gctl_id->name) {
  822. err = -EINVAL;
  823. goto __error;
  824. }
  825. ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id);
  826. memset(&knew, 0, sizeof(knew));
  827. knew.iface = gctl_id->iface;
  828. knew.name = gctl_id->name;
  829. knew.index = gctl_id->index;
  830. knew.device = gctl_id->device;
  831. knew.subdevice = gctl_id->subdevice;
  832. knew.info = snd_emu10k1_gpr_ctl_info;
  833. knew.tlv.p = copy_tlv((const unsigned int __user *)gctl->tlv, in_kernel);
  834. if (knew.tlv.p)
  835. knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  836. SNDRV_CTL_ELEM_ACCESS_TLV_READ;
  837. knew.get = snd_emu10k1_gpr_ctl_get;
  838. knew.put = snd_emu10k1_gpr_ctl_put;
  839. memset(nctl, 0, sizeof(*nctl));
  840. nctl->vcount = gctl->vcount;
  841. nctl->count = gctl->count;
  842. for (j = 0; j < 32; j++) {
  843. nctl->gpr[j] = gctl->gpr[j];
  844. nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */
  845. val->value.integer.value[j] = gctl->value[j];
  846. }
  847. nctl->min = gctl->min;
  848. nctl->max = gctl->max;
  849. nctl->translation = gctl->translation;
  850. if (ctl == NULL) {
  851. ctl = kmalloc(sizeof(*ctl), GFP_KERNEL);
  852. if (ctl == NULL) {
  853. err = -ENOMEM;
  854. kfree(knew.tlv.p);
  855. goto __error;
  856. }
  857. knew.private_value = (unsigned long)ctl;
  858. *ctl = *nctl;
  859. kctl = snd_ctl_new1(&knew, emu);
  860. err = snd_ctl_add(emu->card, kctl);
  861. if (err < 0) {
  862. kfree(ctl);
  863. kfree(knew.tlv.p);
  864. goto __error;
  865. }
  866. kctl->private_free = snd_emu10k1_ctl_private_free;
  867. ctl->kcontrol = kctl;
  868. list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl);
  869. } else {
  870. /* overwrite */
  871. nctl->list = ctl->list;
  872. nctl->kcontrol = ctl->kcontrol;
  873. *ctl = *nctl;
  874. snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE |
  875. SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id);
  876. }
  877. snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val);
  878. }
  879. __error:
  880. kfree(nctl);
  881. kfree(gctl);
  882. kfree(val);
  883. return err;
  884. }
  885. static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu,
  886. struct snd_emu10k1_fx8010_code *icode,
  887. bool in_kernel)
  888. {
  889. unsigned int i;
  890. struct emu10k1_ctl_elem_id id;
  891. struct snd_emu10k1_fx8010_ctl *ctl;
  892. struct snd_card *card = emu->card;
  893. int err;
  894. for (i = 0; i < icode->gpr_del_control_count; i++) {
  895. err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id,
  896. in_kernel);
  897. if (err < 0)
  898. return err;
  899. ctl = snd_emu10k1_look_for_ctl(emu, &id);
  900. if (ctl)
  901. snd_ctl_remove(card, ctl->kcontrol);
  902. }
  903. return 0;
  904. }
  905. static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu,
  906. struct snd_emu10k1_fx8010_code *icode)
  907. {
  908. unsigned int i = 0, j;
  909. unsigned int total = 0;
  910. struct snd_emu10k1_fx8010_control_gpr *gctl;
  911. struct snd_emu10k1_fx8010_ctl *ctl;
  912. struct snd_ctl_elem_id *id;
  913. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  914. if (! gctl)
  915. return -ENOMEM;
  916. list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
  917. total++;
  918. if (icode->gpr_list_controls &&
  919. i < icode->gpr_list_control_count) {
  920. memset(gctl, 0, sizeof(*gctl));
  921. id = &ctl->kcontrol->id;
  922. gctl->id.iface = (__force int)id->iface;
  923. strscpy(gctl->id.name, id->name, sizeof(gctl->id.name));
  924. gctl->id.index = id->index;
  925. gctl->id.device = id->device;
  926. gctl->id.subdevice = id->subdevice;
  927. gctl->vcount = ctl->vcount;
  928. gctl->count = ctl->count;
  929. for (j = 0; j < 32; j++) {
  930. gctl->gpr[j] = ctl->gpr[j];
  931. gctl->value[j] = ctl->value[j];
  932. }
  933. gctl->min = ctl->min;
  934. gctl->max = ctl->max;
  935. gctl->translation = ctl->translation;
  936. if (copy_gctl_to_user(emu, icode->gpr_list_controls,
  937. gctl, i)) {
  938. kfree(gctl);
  939. return -EFAULT;
  940. }
  941. i++;
  942. }
  943. }
  944. icode->gpr_list_control_total = total;
  945. kfree(gctl);
  946. return 0;
  947. }
  948. static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu,
  949. struct snd_emu10k1_fx8010_code *icode,
  950. bool in_kernel)
  951. {
  952. int err = 0;
  953. mutex_lock(&emu->fx8010.lock);
  954. err = snd_emu10k1_verify_controls(emu, icode, in_kernel);
  955. if (err < 0)
  956. goto __error;
  957. strscpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name));
  958. /* stop FX processor - this may be dangerous, but it's better to miss
  959. some samples than generate wrong ones - [jk] */
  960. if (emu->audigy)
  961. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
  962. else
  963. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
  964. /* ok, do the main job */
  965. err = snd_emu10k1_del_controls(emu, icode, in_kernel);
  966. if (err < 0)
  967. goto __error;
  968. err = snd_emu10k1_gpr_poke(emu, icode, in_kernel);
  969. if (err < 0)
  970. goto __error;
  971. err = snd_emu10k1_tram_poke(emu, icode, in_kernel);
  972. if (err < 0)
  973. goto __error;
  974. err = snd_emu10k1_code_poke(emu, icode, in_kernel);
  975. if (err < 0)
  976. goto __error;
  977. err = snd_emu10k1_add_controls(emu, icode, in_kernel);
  978. if (err < 0)
  979. goto __error;
  980. /* start FX processor when the DSP code is updated */
  981. if (emu->audigy)
  982. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  983. else
  984. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  985. __error:
  986. mutex_unlock(&emu->fx8010.lock);
  987. return err;
  988. }
  989. static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu,
  990. struct snd_emu10k1_fx8010_code *icode)
  991. {
  992. int err;
  993. mutex_lock(&emu->fx8010.lock);
  994. strscpy(icode->name, emu->fx8010.name, sizeof(icode->name));
  995. /* ok, do the main job */
  996. err = snd_emu10k1_gpr_peek(emu, icode);
  997. if (err >= 0)
  998. err = snd_emu10k1_tram_peek(emu, icode);
  999. if (err >= 0)
  1000. err = snd_emu10k1_code_peek(emu, icode);
  1001. if (err >= 0)
  1002. err = snd_emu10k1_list_controls(emu, icode);
  1003. mutex_unlock(&emu->fx8010.lock);
  1004. return err;
  1005. }
  1006. static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu,
  1007. struct snd_emu10k1_fx8010_pcm_rec *ipcm)
  1008. {
  1009. unsigned int i;
  1010. int err = 0;
  1011. struct snd_emu10k1_fx8010_pcm *pcm;
  1012. if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
  1013. return -EINVAL;
  1014. ipcm->substream = array_index_nospec(ipcm->substream,
  1015. EMU10K1_FX8010_PCM_COUNT);
  1016. if (ipcm->channels > 32)
  1017. return -EINVAL;
  1018. pcm = &emu->fx8010.pcm[ipcm->substream];
  1019. mutex_lock(&emu->fx8010.lock);
  1020. spin_lock_irq(&emu->reg_lock);
  1021. if (pcm->opened) {
  1022. err = -EBUSY;
  1023. goto __error;
  1024. }
  1025. if (ipcm->channels == 0) { /* remove */
  1026. pcm->valid = 0;
  1027. } else {
  1028. /* FIXME: we need to add universal code to the PCM transfer routine */
  1029. if (ipcm->channels != 2) {
  1030. err = -EINVAL;
  1031. goto __error;
  1032. }
  1033. pcm->valid = 1;
  1034. pcm->opened = 0;
  1035. pcm->channels = ipcm->channels;
  1036. pcm->tram_start = ipcm->tram_start;
  1037. pcm->buffer_size = ipcm->buffer_size;
  1038. pcm->gpr_size = ipcm->gpr_size;
  1039. pcm->gpr_count = ipcm->gpr_count;
  1040. pcm->gpr_tmpcount = ipcm->gpr_tmpcount;
  1041. pcm->gpr_ptr = ipcm->gpr_ptr;
  1042. pcm->gpr_trigger = ipcm->gpr_trigger;
  1043. pcm->gpr_running = ipcm->gpr_running;
  1044. for (i = 0; i < pcm->channels; i++)
  1045. pcm->etram[i] = ipcm->etram[i];
  1046. }
  1047. __error:
  1048. spin_unlock_irq(&emu->reg_lock);
  1049. mutex_unlock(&emu->fx8010.lock);
  1050. return err;
  1051. }
  1052. static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu,
  1053. struct snd_emu10k1_fx8010_pcm_rec *ipcm)
  1054. {
  1055. unsigned int i;
  1056. int err = 0;
  1057. struct snd_emu10k1_fx8010_pcm *pcm;
  1058. if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
  1059. return -EINVAL;
  1060. ipcm->substream = array_index_nospec(ipcm->substream,
  1061. EMU10K1_FX8010_PCM_COUNT);
  1062. pcm = &emu->fx8010.pcm[ipcm->substream];
  1063. mutex_lock(&emu->fx8010.lock);
  1064. spin_lock_irq(&emu->reg_lock);
  1065. ipcm->channels = pcm->channels;
  1066. ipcm->tram_start = pcm->tram_start;
  1067. ipcm->buffer_size = pcm->buffer_size;
  1068. ipcm->gpr_size = pcm->gpr_size;
  1069. ipcm->gpr_ptr = pcm->gpr_ptr;
  1070. ipcm->gpr_count = pcm->gpr_count;
  1071. ipcm->gpr_tmpcount = pcm->gpr_tmpcount;
  1072. ipcm->gpr_trigger = pcm->gpr_trigger;
  1073. ipcm->gpr_running = pcm->gpr_running;
  1074. for (i = 0; i < pcm->channels; i++)
  1075. ipcm->etram[i] = pcm->etram[i];
  1076. ipcm->res1 = ipcm->res2 = 0;
  1077. ipcm->pad = 0;
  1078. spin_unlock_irq(&emu->reg_lock);
  1079. mutex_unlock(&emu->fx8010.lock);
  1080. return err;
  1081. }
  1082. #define SND_EMU10K1_GPR_CONTROLS 44
  1083. #define SND_EMU10K1_INPUTS 12
  1084. #define SND_EMU10K1_PLAYBACK_CHANNELS 8
  1085. #define SND_EMU10K1_CAPTURE_CHANNELS 4
  1086. #define HR_VAL(v) ((v) * 0x80000000LL / 100 - 1)
  1087. static void
  1088. snd_emu10k1_init_mono_control2(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1089. const char *name, int gpr, int defval, int defval_hr)
  1090. {
  1091. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1092. strcpy(ctl->id.name, name);
  1093. ctl->vcount = ctl->count = 1;
  1094. if (high_res_gpr_volume) {
  1095. ctl->min = -1;
  1096. ctl->max = 0x7fffffff;
  1097. ctl->tlv = snd_emu10k1_db_linear;
  1098. ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE;
  1099. defval = defval_hr;
  1100. } else {
  1101. ctl->min = 0;
  1102. ctl->max = 100;
  1103. ctl->tlv = snd_emu10k1_db_scale1;
  1104. ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100;
  1105. }
  1106. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1107. }
  1108. #define snd_emu10k1_init_mono_control(ctl, name, gpr, defval) \
  1109. snd_emu10k1_init_mono_control2(ctl, name, gpr, defval, HR_VAL(defval))
  1110. static void
  1111. snd_emu10k1_init_stereo_control2(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1112. const char *name, int gpr, int defval, int defval_hr)
  1113. {
  1114. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1115. strcpy(ctl->id.name, name);
  1116. ctl->vcount = ctl->count = 2;
  1117. if (high_res_gpr_volume) {
  1118. ctl->min = -1;
  1119. ctl->max = 0x7fffffff;
  1120. ctl->tlv = snd_emu10k1_db_linear;
  1121. ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE;
  1122. defval = defval_hr;
  1123. } else {
  1124. ctl->min = 0;
  1125. ctl->max = 100;
  1126. ctl->tlv = snd_emu10k1_db_scale1;
  1127. ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100;
  1128. }
  1129. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1130. ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
  1131. }
  1132. #define snd_emu10k1_init_stereo_control(ctl, name, gpr, defval) \
  1133. snd_emu10k1_init_stereo_control2(ctl, name, gpr, defval, HR_VAL(defval))
  1134. static void
  1135. snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1136. const char *name, int gpr, int defval)
  1137. {
  1138. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1139. strcpy(ctl->id.name, name);
  1140. ctl->vcount = ctl->count = 1;
  1141. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1142. ctl->min = 0;
  1143. ctl->max = 1;
  1144. ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
  1145. }
  1146. static void
  1147. snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1148. const char *name, int gpr, int defval)
  1149. {
  1150. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1151. strcpy(ctl->id.name, name);
  1152. ctl->vcount = ctl->count = 2;
  1153. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1154. ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
  1155. ctl->min = 0;
  1156. ctl->max = 1;
  1157. ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
  1158. }
  1159. /*
  1160. * Used for emu1010 - conversion from 32-bit capture inputs from the FPGA
  1161. * to 2 x 16-bit registers in Audigy - their values are read via DMA.
  1162. * Conversion is performed by Audigy DSP instructions of FX8010.
  1163. */
  1164. static void snd_emu10k1_audigy_dsp_convert_32_to_2x16(
  1165. struct snd_emu10k1_fx8010_code *icode,
  1166. u32 *ptr, int tmp, int bit_shifter16,
  1167. int reg_in, int reg_out)
  1168. {
  1169. // This leaves the low word in place, which is fine,
  1170. // as the low bits are completely ignored subsequently.
  1171. // reg_out[1] = reg_in
  1172. A_OP(icode, ptr, iACC3, reg_out + 1, reg_in, A_C_00000000, A_C_00000000);
  1173. // It is fine to read reg_in multiple times.
  1174. // tmp = reg_in << 15
  1175. A_OP(icode, ptr, iMACINT1, A_GPR(tmp), A_C_00000000, reg_in, A_GPR(bit_shifter16));
  1176. // Left-shift once more. This is a separate step, as the
  1177. // signed multiplication would clobber the MSB.
  1178. // reg_out[0] = tmp + ((tmp << 31) >> 31)
  1179. A_OP(icode, ptr, iMAC3, reg_out, A_GPR(tmp), A_GPR(tmp), A_C_80000000);
  1180. }
  1181. #define ENUM_GPR(name, size) name, name ## _dummy = name + (size) - 1
  1182. /*
  1183. * initial DSP configuration for Audigy
  1184. */
  1185. static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
  1186. {
  1187. int err, z, nctl;
  1188. enum {
  1189. ENUM_GPR(playback, SND_EMU10K1_PLAYBACK_CHANNELS),
  1190. ENUM_GPR(stereo_mix, 2),
  1191. ENUM_GPR(capture, 2),
  1192. ENUM_GPR(bit_shifter16, 1),
  1193. // The fixed allocation of these breaks the pattern, but why not.
  1194. // Splitting these into left/right is questionable, as it will break
  1195. // down for center/lfe. But it works for stereo/quadro, so whatever.
  1196. ENUM_GPR(bass_gpr, 2 * 5), // two sides, five coefficients
  1197. ENUM_GPR(treble_gpr, 2 * 5),
  1198. ENUM_GPR(bass_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4), // four delay stages
  1199. ENUM_GPR(treble_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4),
  1200. ENUM_GPR(tmp, 3),
  1201. num_static_gprs
  1202. };
  1203. int gpr = num_static_gprs;
  1204. u32 ptr, ptr_skip;
  1205. struct snd_emu10k1_fx8010_code *icode = NULL;
  1206. struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
  1207. u32 *gpr_map;
  1208. err = -ENOMEM;
  1209. icode = kzalloc(sizeof(*icode), GFP_KERNEL);
  1210. if (!icode)
  1211. return err;
  1212. icode->gpr_map = kcalloc(512 + 256 + 256 + 2 * 1024,
  1213. sizeof(u_int32_t), GFP_KERNEL);
  1214. if (!icode->gpr_map)
  1215. goto __err_gpr;
  1216. controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
  1217. sizeof(*controls), GFP_KERNEL);
  1218. if (!controls)
  1219. goto __err_ctrls;
  1220. gpr_map = icode->gpr_map;
  1221. icode->tram_data_map = icode->gpr_map + 512;
  1222. icode->tram_addr_map = icode->tram_data_map + 256;
  1223. icode->code = icode->tram_addr_map + 256;
  1224. /* clear free GPRs */
  1225. memset(icode->gpr_valid, 0xff, 512 / 8);
  1226. /* clear TRAM data & address lines */
  1227. memset(icode->tram_valid, 0xff, 256 / 8);
  1228. strcpy(icode->name, "Audigy DSP code for ALSA");
  1229. ptr = 0;
  1230. nctl = 0;
  1231. gpr_map[bit_shifter16] = 0x00008000;
  1232. #if 1
  1233. /* PCM front Playback Volume (independent from stereo mix)
  1234. * playback = -gpr * FXBUS_PCM_LEFT_FRONT >> 31
  1235. * where gpr contains negated attenuation from corresponding mixer control
  1236. * (snd_emu10k1_init_stereo_control)
  1237. */
  1238. A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));
  1239. A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));
  1240. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100);
  1241. gpr += 2;
  1242. /* PCM Surround Playback (independent from stereo mix) */
  1243. A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));
  1244. A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));
  1245. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100);
  1246. gpr += 2;
  1247. /* PCM Side Playback (independent from stereo mix) */
  1248. if (emu->card_capabilities->spk71) {
  1249. A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));
  1250. A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));
  1251. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100);
  1252. gpr += 2;
  1253. }
  1254. /* PCM Center Playback (independent from stereo mix) */
  1255. A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));
  1256. snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100);
  1257. gpr++;
  1258. /* PCM LFE Playback (independent from stereo mix) */
  1259. A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));
  1260. snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100);
  1261. gpr++;
  1262. /*
  1263. * Stereo Mix
  1264. */
  1265. /* Wave (PCM) Playback Volume (will be renamed later) */
  1266. A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
  1267. A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
  1268. snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100);
  1269. gpr += 2;
  1270. /* Synth Playback */
  1271. A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
  1272. A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
  1273. snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100);
  1274. gpr += 2;
  1275. /* Wave (PCM) Capture */
  1276. A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
  1277. A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
  1278. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0);
  1279. gpr += 2;
  1280. /* Synth Capture */
  1281. A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
  1282. A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
  1283. snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0);
  1284. gpr += 2;
  1285. // We need to double the volume, as we configure the voices for half volume,
  1286. // which is necessary for bit-identical reproduction.
  1287. { static_assert(stereo_mix == playback + SND_EMU10K1_PLAYBACK_CHANNELS); }
  1288. for (z = 0; z < SND_EMU10K1_PLAYBACK_CHANNELS + 2; z++)
  1289. A_OP(icode, &ptr, iACC3, A_GPR(playback + z), A_GPR(playback + z), A_GPR(playback + z), A_C_00000000);
  1290. /*
  1291. * inputs
  1292. */
  1293. #define A_ADD_VOLUME_IN(var,vol,input) \
  1294. A_OP(icode, &ptr, iMAC1, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
  1295. if (emu->card_capabilities->emu_model) {
  1296. /* EMU1010 DSP 0 and DSP 1 Capture */
  1297. // The 24 MSB hold the actual value. We implicitly discard the 16 LSB.
  1298. if (emu->card_capabilities->ca0108_chip) {
  1299. // For unclear reasons, the EMU32IN cannot be the Y operand!
  1300. A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A3_EMU32IN(0x0), A_GPR(gpr));
  1301. // A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels
  1302. // need to be delayed as well; we use an auxiliary register for that.
  1303. A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1));
  1304. A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A3_EMU32IN(0x1), A_C_00000000, A_C_00000000);
  1305. } else {
  1306. A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_P16VIN(0x0), A_GPR(gpr));
  1307. // A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels
  1308. // need to be delayed as well; we use an auxiliary register for that.
  1309. A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1));
  1310. A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A_P16VIN(0x1), A_C_00000000, A_C_00000000);
  1311. }
  1312. snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0);
  1313. gpr_map[gpr + 2] = 0x00000000;
  1314. gpr += 3;
  1315. } else {
  1316. if (emu->card_capabilities->ac97_chip) {
  1317. /* AC'97 Playback Volume - used only for mic (renamed later) */
  1318. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L);
  1319. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R);
  1320. snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0);
  1321. gpr += 2;
  1322. /* AC'97 Capture Volume - used only for mic */
  1323. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L);
  1324. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R);
  1325. snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0);
  1326. gpr += 2;
  1327. /* mic capture buffer */
  1328. A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), A_C_40000000, A_EXTIN(A_EXTIN_AC97_R));
  1329. }
  1330. /* Audigy CD Playback Volume */
  1331. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);
  1332. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R);
  1333. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1334. emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume",
  1335. gpr, 0);
  1336. gpr += 2;
  1337. /* Audigy CD Capture Volume */
  1338. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L);
  1339. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R);
  1340. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1341. emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume",
  1342. gpr, 0);
  1343. gpr += 2;
  1344. /* Optical SPDIF Playback Volume */
  1345. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L);
  1346. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
  1347. snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0);
  1348. gpr += 2;
  1349. /* Optical SPDIF Capture Volume */
  1350. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L);
  1351. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
  1352. snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0);
  1353. gpr += 2;
  1354. /* Line2 Playback Volume */
  1355. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L);
  1356. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R);
  1357. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1358. emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume",
  1359. gpr, 0);
  1360. gpr += 2;
  1361. /* Line2 Capture Volume */
  1362. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L);
  1363. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R);
  1364. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1365. emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume",
  1366. gpr, 0);
  1367. gpr += 2;
  1368. /* Philips ADC Playback Volume */
  1369. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L);
  1370. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R);
  1371. snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0);
  1372. gpr += 2;
  1373. /* Philips ADC Capture Volume */
  1374. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L);
  1375. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R);
  1376. snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0);
  1377. gpr += 2;
  1378. /* Aux2 Playback Volume */
  1379. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L);
  1380. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R);
  1381. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1382. emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume",
  1383. gpr, 0);
  1384. gpr += 2;
  1385. /* Aux2 Capture Volume */
  1386. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L);
  1387. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R);
  1388. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1389. emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume",
  1390. gpr, 0);
  1391. gpr += 2;
  1392. }
  1393. /* Stereo Mix Front Playback Volume */
  1394. A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));
  1395. A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1396. snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100);
  1397. gpr += 2;
  1398. /* Stereo Mix Surround Playback */
  1399. A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));
  1400. A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1401. snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0);
  1402. gpr += 2;
  1403. /* Stereo Mix Center Playback */
  1404. /* Center = sub = Left/2 + Right/2 */
  1405. A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), A_C_40000000, A_GPR(stereo_mix+1));
  1406. A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));
  1407. snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0);
  1408. gpr++;
  1409. /* Stereo Mix LFE Playback */
  1410. A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));
  1411. snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0);
  1412. gpr++;
  1413. if (emu->card_capabilities->spk71) {
  1414. /* Stereo Mix Side Playback */
  1415. A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));
  1416. A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1417. snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0);
  1418. gpr += 2;
  1419. }
  1420. /*
  1421. * outputs
  1422. */
  1423. #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src))
  1424. #define A_PUT_STEREO_OUTPUT(out1,out2,src) \
  1425. {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);}
  1426. #define _A_SWITCH(icode, ptr, dst, src, sw) \
  1427. A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw);
  1428. #define A_SWITCH(icode, ptr, dst, src, sw) \
  1429. _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw))
  1430. #define _A_SWITCH_NEG(icode, ptr, dst, src) \
  1431. A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001);
  1432. #define A_SWITCH_NEG(icode, ptr, dst, src) \
  1433. _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src))
  1434. /*
  1435. * Process tone control
  1436. */
  1437. ctl = &controls[nctl + 0];
  1438. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1439. strcpy(ctl->id.name, "Tone Control - Bass");
  1440. ctl->vcount = 2;
  1441. ctl->count = 10;
  1442. ctl->min = 0;
  1443. ctl->max = 40;
  1444. ctl->value[0] = ctl->value[1] = 20;
  1445. ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
  1446. ctl = &controls[nctl + 1];
  1447. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1448. strcpy(ctl->id.name, "Tone Control - Treble");
  1449. ctl->vcount = 2;
  1450. ctl->count = 10;
  1451. ctl->min = 0;
  1452. ctl->max = 40;
  1453. ctl->value[0] = ctl->value[1] = 20;
  1454. ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
  1455. for (z = 0; z < 5; z++) {
  1456. int j;
  1457. for (j = 0; j < 2; j++) {
  1458. controls[nctl + 0].gpr[z * 2 + j] = bass_gpr + z * 2 + j;
  1459. controls[nctl + 1].gpr[z * 2 + j] = treble_gpr + z * 2 + j;
  1460. }
  1461. }
  1462. nctl += 2;
  1463. A_OP(icode, &ptr, iACC3, A_C_00000000, A_GPR(gpr), A_C_00000000, A_C_00000000);
  1464. snd_emu10k1_init_mono_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0);
  1465. gpr++;
  1466. A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_CC_REG_ZERO, A_GPR(gpr));
  1467. ptr_skip = ptr;
  1468. for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */
  1469. int j, k, l, d;
  1470. for (j = 0; j < 2; j++) { /* left/right */
  1471. k = bass_tmp + (z * 8) + (j * 4);
  1472. l = treble_tmp + (z * 8) + (j * 4);
  1473. d = playback + z * 2 + j;
  1474. A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(bass_gpr + 0 + j));
  1475. A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(bass_gpr + 4 + j));
  1476. A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(bass_gpr + 2 + j));
  1477. A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(bass_gpr + 8 + j));
  1478. A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(bass_gpr + 6 + j));
  1479. A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);
  1480. A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(treble_gpr + 0 + j));
  1481. A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(treble_gpr + 4 + j));
  1482. A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(treble_gpr + 2 + j));
  1483. A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(treble_gpr + 8 + j));
  1484. A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(treble_gpr + 6 + j));
  1485. A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010);
  1486. A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000);
  1487. if (z == 2) /* center */
  1488. break;
  1489. }
  1490. }
  1491. gpr_map[gpr++] = ptr - ptr_skip;
  1492. /* Master volume (will be renamed later) */
  1493. for (z = 0; z < 8; z++)
  1494. A_OP(icode, &ptr, iMAC1, A_GPR(playback+z), A_C_00000000, A_GPR(gpr), A_GPR(playback+z));
  1495. snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0);
  1496. gpr++;
  1497. if (emu->card_capabilities->emu_model) {
  1498. /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */
  1499. dev_info(emu->card->dev, "EMU outputs on\n");
  1500. for (z = 0; z < 8; z++) {
  1501. if (emu->card_capabilities->ca0108_chip) {
  1502. A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + z), A_C_00000000, A_C_00000000);
  1503. } else {
  1504. A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + z), A_C_00000000, A_C_00000000);
  1505. }
  1506. }
  1507. } else {
  1508. /* analog speakers */
  1509. A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback);
  1510. A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2);
  1511. A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4);
  1512. A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5);
  1513. if (emu->card_capabilities->spk71)
  1514. A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6);
  1515. /* headphone */
  1516. A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback);
  1517. /* IEC958 Optical Raw Playback Switch */
  1518. gpr_map[gpr++] = 0;
  1519. gpr_map[gpr++] = 0x1008;
  1520. gpr_map[gpr++] = 0xffff0000;
  1521. for (z = 0; z < 2; z++) {
  1522. A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000);
  1523. A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001);
  1524. A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2));
  1525. A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000);
  1526. A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z);
  1527. A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
  1528. A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
  1529. if ((z==1) && (emu->card_capabilities->spdif_bug)) {
  1530. /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */
  1531. dev_info(emu->card->dev,
  1532. "Installing spdif_bug patch: %s\n",
  1533. emu->card_capabilities->name);
  1534. A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000);
  1535. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1536. } else {
  1537. A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1538. }
  1539. }
  1540. snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
  1541. gpr += 2;
  1542. A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2);
  1543. A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4);
  1544. A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5);
  1545. }
  1546. /* ADC buffer */
  1547. #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
  1548. A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback);
  1549. #else
  1550. A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture);
  1551. A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1);
  1552. #endif
  1553. if (emu->card_capabilities->emu_model) {
  1554. /* Capture 16 channels of S32_LE sound. */
  1555. if (emu->card_capabilities->ca0108_chip) {
  1556. dev_info(emu->card->dev, "EMU2 inputs on\n");
  1557. /* Note that the Tina[2] DSPs have 16 more EMU32 inputs which we don't use. */
  1558. snd_emu10k1_audigy_dsp_convert_32_to_2x16(
  1559. icode, &ptr, tmp, bit_shifter16, A3_EMU32IN(0), A_FXBUS2(0));
  1560. // A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels
  1561. // need to be delayed as well; we use an auxiliary register for that.
  1562. for (z = 1; z < 0x10; z++) {
  1563. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp,
  1564. bit_shifter16,
  1565. A_GPR(gpr),
  1566. A_FXBUS2(z*2) );
  1567. A_OP(icode, &ptr, iACC3, A_GPR(gpr), A3_EMU32IN(z), A_C_00000000, A_C_00000000);
  1568. gpr_map[gpr++] = 0x00000000;
  1569. }
  1570. } else {
  1571. dev_info(emu->card->dev, "EMU inputs on\n");
  1572. /* Note that the Alice2 DSPs have 6 I2S inputs which we don't use. */
  1573. /*
  1574. dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n",
  1575. gpr, tmp);
  1576. */
  1577. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
  1578. /* A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels
  1579. * will need to also be delayed; we use an auxiliary register for that. */
  1580. for (z = 1; z < 0x10; z++) {
  1581. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr), A_FXBUS2(z * 2) );
  1582. A_OP(icode, &ptr, iACC3, A_GPR(gpr), A_P16VIN(z), A_C_00000000, A_C_00000000);
  1583. gpr_map[gpr++] = 0x00000000;
  1584. }
  1585. }
  1586. #if 0
  1587. for (z = 4; z < 8; z++) {
  1588. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
  1589. }
  1590. for (z = 0xc; z < 0x10; z++) {
  1591. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
  1592. }
  1593. #endif
  1594. } else {
  1595. /* EFX capture - capture the 16 EXTINs */
  1596. /* Capture 16 channels of S16_LE sound */
  1597. for (z = 0; z < 16; z++) {
  1598. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z));
  1599. }
  1600. }
  1601. #endif /* JCD test */
  1602. /*
  1603. * ok, set up done..
  1604. */
  1605. if (gpr > 512) {
  1606. snd_BUG();
  1607. err = -EIO;
  1608. goto __err;
  1609. }
  1610. /* clear remaining instruction memory */
  1611. while (ptr < 0x400)
  1612. A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0);
  1613. icode->gpr_add_control_count = nctl;
  1614. icode->gpr_add_controls = controls;
  1615. emu->support_tlv = 1; /* support TLV */
  1616. err = snd_emu10k1_icode_poke(emu, icode, true);
  1617. emu->support_tlv = 0; /* clear again */
  1618. __err:
  1619. kfree(controls);
  1620. __err_ctrls:
  1621. kfree(icode->gpr_map);
  1622. __err_gpr:
  1623. kfree(icode);
  1624. return err;
  1625. }
  1626. /*
  1627. * initial DSP configuration for Emu10k1
  1628. */
  1629. /* Volumes are in the [-2^31, 0] range, zero being mute. */
  1630. static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1631. {
  1632. OP(icode, ptr, iMAC1, dst, C_00000000, src, vol);
  1633. }
  1634. static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1635. {
  1636. OP(icode, ptr, iMAC1, dst, dst, src, vol);
  1637. }
  1638. #define VOLUME(icode, ptr, dst, src, vol) \
  1639. _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol))
  1640. #define VOLUME_IN(icode, ptr, dst, src, vol) \
  1641. _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
  1642. #define VOLUME_ADD(icode, ptr, dst, src, vol) \
  1643. _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol))
  1644. #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \
  1645. _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
  1646. #define VOLUME_OUT(icode, ptr, dst, src, vol) \
  1647. _volume(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))
  1648. #define _SWITCH(icode, ptr, dst, src, sw) \
  1649. OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw);
  1650. #define SWITCH(icode, ptr, dst, src, sw) \
  1651. _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw))
  1652. #define SWITCH_IN(icode, ptr, dst, src, sw) \
  1653. _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw))
  1654. #define _SWITCH_NEG(icode, ptr, dst, src) \
  1655. OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001);
  1656. #define SWITCH_NEG(icode, ptr, dst, src) \
  1657. _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src))
  1658. static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
  1659. {
  1660. int err, i, z, gpr, tmp, playback, capture;
  1661. u32 ptr, ptr_skip;
  1662. struct snd_emu10k1_fx8010_code *icode;
  1663. struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL;
  1664. struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
  1665. u32 *gpr_map;
  1666. err = -ENOMEM;
  1667. icode = kzalloc(sizeof(*icode), GFP_KERNEL);
  1668. if (!icode)
  1669. return err;
  1670. icode->gpr_map = kcalloc(256 + 160 + 160 + 2 * 512,
  1671. sizeof(u_int32_t), GFP_KERNEL);
  1672. if (!icode->gpr_map)
  1673. goto __err_gpr;
  1674. controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
  1675. sizeof(struct snd_emu10k1_fx8010_control_gpr),
  1676. GFP_KERNEL);
  1677. if (!controls)
  1678. goto __err_ctrls;
  1679. ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL);
  1680. if (!ipcm)
  1681. goto __err_ipcm;
  1682. gpr_map = icode->gpr_map;
  1683. icode->tram_data_map = icode->gpr_map + 256;
  1684. icode->tram_addr_map = icode->tram_data_map + 160;
  1685. icode->code = icode->tram_addr_map + 160;
  1686. /* clear free GPRs */
  1687. memset(icode->gpr_valid, 0xff, 256 / 8);
  1688. /* clear TRAM data & address lines */
  1689. memset(icode->tram_valid, 0xff, 160 / 8);
  1690. strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela");
  1691. ptr = 0; i = 0;
  1692. /* we have 12 inputs */
  1693. playback = SND_EMU10K1_INPUTS;
  1694. /* we have 6 playback channels and tone control doubles */
  1695. capture = playback + SND_EMU10K1_PLAYBACK_CHANNELS;
  1696. gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS;
  1697. tmp = 0x88; /* we need 4 temporary GPR */
  1698. /* from 0x8c to 0xff is the area for tone control */
  1699. /*
  1700. * Process FX Buses
  1701. */
  1702. OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000008);
  1703. OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000008);
  1704. OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000008);
  1705. OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000008);
  1706. OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000008);
  1707. OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000008);
  1708. OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000008);
  1709. OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000008);
  1710. OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */
  1711. OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */
  1712. OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000008);
  1713. OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000008);
  1714. /* Raw S/PDIF PCM */
  1715. ipcm->substream = 0;
  1716. ipcm->channels = 2;
  1717. ipcm->tram_start = 0;
  1718. ipcm->buffer_size = (64 * 1024) / 2;
  1719. ipcm->gpr_size = gpr++;
  1720. ipcm->gpr_ptr = gpr++;
  1721. ipcm->gpr_count = gpr++;
  1722. ipcm->gpr_tmpcount = gpr++;
  1723. ipcm->gpr_trigger = gpr++;
  1724. ipcm->gpr_running = gpr++;
  1725. ipcm->etram[0] = 0;
  1726. ipcm->etram[1] = 1;
  1727. gpr_map[gpr + 0] = 0xfffff000;
  1728. gpr_map[gpr + 1] = 0xffff0000;
  1729. gpr_map[gpr + 2] = 0x70000000;
  1730. gpr_map[gpr + 3] = 0x00000007;
  1731. gpr_map[gpr + 4] = 0x001f << 11;
  1732. gpr_map[gpr + 5] = 0x001c << 11;
  1733. gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */
  1734. gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */
  1735. gpr_map[gpr + 8] = 0x2000000 + (2<<11);
  1736. gpr_map[gpr + 9] = 0x4000000 + (2<<11);
  1737. gpr_map[gpr + 10] = 1<<11;
  1738. gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */
  1739. gpr_map[gpr + 12] = 0;
  1740. /* if the trigger flag is not set, skip */
  1741. /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000);
  1742. /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6));
  1743. /* if the running flag is set, we're running */
  1744. /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000);
  1745. /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004);
  1746. /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */
  1747. /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000);
  1748. /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5));
  1749. /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7));
  1750. /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000);
  1751. /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001);
  1752. /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000);
  1753. /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11));
  1754. /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000);
  1755. /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000);
  1756. /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
  1757. /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
  1758. /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
  1759. /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2));
  1760. /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000);
  1761. /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
  1762. /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
  1763. /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
  1764. /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2));
  1765. /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000);
  1766. /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size));
  1767. /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001);
  1768. /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000);
  1769. /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000);
  1770. /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000);
  1771. /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1772. /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000);
  1773. /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000);
  1774. /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000);
  1775. /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001);
  1776. /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002);
  1777. /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff);
  1778. /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff);
  1779. /* 24: */
  1780. gpr += 13;
  1781. /* Wave Playback Volume */
  1782. for (z = 0; z < 2; z++)
  1783. VOLUME(icode, &ptr, playback + z, z, gpr + z);
  1784. snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100);
  1785. gpr += 2;
  1786. /* Wave Surround Playback Volume */
  1787. for (z = 0; z < 2; z++)
  1788. VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z);
  1789. snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0);
  1790. gpr += 2;
  1791. /* Wave Center/LFE Playback Volume */
  1792. OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000);
  1793. OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000004);
  1794. VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr);
  1795. snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0);
  1796. VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr);
  1797. snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0);
  1798. /* Wave Capture Volume + Switch */
  1799. for (z = 0; z < 2; z++) {
  1800. SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z);
  1801. VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1802. }
  1803. snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0);
  1804. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0);
  1805. gpr += 4;
  1806. /* Synth Playback Volume */
  1807. for (z = 0; z < 2; z++)
  1808. VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z);
  1809. snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100);
  1810. gpr += 2;
  1811. /* Synth Capture Volume + Switch */
  1812. for (z = 0; z < 2; z++) {
  1813. SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z);
  1814. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1815. }
  1816. snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0);
  1817. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0);
  1818. gpr += 4;
  1819. /* Surround Digital Playback Volume (renamed later without Digital) */
  1820. for (z = 0; z < 2; z++)
  1821. VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z);
  1822. snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100);
  1823. gpr += 2;
  1824. /* Surround Capture Volume + Switch */
  1825. for (z = 0; z < 2; z++) {
  1826. SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z);
  1827. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1828. }
  1829. snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0);
  1830. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0);
  1831. gpr += 4;
  1832. /* Center Playback Volume (renamed later without Digital) */
  1833. VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr);
  1834. snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100);
  1835. /* LFE Playback Volume + Switch (renamed later without Digital) */
  1836. VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr);
  1837. snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100);
  1838. /* Front Playback Volume */
  1839. for (z = 0; z < 2; z++)
  1840. VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z);
  1841. snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100);
  1842. gpr += 2;
  1843. /* Front Capture Volume + Switch */
  1844. for (z = 0; z < 2; z++) {
  1845. SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2);
  1846. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1847. }
  1848. snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0);
  1849. snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0);
  1850. gpr += 3;
  1851. /*
  1852. * Process inputs
  1853. */
  1854. if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) {
  1855. /* AC'97 Playback Volume */
  1856. VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++;
  1857. VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++;
  1858. snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0);
  1859. /* AC'97 Capture Volume */
  1860. VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++;
  1861. VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++;
  1862. snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100);
  1863. }
  1864. if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) {
  1865. /* IEC958 TTL Playback Volume */
  1866. for (z = 0; z < 2; z++)
  1867. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z);
  1868. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0);
  1869. gpr += 2;
  1870. /* IEC958 TTL Capture Volume + Switch */
  1871. for (z = 0; z < 2; z++) {
  1872. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z);
  1873. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1874. }
  1875. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0);
  1876. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0);
  1877. gpr += 4;
  1878. }
  1879. if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) {
  1880. /* Zoom Video Playback Volume */
  1881. for (z = 0; z < 2; z++)
  1882. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z);
  1883. snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0);
  1884. gpr += 2;
  1885. /* Zoom Video Capture Volume + Switch */
  1886. for (z = 0; z < 2; z++) {
  1887. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z);
  1888. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1889. }
  1890. snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0);
  1891. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0);
  1892. gpr += 4;
  1893. }
  1894. if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) {
  1895. /* IEC958 Optical Playback Volume */
  1896. for (z = 0; z < 2; z++)
  1897. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z);
  1898. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0);
  1899. gpr += 2;
  1900. /* IEC958 Optical Capture Volume */
  1901. for (z = 0; z < 2; z++) {
  1902. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z);
  1903. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1904. }
  1905. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0);
  1906. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0);
  1907. gpr += 4;
  1908. }
  1909. if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) {
  1910. /* Line LiveDrive Playback Volume */
  1911. for (z = 0; z < 2; z++)
  1912. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z);
  1913. snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0);
  1914. gpr += 2;
  1915. /* Line LiveDrive Capture Volume + Switch */
  1916. for (z = 0; z < 2; z++) {
  1917. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z);
  1918. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1919. }
  1920. snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0);
  1921. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0);
  1922. gpr += 4;
  1923. }
  1924. if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) {
  1925. /* IEC958 Coax Playback Volume */
  1926. for (z = 0; z < 2; z++)
  1927. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z);
  1928. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0);
  1929. gpr += 2;
  1930. /* IEC958 Coax Capture Volume + Switch */
  1931. for (z = 0; z < 2; z++) {
  1932. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z);
  1933. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1934. }
  1935. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0);
  1936. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0);
  1937. gpr += 4;
  1938. }
  1939. if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) {
  1940. /* Line LiveDrive Playback Volume */
  1941. for (z = 0; z < 2; z++)
  1942. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z);
  1943. snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0);
  1944. controls[i-1].id.index = 1;
  1945. gpr += 2;
  1946. /* Line LiveDrive Capture Volume */
  1947. for (z = 0; z < 2; z++) {
  1948. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z);
  1949. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1950. }
  1951. snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0);
  1952. controls[i-1].id.index = 1;
  1953. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0);
  1954. controls[i-1].id.index = 1;
  1955. gpr += 4;
  1956. }
  1957. /*
  1958. * Process tone control
  1959. */
  1960. ctl = &controls[i + 0];
  1961. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1962. strcpy(ctl->id.name, "Tone Control - Bass");
  1963. ctl->vcount = 2;
  1964. ctl->count = 10;
  1965. ctl->min = 0;
  1966. ctl->max = 40;
  1967. ctl->value[0] = ctl->value[1] = 20;
  1968. ctl->tlv = snd_emu10k1_bass_treble_db_scale;
  1969. ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
  1970. ctl = &controls[i + 1];
  1971. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1972. strcpy(ctl->id.name, "Tone Control - Treble");
  1973. ctl->vcount = 2;
  1974. ctl->count = 10;
  1975. ctl->min = 0;
  1976. ctl->max = 40;
  1977. ctl->value[0] = ctl->value[1] = 20;
  1978. ctl->tlv = snd_emu10k1_bass_treble_db_scale;
  1979. ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
  1980. #define BASS_GPR 0x8c
  1981. #define TREBLE_GPR 0x96
  1982. for (z = 0; z < 5; z++) {
  1983. int j;
  1984. for (j = 0; j < 2; j++) {
  1985. controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
  1986. controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
  1987. }
  1988. }
  1989. i += 2;
  1990. OP(icode, &ptr, iACC3, C_00000000, GPR(gpr), C_00000000, C_00000000);
  1991. snd_emu10k1_init_mono_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0);
  1992. gpr++;
  1993. OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr));
  1994. ptr_skip = ptr;
  1995. for (z = 0; z < 3; z++) { /* front/rear/center-lfe */
  1996. int j, k, l, d;
  1997. for (j = 0; j < 2; j++) { /* left/right */
  1998. k = 0xa0 + (z * 8) + (j * 4);
  1999. l = 0xd0 + (z * 8) + (j * 4);
  2000. d = playback + z * 2 + j;
  2001. OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j));
  2002. OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));
  2003. OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));
  2004. OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));
  2005. OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));
  2006. OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);
  2007. OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));
  2008. OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j));
  2009. OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));
  2010. OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j));
  2011. OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j));
  2012. OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010);
  2013. OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000);
  2014. if (z == 2) /* center */
  2015. break;
  2016. }
  2017. }
  2018. gpr_map[gpr++] = ptr - ptr_skip;
  2019. #undef BASS_GPR
  2020. #undef TREBLE_GPR
  2021. /*
  2022. * Process outputs
  2023. */
  2024. if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) {
  2025. /* AC'97 Playback Volume */
  2026. for (z = 0; z < 2; z++)
  2027. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + z), C_00000000, C_00000000);
  2028. }
  2029. if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) {
  2030. /* IEC958 Optical Raw Playback Switch */
  2031. for (z = 0; z < 2; z++) {
  2032. SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z);
  2033. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
  2034. SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
  2035. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2036. #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
  2037. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2038. #endif
  2039. }
  2040. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
  2041. gpr += 2;
  2042. }
  2043. if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) {
  2044. /* Headphone Playback Volume */
  2045. for (z = 0; z < 2; z++) {
  2046. SWITCH(icode, &ptr, tmp + 0, playback + 4 + z, gpr + 2 + z);
  2047. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z);
  2048. SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
  2049. OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2050. VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z);
  2051. }
  2052. snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0);
  2053. controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */
  2054. snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0);
  2055. controls[i-1].id.index = 1;
  2056. snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0);
  2057. controls[i-1].id.index = 1;
  2058. gpr += 4;
  2059. }
  2060. if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R)))
  2061. for (z = 0; z < 2; z++)
  2062. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000);
  2063. if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R)))
  2064. for (z = 0; z < 2; z++)
  2065. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000);
  2066. if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) {
  2067. #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
  2068. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 4), C_00000000, C_00000000);
  2069. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 4), C_00000000, C_00000000);
  2070. #else
  2071. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 0), C_00000000, C_00000000);
  2072. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 0), C_00000000, C_00000000);
  2073. #endif
  2074. }
  2075. if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) {
  2076. #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
  2077. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 5), C_00000000, C_00000000);
  2078. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 5), C_00000000, C_00000000);
  2079. #else
  2080. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 1), C_00000000, C_00000000);
  2081. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 1), C_00000000, C_00000000);
  2082. #endif
  2083. }
  2084. #ifndef EMU10K1_CAPTURE_DIGITAL_OUT
  2085. for (z = 0; z < 2; z++)
  2086. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000);
  2087. #endif
  2088. if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP))
  2089. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000);
  2090. /* EFX capture - capture the 16 EXTINS */
  2091. if (emu->card_capabilities->sblive51) {
  2092. for (z = 0; z < 16; z++) {
  2093. s8 c = snd_emu10k1_sblive51_fxbus2_map[z];
  2094. if (c != -1)
  2095. OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(c));
  2096. }
  2097. } else {
  2098. for (z = 0; z < 16; z++)
  2099. OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
  2100. }
  2101. if (gpr > tmp) {
  2102. snd_BUG();
  2103. err = -EIO;
  2104. goto __err;
  2105. }
  2106. if (i > SND_EMU10K1_GPR_CONTROLS) {
  2107. snd_BUG();
  2108. err = -EIO;
  2109. goto __err;
  2110. }
  2111. /* clear remaining instruction memory */
  2112. while (ptr < 0x200)
  2113. OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000);
  2114. err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size);
  2115. if (err < 0)
  2116. goto __err;
  2117. icode->gpr_add_control_count = i;
  2118. icode->gpr_add_controls = controls;
  2119. emu->support_tlv = 1; /* support TLV */
  2120. err = snd_emu10k1_icode_poke(emu, icode, true);
  2121. emu->support_tlv = 0; /* clear again */
  2122. if (err >= 0)
  2123. err = snd_emu10k1_ipcm_poke(emu, ipcm);
  2124. __err:
  2125. kfree(ipcm);
  2126. __err_ipcm:
  2127. kfree(controls);
  2128. __err_ctrls:
  2129. kfree(icode->gpr_map);
  2130. __err_gpr:
  2131. kfree(icode);
  2132. return err;
  2133. }
  2134. int snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
  2135. {
  2136. spin_lock_init(&emu->fx8010.irq_lock);
  2137. INIT_LIST_HEAD(&emu->fx8010.gpr_ctl);
  2138. if (emu->audigy)
  2139. return _snd_emu10k1_audigy_init_efx(emu);
  2140. else
  2141. return _snd_emu10k1_init_efx(emu);
  2142. }
  2143. void snd_emu10k1_free_efx(struct snd_emu10k1 *emu)
  2144. {
  2145. /* stop processor */
  2146. if (emu->audigy)
  2147. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP);
  2148. else
  2149. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP);
  2150. }
  2151. #if 0 /* FIXME: who use them? */
  2152. int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output)
  2153. {
  2154. if (output < 0 || output >= 6)
  2155. return -EINVAL;
  2156. snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1);
  2157. return 0;
  2158. }
  2159. int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output)
  2160. {
  2161. if (output < 0 || output >= 6)
  2162. return -EINVAL;
  2163. snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0);
  2164. return 0;
  2165. }
  2166. #endif
  2167. int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size)
  2168. {
  2169. u8 size_reg = 0;
  2170. /* size is in samples */
  2171. if (size != 0) {
  2172. size = (size - 1) >> 13;
  2173. while (size) {
  2174. size >>= 1;
  2175. size_reg++;
  2176. }
  2177. size = 0x2000 << size_reg;
  2178. }
  2179. if ((emu->fx8010.etram_pages.bytes / 2) == size)
  2180. return 0;
  2181. spin_lock_irq(&emu->emu_lock);
  2182. outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
  2183. spin_unlock_irq(&emu->emu_lock);
  2184. snd_emu10k1_ptr_write(emu, TCB, 0, 0);
  2185. snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
  2186. if (emu->fx8010.etram_pages.area != NULL) {
  2187. snd_dma_free_pages(&emu->fx8010.etram_pages);
  2188. emu->fx8010.etram_pages.area = NULL;
  2189. emu->fx8010.etram_pages.bytes = 0;
  2190. }
  2191. if (size > 0) {
  2192. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &emu->pci->dev,
  2193. size * 2, &emu->fx8010.etram_pages) < 0)
  2194. return -ENOMEM;
  2195. memset(emu->fx8010.etram_pages.area, 0, size * 2);
  2196. snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
  2197. snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
  2198. spin_lock_irq(&emu->emu_lock);
  2199. outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
  2200. spin_unlock_irq(&emu->emu_lock);
  2201. }
  2202. return 0;
  2203. }
  2204. static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file)
  2205. {
  2206. return 0;
  2207. }
  2208. static void copy_string(char *dst, const char *src, const char *null, int idx)
  2209. {
  2210. if (src == NULL)
  2211. sprintf(dst, "%s %02X", null, idx);
  2212. else
  2213. strcpy(dst, src);
  2214. }
  2215. static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu,
  2216. struct snd_emu10k1_fx8010_info *info)
  2217. {
  2218. const char * const *fxbus, * const *extin, * const *extout;
  2219. unsigned short extin_mask, extout_mask;
  2220. int res;
  2221. info->internal_tram_size = emu->fx8010.itram_size;
  2222. info->external_tram_size = emu->fx8010.etram_pages.bytes / 2;
  2223. fxbus = snd_emu10k1_fxbus;
  2224. extin = emu->audigy ? snd_emu10k1_audigy_ins : snd_emu10k1_sblive_ins;
  2225. extout = emu->audigy ? snd_emu10k1_audigy_outs : snd_emu10k1_sblive_outs;
  2226. extin_mask = emu->audigy ? ~0 : emu->fx8010.extin_mask;
  2227. extout_mask = emu->audigy ? ~0 : emu->fx8010.extout_mask;
  2228. for (res = 0; res < 16; res++, fxbus++, extin++, extout++) {
  2229. copy_string(info->fxbus_names[res], *fxbus, "FXBUS", res);
  2230. copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res);
  2231. copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
  2232. }
  2233. for (res = 16; res < 32; res++, extout++)
  2234. copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
  2235. info->gpr_controls = emu->fx8010.gpr_count;
  2236. }
  2237. static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg)
  2238. {
  2239. struct snd_emu10k1 *emu = hw->private_data;
  2240. struct snd_emu10k1_fx8010_info *info;
  2241. struct snd_emu10k1_fx8010_code *icode;
  2242. struct snd_emu10k1_fx8010_pcm_rec *ipcm;
  2243. unsigned int addr;
  2244. void __user *argp = (void __user *)arg;
  2245. int res;
  2246. switch (cmd) {
  2247. case SNDRV_EMU10K1_IOCTL_PVERSION:
  2248. emu->support_tlv = 1;
  2249. return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp);
  2250. case SNDRV_EMU10K1_IOCTL_INFO:
  2251. info = kzalloc(sizeof(*info), GFP_KERNEL);
  2252. if (!info)
  2253. return -ENOMEM;
  2254. snd_emu10k1_fx8010_info(emu, info);
  2255. if (copy_to_user(argp, info, sizeof(*info))) {
  2256. kfree(info);
  2257. return -EFAULT;
  2258. }
  2259. kfree(info);
  2260. return 0;
  2261. case SNDRV_EMU10K1_IOCTL_CODE_POKE:
  2262. if (!capable(CAP_SYS_ADMIN))
  2263. return -EPERM;
  2264. icode = memdup_user(argp, sizeof(*icode));
  2265. if (IS_ERR(icode))
  2266. return PTR_ERR(icode);
  2267. res = snd_emu10k1_icode_poke(emu, icode, false);
  2268. kfree(icode);
  2269. return res;
  2270. case SNDRV_EMU10K1_IOCTL_CODE_PEEK:
  2271. icode = memdup_user(argp, sizeof(*icode));
  2272. if (IS_ERR(icode))
  2273. return PTR_ERR(icode);
  2274. res = snd_emu10k1_icode_peek(emu, icode);
  2275. if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) {
  2276. kfree(icode);
  2277. return -EFAULT;
  2278. }
  2279. kfree(icode);
  2280. return res;
  2281. case SNDRV_EMU10K1_IOCTL_PCM_POKE:
  2282. ipcm = memdup_user(argp, sizeof(*ipcm));
  2283. if (IS_ERR(ipcm))
  2284. return PTR_ERR(ipcm);
  2285. res = snd_emu10k1_ipcm_poke(emu, ipcm);
  2286. kfree(ipcm);
  2287. return res;
  2288. case SNDRV_EMU10K1_IOCTL_PCM_PEEK:
  2289. ipcm = memdup_user(argp, sizeof(*ipcm));
  2290. if (IS_ERR(ipcm))
  2291. return PTR_ERR(ipcm);
  2292. res = snd_emu10k1_ipcm_peek(emu, ipcm);
  2293. if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) {
  2294. kfree(ipcm);
  2295. return -EFAULT;
  2296. }
  2297. kfree(ipcm);
  2298. return res;
  2299. case SNDRV_EMU10K1_IOCTL_TRAM_SETUP:
  2300. if (!capable(CAP_SYS_ADMIN))
  2301. return -EPERM;
  2302. if (get_user(addr, (unsigned int __user *)argp))
  2303. return -EFAULT;
  2304. mutex_lock(&emu->fx8010.lock);
  2305. res = snd_emu10k1_fx8010_tram_setup(emu, addr);
  2306. mutex_unlock(&emu->fx8010.lock);
  2307. return res;
  2308. case SNDRV_EMU10K1_IOCTL_STOP:
  2309. if (!capable(CAP_SYS_ADMIN))
  2310. return -EPERM;
  2311. if (emu->audigy)
  2312. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
  2313. else
  2314. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
  2315. return 0;
  2316. case SNDRV_EMU10K1_IOCTL_CONTINUE:
  2317. if (!capable(CAP_SYS_ADMIN))
  2318. return -EPERM;
  2319. if (emu->audigy)
  2320. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0);
  2321. else
  2322. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0);
  2323. return 0;
  2324. case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER:
  2325. if (!capable(CAP_SYS_ADMIN))
  2326. return -EPERM;
  2327. if (emu->audigy)
  2328. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC);
  2329. else
  2330. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC);
  2331. udelay(10);
  2332. if (emu->audigy)
  2333. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  2334. else
  2335. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  2336. return 0;
  2337. case SNDRV_EMU10K1_IOCTL_SINGLE_STEP:
  2338. if (!capable(CAP_SYS_ADMIN))
  2339. return -EPERM;
  2340. if (get_user(addr, (unsigned int __user *)argp))
  2341. return -EFAULT;
  2342. if (emu->audigy) {
  2343. if (addr > A_DBG_STEP_ADDR)
  2344. return -EINVAL;
  2345. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
  2346. udelay(10);
  2347. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_STEP | addr);
  2348. } else {
  2349. if (addr > EMU10K1_DBG_SINGLE_STEP_ADDR)
  2350. return -EINVAL;
  2351. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
  2352. udelay(10);
  2353. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_STEP | addr);
  2354. }
  2355. return 0;
  2356. case SNDRV_EMU10K1_IOCTL_DBG_READ:
  2357. if (emu->audigy)
  2358. addr = snd_emu10k1_ptr_read(emu, A_DBG, 0);
  2359. else
  2360. addr = snd_emu10k1_ptr_read(emu, DBG, 0);
  2361. if (put_user(addr, (unsigned int __user *)argp))
  2362. return -EFAULT;
  2363. return 0;
  2364. }
  2365. return -ENOTTY;
  2366. }
  2367. static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file)
  2368. {
  2369. return 0;
  2370. }
  2371. int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device)
  2372. {
  2373. struct snd_hwdep *hw;
  2374. int err;
  2375. err = snd_hwdep_new(emu->card, "FX8010", device, &hw);
  2376. if (err < 0)
  2377. return err;
  2378. strcpy(hw->name, "EMU10K1 (FX8010)");
  2379. hw->iface = SNDRV_HWDEP_IFACE_EMU10K1;
  2380. hw->ops.open = snd_emu10k1_fx8010_open;
  2381. hw->ops.ioctl = snd_emu10k1_fx8010_ioctl;
  2382. hw->ops.release = snd_emu10k1_fx8010_release;
  2383. hw->private_data = emu;
  2384. return 0;
  2385. }
  2386. #ifdef CONFIG_PM_SLEEP
  2387. int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu)
  2388. {
  2389. int len;
  2390. len = emu->audigy ? 0x200 : 0x100;
  2391. emu->saved_gpr = kmalloc_array(len, 4, GFP_KERNEL);
  2392. if (! emu->saved_gpr)
  2393. return -ENOMEM;
  2394. len = emu->audigy ? 0x100 : 0xa0;
  2395. emu->tram_val_saved = kmalloc_array(len, 4, GFP_KERNEL);
  2396. emu->tram_addr_saved = kmalloc_array(len, 4, GFP_KERNEL);
  2397. if (! emu->tram_val_saved || ! emu->tram_addr_saved)
  2398. return -ENOMEM;
  2399. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2400. emu->saved_icode = vmalloc(array_size(len, 4));
  2401. if (! emu->saved_icode)
  2402. return -ENOMEM;
  2403. return 0;
  2404. }
  2405. void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu)
  2406. {
  2407. kfree(emu->saved_gpr);
  2408. kfree(emu->tram_val_saved);
  2409. kfree(emu->tram_addr_saved);
  2410. vfree(emu->saved_icode);
  2411. }
  2412. /*
  2413. * save/restore GPR, TRAM and codes
  2414. */
  2415. void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu)
  2416. {
  2417. int i, len;
  2418. len = emu->audigy ? 0x200 : 0x100;
  2419. for (i = 0; i < len; i++)
  2420. emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0);
  2421. len = emu->audigy ? 0x100 : 0xa0;
  2422. for (i = 0; i < len; i++) {
  2423. emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0);
  2424. emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0);
  2425. if (emu->audigy) {
  2426. emu->tram_addr_saved[i] >>= 12;
  2427. emu->tram_addr_saved[i] |=
  2428. snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20;
  2429. }
  2430. }
  2431. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2432. for (i = 0; i < len; i++)
  2433. emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i);
  2434. }
  2435. void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu)
  2436. {
  2437. int i, len;
  2438. /* set up TRAM */
  2439. if (emu->fx8010.etram_pages.bytes > 0) {
  2440. unsigned size, size_reg = 0;
  2441. size = emu->fx8010.etram_pages.bytes / 2;
  2442. size = (size - 1) >> 13;
  2443. while (size) {
  2444. size >>= 1;
  2445. size_reg++;
  2446. }
  2447. outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
  2448. snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
  2449. snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
  2450. outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
  2451. }
  2452. if (emu->audigy)
  2453. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
  2454. else
  2455. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
  2456. len = emu->audigy ? 0x200 : 0x100;
  2457. for (i = 0; i < len; i++)
  2458. snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]);
  2459. len = emu->audigy ? 0x100 : 0xa0;
  2460. for (i = 0; i < len; i++) {
  2461. snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0,
  2462. emu->tram_val_saved[i]);
  2463. if (! emu->audigy)
  2464. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2465. emu->tram_addr_saved[i]);
  2466. else {
  2467. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2468. emu->tram_addr_saved[i] << 12);
  2469. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2470. emu->tram_addr_saved[i] >> 20);
  2471. }
  2472. }
  2473. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2474. for (i = 0; i < len; i++)
  2475. snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]);
  2476. /* start FX processor when the DSP code is updated */
  2477. if (emu->audigy)
  2478. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  2479. else
  2480. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  2481. }
  2482. #endif