nm256.c 42 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for NeoMagic 256AV and 256ZX chipsets.
  4. * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
  5. *
  6. * Based on nm256_audio.c OSS driver in linux kernel.
  7. * The original author of OSS nm256 driver wishes to remain anonymous,
  8. * so I just put my acknoledgment to him/her here.
  9. * The original author's web page is found at
  10. * http://www.uglx.org/sony.html
  11. */
  12. #include <linux/io.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/init.h>
  16. #include <linux/pci.h>
  17. #include <linux/slab.h>
  18. #include <linux/module.h>
  19. #include <linux/mutex.h>
  20. #include <sound/core.h>
  21. #include <sound/info.h>
  22. #include <sound/control.h>
  23. #include <sound/pcm.h>
  24. #include <sound/ac97_codec.h>
  25. #include <sound/initval.h>
  26. #define CARD_NAME "NeoMagic 256AV/ZX"
  27. #define DRIVER_NAME "NM256"
  28. MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
  29. MODULE_DESCRIPTION("NeoMagic NM256AV/ZX");
  30. MODULE_LICENSE("GPL");
  31. /*
  32. * some compile conditions.
  33. */
  34. static int index = SNDRV_DEFAULT_IDX1; /* Index */
  35. static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
  36. static int playback_bufsize = 16;
  37. static int capture_bufsize = 16;
  38. static bool force_ac97; /* disabled as default */
  39. static int buffer_top; /* not specified */
  40. static bool use_cache; /* disabled */
  41. static bool vaio_hack; /* disabled */
  42. static bool reset_workaround;
  43. static bool reset_workaround_2;
  44. module_param(index, int, 0444);
  45. MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  46. module_param(id, charp, 0444);
  47. MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  48. module_param(playback_bufsize, int, 0444);
  49. MODULE_PARM_DESC(playback_bufsize, "DAC frame size in kB for " CARD_NAME " soundcard.");
  50. module_param(capture_bufsize, int, 0444);
  51. MODULE_PARM_DESC(capture_bufsize, "ADC frame size in kB for " CARD_NAME " soundcard.");
  52. module_param(force_ac97, bool, 0444);
  53. MODULE_PARM_DESC(force_ac97, "Force to use AC97 codec for " CARD_NAME " soundcard.");
  54. module_param(buffer_top, int, 0444);
  55. MODULE_PARM_DESC(buffer_top, "Set the top address of audio buffer for " CARD_NAME " soundcard.");
  56. module_param(use_cache, bool, 0444);
  57. MODULE_PARM_DESC(use_cache, "Enable the cache for coefficient table access.");
  58. module_param(vaio_hack, bool, 0444);
  59. MODULE_PARM_DESC(vaio_hack, "Enable workaround for Sony VAIO notebooks.");
  60. module_param(reset_workaround, bool, 0444);
  61. MODULE_PARM_DESC(reset_workaround, "Enable AC97 RESET workaround for some laptops.");
  62. module_param(reset_workaround_2, bool, 0444);
  63. MODULE_PARM_DESC(reset_workaround_2, "Enable extended AC97 RESET workaround for some other laptops.");
  64. /* just for backward compatibility */
  65. static bool enable;
  66. module_param(enable, bool, 0444);
  67. /*
  68. * hw definitions
  69. */
  70. /* The BIOS signature. */
  71. #define NM_SIGNATURE 0x4e4d0000
  72. /* Signature mask. */
  73. #define NM_SIG_MASK 0xffff0000
  74. /* Size of the second memory area. */
  75. #define NM_PORT2_SIZE 4096
  76. /* The base offset of the mixer in the second memory area. */
  77. #define NM_MIXER_OFFSET 0x600
  78. /* The maximum size of a coefficient entry. */
  79. #define NM_MAX_PLAYBACK_COEF_SIZE 0x5000
  80. #define NM_MAX_RECORD_COEF_SIZE 0x1260
  81. /* The interrupt register. */
  82. #define NM_INT_REG 0xa04
  83. /* And its bits. */
  84. #define NM_PLAYBACK_INT 0x40
  85. #define NM_RECORD_INT 0x100
  86. #define NM_MISC_INT_1 0x4000
  87. #define NM_MISC_INT_2 0x1
  88. #define NM_ACK_INT(chip, X) snd_nm256_writew(chip, NM_INT_REG, (X) << 1)
  89. /* The AV's "mixer ready" status bit and location. */
  90. #define NM_MIXER_STATUS_OFFSET 0xa04
  91. #define NM_MIXER_READY_MASK 0x0800
  92. #define NM_MIXER_PRESENCE 0xa06
  93. #define NM_PRESENCE_MASK 0x0050
  94. #define NM_PRESENCE_VALUE 0x0040
  95. /*
  96. * For the ZX. It uses the same interrupt register, but it holds 32
  97. * bits instead of 16.
  98. */
  99. #define NM2_PLAYBACK_INT 0x10000
  100. #define NM2_RECORD_INT 0x80000
  101. #define NM2_MISC_INT_1 0x8
  102. #define NM2_MISC_INT_2 0x2
  103. #define NM2_ACK_INT(chip, X) snd_nm256_writel(chip, NM_INT_REG, (X))
  104. /* The ZX's "mixer ready" status bit and location. */
  105. #define NM2_MIXER_STATUS_OFFSET 0xa06
  106. #define NM2_MIXER_READY_MASK 0x0800
  107. /* The playback registers start from here. */
  108. #define NM_PLAYBACK_REG_OFFSET 0x0
  109. /* The record registers start from here. */
  110. #define NM_RECORD_REG_OFFSET 0x200
  111. /* The rate register is located 2 bytes from the start of the register area. */
  112. #define NM_RATE_REG_OFFSET 2
  113. /* Mono/stereo flag, number of bits on playback, and rate mask. */
  114. #define NM_RATE_STEREO 1
  115. #define NM_RATE_BITS_16 2
  116. #define NM_RATE_MASK 0xf0
  117. /* Playback enable register. */
  118. #define NM_PLAYBACK_ENABLE_REG (NM_PLAYBACK_REG_OFFSET + 0x1)
  119. #define NM_PLAYBACK_ENABLE_FLAG 1
  120. #define NM_PLAYBACK_ONESHOT 2
  121. #define NM_PLAYBACK_FREERUN 4
  122. /* Mutes the audio output. */
  123. #define NM_AUDIO_MUTE_REG (NM_PLAYBACK_REG_OFFSET + 0x18)
  124. #define NM_AUDIO_MUTE_LEFT 0x8000
  125. #define NM_AUDIO_MUTE_RIGHT 0x0080
  126. /* Recording enable register. */
  127. #define NM_RECORD_ENABLE_REG (NM_RECORD_REG_OFFSET + 0)
  128. #define NM_RECORD_ENABLE_FLAG 1
  129. #define NM_RECORD_FREERUN 2
  130. /* coefficient buffer pointer */
  131. #define NM_COEFF_START_OFFSET 0x1c
  132. #define NM_COEFF_END_OFFSET 0x20
  133. /* DMA buffer offsets */
  134. #define NM_RBUFFER_START (NM_RECORD_REG_OFFSET + 0x4)
  135. #define NM_RBUFFER_END (NM_RECORD_REG_OFFSET + 0x10)
  136. #define NM_RBUFFER_WMARK (NM_RECORD_REG_OFFSET + 0xc)
  137. #define NM_RBUFFER_CURRP (NM_RECORD_REG_OFFSET + 0x8)
  138. #define NM_PBUFFER_START (NM_PLAYBACK_REG_OFFSET + 0x4)
  139. #define NM_PBUFFER_END (NM_PLAYBACK_REG_OFFSET + 0x14)
  140. #define NM_PBUFFER_WMARK (NM_PLAYBACK_REG_OFFSET + 0xc)
  141. #define NM_PBUFFER_CURRP (NM_PLAYBACK_REG_OFFSET + 0x8)
  142. struct nm256_stream {
  143. struct nm256 *chip;
  144. struct snd_pcm_substream *substream;
  145. int running;
  146. int suspended;
  147. u32 buf; /* offset from chip->buffer */
  148. int bufsize; /* buffer size in bytes */
  149. void __iomem *bufptr; /* mapped pointer */
  150. unsigned long bufptr_addr; /* physical address of the mapped pointer */
  151. int dma_size; /* buffer size of the substream in bytes */
  152. int period_size; /* period size in bytes */
  153. int periods; /* # of periods */
  154. int shift; /* bit shifts */
  155. int cur_period; /* current period # */
  156. };
  157. struct nm256 {
  158. struct snd_card *card;
  159. void __iomem *cport; /* control port */
  160. unsigned long cport_addr; /* physical address */
  161. void __iomem *buffer; /* buffer */
  162. unsigned long buffer_addr; /* buffer phyiscal address */
  163. u32 buffer_start; /* start offset from pci resource 0 */
  164. u32 buffer_end; /* end offset */
  165. u32 buffer_size; /* total buffer size */
  166. u32 all_coeff_buf; /* coefficient buffer */
  167. u32 coeff_buf[2]; /* coefficient buffer for each stream */
  168. unsigned int coeffs_current: 1; /* coeff. table is loaded? */
  169. unsigned int use_cache: 1; /* use one big coef. table */
  170. unsigned int reset_workaround: 1; /* Workaround for some laptops to avoid freeze */
  171. unsigned int reset_workaround_2: 1; /* Extended workaround for some other laptops to avoid freeze */
  172. unsigned int in_resume: 1;
  173. int mixer_base; /* register offset of ac97 mixer */
  174. int mixer_status_offset; /* offset of mixer status reg. */
  175. int mixer_status_mask; /* bit mask to test the mixer status */
  176. int irq;
  177. int irq_acks;
  178. irq_handler_t interrupt;
  179. int badintrcount; /* counter to check bogus interrupts */
  180. struct mutex irq_mutex;
  181. struct nm256_stream streams[2];
  182. struct snd_ac97 *ac97;
  183. unsigned short *ac97_regs; /* register caches, only for valid regs */
  184. struct snd_pcm *pcm;
  185. struct pci_dev *pci;
  186. spinlock_t reg_lock;
  187. };
  188. /*
  189. * include coefficient table
  190. */
  191. #include "nm256_coef.c"
  192. /*
  193. * PCI ids
  194. */
  195. static const struct pci_device_id snd_nm256_ids[] = {
  196. {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO), 0},
  197. {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO), 0},
  198. {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO), 0},
  199. {0,},
  200. };
  201. MODULE_DEVICE_TABLE(pci, snd_nm256_ids);
  202. /*
  203. * lowlvel stuffs
  204. */
  205. static inline u8
  206. snd_nm256_readb(struct nm256 *chip, int offset)
  207. {
  208. return readb(chip->cport + offset);
  209. }
  210. static inline u16
  211. snd_nm256_readw(struct nm256 *chip, int offset)
  212. {
  213. return readw(chip->cport + offset);
  214. }
  215. static inline u32
  216. snd_nm256_readl(struct nm256 *chip, int offset)
  217. {
  218. return readl(chip->cport + offset);
  219. }
  220. static inline void
  221. snd_nm256_writeb(struct nm256 *chip, int offset, u8 val)
  222. {
  223. writeb(val, chip->cport + offset);
  224. }
  225. static inline void
  226. snd_nm256_writew(struct nm256 *chip, int offset, u16 val)
  227. {
  228. writew(val, chip->cport + offset);
  229. }
  230. static inline void
  231. snd_nm256_writel(struct nm256 *chip, int offset, u32 val)
  232. {
  233. writel(val, chip->cport + offset);
  234. }
  235. static inline void
  236. snd_nm256_write_buffer(struct nm256 *chip, const void *src, int offset, int size)
  237. {
  238. offset -= chip->buffer_start;
  239. #ifdef CONFIG_SND_DEBUG
  240. if (offset < 0 || offset >= chip->buffer_size) {
  241. dev_err(chip->card->dev,
  242. "write_buffer invalid offset = %d size = %d\n",
  243. offset, size);
  244. return;
  245. }
  246. #endif
  247. memcpy_toio(chip->buffer + offset, src, size);
  248. }
  249. /*
  250. * coefficient handlers -- what a magic!
  251. */
  252. static u16
  253. snd_nm256_get_start_offset(int which)
  254. {
  255. u16 offset = 0;
  256. while (which-- > 0)
  257. offset += coefficient_sizes[which];
  258. return offset;
  259. }
  260. static void
  261. snd_nm256_load_one_coefficient(struct nm256 *chip, int stream, u32 port, int which)
  262. {
  263. u32 coeff_buf = chip->coeff_buf[stream];
  264. u16 offset = snd_nm256_get_start_offset(which);
  265. u16 size = coefficient_sizes[which];
  266. snd_nm256_write_buffer(chip, coefficients + offset, coeff_buf, size);
  267. snd_nm256_writel(chip, port, coeff_buf);
  268. /* ??? Record seems to behave differently than playback. */
  269. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  270. size--;
  271. snd_nm256_writel(chip, port + 4, coeff_buf + size);
  272. }
  273. static void
  274. snd_nm256_load_coefficient(struct nm256 *chip, int stream, int number)
  275. {
  276. /* The enable register for the specified engine. */
  277. u32 poffset = (stream == SNDRV_PCM_STREAM_CAPTURE ?
  278. NM_RECORD_ENABLE_REG : NM_PLAYBACK_ENABLE_REG);
  279. u32 addr = NM_COEFF_START_OFFSET;
  280. addr += (stream == SNDRV_PCM_STREAM_CAPTURE ?
  281. NM_RECORD_REG_OFFSET : NM_PLAYBACK_REG_OFFSET);
  282. if (snd_nm256_readb(chip, poffset) & 1) {
  283. dev_dbg(chip->card->dev,
  284. "NM256: Engine was enabled while loading coefficients!\n");
  285. return;
  286. }
  287. /* The recording engine uses coefficient values 8-15. */
  288. number &= 7;
  289. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  290. number += 8;
  291. if (! chip->use_cache) {
  292. snd_nm256_load_one_coefficient(chip, stream, addr, number);
  293. return;
  294. }
  295. if (! chip->coeffs_current) {
  296. snd_nm256_write_buffer(chip, coefficients, chip->all_coeff_buf,
  297. NM_TOTAL_COEFF_COUNT * 4);
  298. chip->coeffs_current = 1;
  299. } else {
  300. u32 base = chip->all_coeff_buf;
  301. u32 offset = snd_nm256_get_start_offset(number);
  302. u32 end_offset = offset + coefficient_sizes[number];
  303. snd_nm256_writel(chip, addr, base + offset);
  304. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  305. end_offset--;
  306. snd_nm256_writel(chip, addr + 4, base + end_offset);
  307. }
  308. }
  309. /* The actual rates supported by the card. */
  310. static const unsigned int samplerates[8] = {
  311. 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
  312. };
  313. static const struct snd_pcm_hw_constraint_list constraints_rates = {
  314. .count = ARRAY_SIZE(samplerates),
  315. .list = samplerates,
  316. .mask = 0,
  317. };
  318. /*
  319. * return the index of the target rate
  320. */
  321. static int
  322. snd_nm256_fixed_rate(unsigned int rate)
  323. {
  324. unsigned int i;
  325. for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
  326. if (rate == samplerates[i])
  327. return i;
  328. }
  329. snd_BUG();
  330. return 0;
  331. }
  332. /*
  333. * set sample rate and format
  334. */
  335. static void
  336. snd_nm256_set_format(struct nm256 *chip, struct nm256_stream *s,
  337. struct snd_pcm_substream *substream)
  338. {
  339. struct snd_pcm_runtime *runtime = substream->runtime;
  340. int rate_index = snd_nm256_fixed_rate(runtime->rate);
  341. unsigned char ratebits = (rate_index << 4) & NM_RATE_MASK;
  342. s->shift = 0;
  343. if (snd_pcm_format_width(runtime->format) == 16) {
  344. ratebits |= NM_RATE_BITS_16;
  345. s->shift++;
  346. }
  347. if (runtime->channels > 1) {
  348. ratebits |= NM_RATE_STEREO;
  349. s->shift++;
  350. }
  351. runtime->rate = samplerates[rate_index];
  352. switch (substream->stream) {
  353. case SNDRV_PCM_STREAM_PLAYBACK:
  354. snd_nm256_load_coefficient(chip, 0, rate_index); /* 0 = playback */
  355. snd_nm256_writeb(chip,
  356. NM_PLAYBACK_REG_OFFSET + NM_RATE_REG_OFFSET,
  357. ratebits);
  358. break;
  359. case SNDRV_PCM_STREAM_CAPTURE:
  360. snd_nm256_load_coefficient(chip, 1, rate_index); /* 1 = record */
  361. snd_nm256_writeb(chip,
  362. NM_RECORD_REG_OFFSET + NM_RATE_REG_OFFSET,
  363. ratebits);
  364. break;
  365. }
  366. }
  367. /* acquire interrupt */
  368. static int snd_nm256_acquire_irq(struct nm256 *chip)
  369. {
  370. mutex_lock(&chip->irq_mutex);
  371. if (chip->irq < 0) {
  372. if (request_irq(chip->pci->irq, chip->interrupt, IRQF_SHARED,
  373. KBUILD_MODNAME, chip)) {
  374. dev_err(chip->card->dev,
  375. "unable to grab IRQ %d\n", chip->pci->irq);
  376. mutex_unlock(&chip->irq_mutex);
  377. return -EBUSY;
  378. }
  379. chip->irq = chip->pci->irq;
  380. chip->card->sync_irq = chip->irq;
  381. }
  382. chip->irq_acks++;
  383. mutex_unlock(&chip->irq_mutex);
  384. return 0;
  385. }
  386. /* release interrupt */
  387. static void snd_nm256_release_irq(struct nm256 *chip)
  388. {
  389. mutex_lock(&chip->irq_mutex);
  390. if (chip->irq_acks > 0)
  391. chip->irq_acks--;
  392. if (chip->irq_acks == 0 && chip->irq >= 0) {
  393. free_irq(chip->irq, chip);
  394. chip->irq = -1;
  395. chip->card->sync_irq = -1;
  396. }
  397. mutex_unlock(&chip->irq_mutex);
  398. }
  399. /*
  400. * start / stop
  401. */
  402. /* update the watermark (current period) */
  403. static void snd_nm256_pcm_mark(struct nm256 *chip, struct nm256_stream *s, int reg)
  404. {
  405. s->cur_period++;
  406. s->cur_period %= s->periods;
  407. snd_nm256_writel(chip, reg, s->buf + s->cur_period * s->period_size);
  408. }
  409. #define snd_nm256_playback_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_PBUFFER_WMARK)
  410. #define snd_nm256_capture_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_RBUFFER_WMARK)
  411. static void
  412. snd_nm256_playback_start(struct nm256 *chip, struct nm256_stream *s,
  413. struct snd_pcm_substream *substream)
  414. {
  415. /* program buffer pointers */
  416. snd_nm256_writel(chip, NM_PBUFFER_START, s->buf);
  417. snd_nm256_writel(chip, NM_PBUFFER_END, s->buf + s->dma_size - (1 << s->shift));
  418. snd_nm256_writel(chip, NM_PBUFFER_CURRP, s->buf);
  419. snd_nm256_playback_mark(chip, s);
  420. /* Enable playback engine and interrupts. */
  421. snd_nm256_writeb(chip, NM_PLAYBACK_ENABLE_REG,
  422. NM_PLAYBACK_ENABLE_FLAG | NM_PLAYBACK_FREERUN);
  423. /* Enable both channels. */
  424. snd_nm256_writew(chip, NM_AUDIO_MUTE_REG, 0x0);
  425. }
  426. static void
  427. snd_nm256_capture_start(struct nm256 *chip, struct nm256_stream *s,
  428. struct snd_pcm_substream *substream)
  429. {
  430. /* program buffer pointers */
  431. snd_nm256_writel(chip, NM_RBUFFER_START, s->buf);
  432. snd_nm256_writel(chip, NM_RBUFFER_END, s->buf + s->dma_size);
  433. snd_nm256_writel(chip, NM_RBUFFER_CURRP, s->buf);
  434. snd_nm256_capture_mark(chip, s);
  435. /* Enable playback engine and interrupts. */
  436. snd_nm256_writeb(chip, NM_RECORD_ENABLE_REG,
  437. NM_RECORD_ENABLE_FLAG | NM_RECORD_FREERUN);
  438. }
  439. /* Stop the play engine. */
  440. static void
  441. snd_nm256_playback_stop(struct nm256 *chip)
  442. {
  443. /* Shut off sound from both channels. */
  444. snd_nm256_writew(chip, NM_AUDIO_MUTE_REG,
  445. NM_AUDIO_MUTE_LEFT | NM_AUDIO_MUTE_RIGHT);
  446. /* Disable play engine. */
  447. snd_nm256_writeb(chip, NM_PLAYBACK_ENABLE_REG, 0);
  448. }
  449. static void
  450. snd_nm256_capture_stop(struct nm256 *chip)
  451. {
  452. /* Disable recording engine. */
  453. snd_nm256_writeb(chip, NM_RECORD_ENABLE_REG, 0);
  454. }
  455. static int
  456. snd_nm256_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  457. {
  458. struct nm256 *chip = snd_pcm_substream_chip(substream);
  459. struct nm256_stream *s = substream->runtime->private_data;
  460. int err = 0;
  461. if (snd_BUG_ON(!s))
  462. return -ENXIO;
  463. spin_lock(&chip->reg_lock);
  464. switch (cmd) {
  465. case SNDRV_PCM_TRIGGER_RESUME:
  466. s->suspended = 0;
  467. fallthrough;
  468. case SNDRV_PCM_TRIGGER_START:
  469. if (! s->running) {
  470. snd_nm256_playback_start(chip, s, substream);
  471. s->running = 1;
  472. }
  473. break;
  474. case SNDRV_PCM_TRIGGER_SUSPEND:
  475. s->suspended = 1;
  476. fallthrough;
  477. case SNDRV_PCM_TRIGGER_STOP:
  478. if (s->running) {
  479. snd_nm256_playback_stop(chip);
  480. s->running = 0;
  481. }
  482. break;
  483. default:
  484. err = -EINVAL;
  485. break;
  486. }
  487. spin_unlock(&chip->reg_lock);
  488. return err;
  489. }
  490. static int
  491. snd_nm256_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  492. {
  493. struct nm256 *chip = snd_pcm_substream_chip(substream);
  494. struct nm256_stream *s = substream->runtime->private_data;
  495. int err = 0;
  496. if (snd_BUG_ON(!s))
  497. return -ENXIO;
  498. spin_lock(&chip->reg_lock);
  499. switch (cmd) {
  500. case SNDRV_PCM_TRIGGER_START:
  501. case SNDRV_PCM_TRIGGER_RESUME:
  502. if (! s->running) {
  503. snd_nm256_capture_start(chip, s, substream);
  504. s->running = 1;
  505. }
  506. break;
  507. case SNDRV_PCM_TRIGGER_STOP:
  508. case SNDRV_PCM_TRIGGER_SUSPEND:
  509. if (s->running) {
  510. snd_nm256_capture_stop(chip);
  511. s->running = 0;
  512. }
  513. break;
  514. default:
  515. err = -EINVAL;
  516. break;
  517. }
  518. spin_unlock(&chip->reg_lock);
  519. return err;
  520. }
  521. /*
  522. * prepare playback/capture channel
  523. */
  524. static int snd_nm256_pcm_prepare(struct snd_pcm_substream *substream)
  525. {
  526. struct nm256 *chip = snd_pcm_substream_chip(substream);
  527. struct snd_pcm_runtime *runtime = substream->runtime;
  528. struct nm256_stream *s = runtime->private_data;
  529. if (snd_BUG_ON(!s))
  530. return -ENXIO;
  531. s->dma_size = frames_to_bytes(runtime, substream->runtime->buffer_size);
  532. s->period_size = frames_to_bytes(runtime, substream->runtime->period_size);
  533. s->periods = substream->runtime->periods;
  534. s->cur_period = 0;
  535. spin_lock_irq(&chip->reg_lock);
  536. s->running = 0;
  537. snd_nm256_set_format(chip, s, substream);
  538. spin_unlock_irq(&chip->reg_lock);
  539. return 0;
  540. }
  541. /*
  542. * get the current pointer
  543. */
  544. static snd_pcm_uframes_t
  545. snd_nm256_playback_pointer(struct snd_pcm_substream *substream)
  546. {
  547. struct nm256 *chip = snd_pcm_substream_chip(substream);
  548. struct nm256_stream *s = substream->runtime->private_data;
  549. unsigned long curp;
  550. if (snd_BUG_ON(!s))
  551. return 0;
  552. curp = snd_nm256_readl(chip, NM_PBUFFER_CURRP) - (unsigned long)s->buf;
  553. curp %= s->dma_size;
  554. return bytes_to_frames(substream->runtime, curp);
  555. }
  556. static snd_pcm_uframes_t
  557. snd_nm256_capture_pointer(struct snd_pcm_substream *substream)
  558. {
  559. struct nm256 *chip = snd_pcm_substream_chip(substream);
  560. struct nm256_stream *s = substream->runtime->private_data;
  561. unsigned long curp;
  562. if (snd_BUG_ON(!s))
  563. return 0;
  564. curp = snd_nm256_readl(chip, NM_RBUFFER_CURRP) - (unsigned long)s->buf;
  565. curp %= s->dma_size;
  566. return bytes_to_frames(substream->runtime, curp);
  567. }
  568. /* Remapped I/O space can be accessible as pointer on i386 */
  569. /* This might be changed in the future */
  570. #ifndef __i386__
  571. /*
  572. * silence / copy for playback
  573. */
  574. static int
  575. snd_nm256_playback_silence(struct snd_pcm_substream *substream,
  576. int channel, unsigned long pos, unsigned long count)
  577. {
  578. struct snd_pcm_runtime *runtime = substream->runtime;
  579. struct nm256_stream *s = runtime->private_data;
  580. memset_io(s->bufptr + pos, 0, count);
  581. return 0;
  582. }
  583. static int
  584. snd_nm256_playback_copy(struct snd_pcm_substream *substream,
  585. int channel, unsigned long pos,
  586. struct iov_iter *src, unsigned long count)
  587. {
  588. struct snd_pcm_runtime *runtime = substream->runtime;
  589. struct nm256_stream *s = runtime->private_data;
  590. return copy_from_iter_toio(s->bufptr + pos, src, count);
  591. }
  592. /*
  593. * copy to user
  594. */
  595. static int
  596. snd_nm256_capture_copy(struct snd_pcm_substream *substream,
  597. int channel, unsigned long pos,
  598. struct iov_iter *dst, unsigned long count)
  599. {
  600. struct snd_pcm_runtime *runtime = substream->runtime;
  601. struct nm256_stream *s = runtime->private_data;
  602. return copy_to_iter_fromio(dst, s->bufptr + pos, count);
  603. }
  604. #endif /* !__i386__ */
  605. /*
  606. * update playback/capture watermarks
  607. */
  608. /* spinlock held! */
  609. static void
  610. snd_nm256_playback_update(struct nm256 *chip)
  611. {
  612. struct nm256_stream *s;
  613. s = &chip->streams[SNDRV_PCM_STREAM_PLAYBACK];
  614. if (s->running && s->substream) {
  615. spin_unlock(&chip->reg_lock);
  616. snd_pcm_period_elapsed(s->substream);
  617. spin_lock(&chip->reg_lock);
  618. snd_nm256_playback_mark(chip, s);
  619. }
  620. }
  621. /* spinlock held! */
  622. static void
  623. snd_nm256_capture_update(struct nm256 *chip)
  624. {
  625. struct nm256_stream *s;
  626. s = &chip->streams[SNDRV_PCM_STREAM_CAPTURE];
  627. if (s->running && s->substream) {
  628. spin_unlock(&chip->reg_lock);
  629. snd_pcm_period_elapsed(s->substream);
  630. spin_lock(&chip->reg_lock);
  631. snd_nm256_capture_mark(chip, s);
  632. }
  633. }
  634. /*
  635. * hardware info
  636. */
  637. static const struct snd_pcm_hardware snd_nm256_playback =
  638. {
  639. .info = SNDRV_PCM_INFO_MMAP_IOMEM |SNDRV_PCM_INFO_MMAP_VALID |
  640. SNDRV_PCM_INFO_INTERLEAVED |
  641. /*SNDRV_PCM_INFO_PAUSE |*/
  642. SNDRV_PCM_INFO_RESUME,
  643. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  644. .rates = SNDRV_PCM_RATE_KNOT/*24k*/ | SNDRV_PCM_RATE_8000_48000,
  645. .rate_min = 8000,
  646. .rate_max = 48000,
  647. .channels_min = 1,
  648. .channels_max = 2,
  649. .periods_min = 2,
  650. .periods_max = 1024,
  651. .buffer_bytes_max = 128 * 1024,
  652. .period_bytes_min = 256,
  653. .period_bytes_max = 128 * 1024,
  654. };
  655. static const struct snd_pcm_hardware snd_nm256_capture =
  656. {
  657. .info = SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID |
  658. SNDRV_PCM_INFO_INTERLEAVED |
  659. /*SNDRV_PCM_INFO_PAUSE |*/
  660. SNDRV_PCM_INFO_RESUME,
  661. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  662. .rates = SNDRV_PCM_RATE_KNOT/*24k*/ | SNDRV_PCM_RATE_8000_48000,
  663. .rate_min = 8000,
  664. .rate_max = 48000,
  665. .channels_min = 1,
  666. .channels_max = 2,
  667. .periods_min = 2,
  668. .periods_max = 1024,
  669. .buffer_bytes_max = 128 * 1024,
  670. .period_bytes_min = 256,
  671. .period_bytes_max = 128 * 1024,
  672. };
  673. /* set dma transfer size */
  674. static int snd_nm256_pcm_hw_params(struct snd_pcm_substream *substream,
  675. struct snd_pcm_hw_params *hw_params)
  676. {
  677. /* area and addr are already set and unchanged */
  678. substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
  679. return 0;
  680. }
  681. /*
  682. * open
  683. */
  684. static void snd_nm256_setup_stream(struct nm256 *chip, struct nm256_stream *s,
  685. struct snd_pcm_substream *substream,
  686. const struct snd_pcm_hardware *hw_ptr)
  687. {
  688. struct snd_pcm_runtime *runtime = substream->runtime;
  689. s->running = 0;
  690. runtime->hw = *hw_ptr;
  691. runtime->hw.buffer_bytes_max = s->bufsize;
  692. runtime->hw.period_bytes_max = s->bufsize / 2;
  693. runtime->dma_area = (void __force *) s->bufptr;
  694. runtime->dma_addr = s->bufptr_addr;
  695. runtime->dma_bytes = s->bufsize;
  696. runtime->private_data = s;
  697. s->substream = substream;
  698. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  699. &constraints_rates);
  700. }
  701. static int
  702. snd_nm256_playback_open(struct snd_pcm_substream *substream)
  703. {
  704. struct nm256 *chip = snd_pcm_substream_chip(substream);
  705. if (snd_nm256_acquire_irq(chip) < 0)
  706. return -EBUSY;
  707. snd_nm256_setup_stream(chip, &chip->streams[SNDRV_PCM_STREAM_PLAYBACK],
  708. substream, &snd_nm256_playback);
  709. return 0;
  710. }
  711. static int
  712. snd_nm256_capture_open(struct snd_pcm_substream *substream)
  713. {
  714. struct nm256 *chip = snd_pcm_substream_chip(substream);
  715. if (snd_nm256_acquire_irq(chip) < 0)
  716. return -EBUSY;
  717. snd_nm256_setup_stream(chip, &chip->streams[SNDRV_PCM_STREAM_CAPTURE],
  718. substream, &snd_nm256_capture);
  719. return 0;
  720. }
  721. /*
  722. * close - we don't have to do special..
  723. */
  724. static int
  725. snd_nm256_playback_close(struct snd_pcm_substream *substream)
  726. {
  727. struct nm256 *chip = snd_pcm_substream_chip(substream);
  728. snd_nm256_release_irq(chip);
  729. return 0;
  730. }
  731. static int
  732. snd_nm256_capture_close(struct snd_pcm_substream *substream)
  733. {
  734. struct nm256 *chip = snd_pcm_substream_chip(substream);
  735. snd_nm256_release_irq(chip);
  736. return 0;
  737. }
  738. /*
  739. * create a pcm instance
  740. */
  741. static const struct snd_pcm_ops snd_nm256_playback_ops = {
  742. .open = snd_nm256_playback_open,
  743. .close = snd_nm256_playback_close,
  744. .hw_params = snd_nm256_pcm_hw_params,
  745. .prepare = snd_nm256_pcm_prepare,
  746. .trigger = snd_nm256_playback_trigger,
  747. .pointer = snd_nm256_playback_pointer,
  748. #ifndef __i386__
  749. .copy = snd_nm256_playback_copy,
  750. .fill_silence = snd_nm256_playback_silence,
  751. #endif
  752. .mmap = snd_pcm_lib_mmap_iomem,
  753. };
  754. static const struct snd_pcm_ops snd_nm256_capture_ops = {
  755. .open = snd_nm256_capture_open,
  756. .close = snd_nm256_capture_close,
  757. .hw_params = snd_nm256_pcm_hw_params,
  758. .prepare = snd_nm256_pcm_prepare,
  759. .trigger = snd_nm256_capture_trigger,
  760. .pointer = snd_nm256_capture_pointer,
  761. #ifndef __i386__
  762. .copy = snd_nm256_capture_copy,
  763. #endif
  764. .mmap = snd_pcm_lib_mmap_iomem,
  765. };
  766. static int
  767. snd_nm256_pcm(struct nm256 *chip, int device)
  768. {
  769. struct snd_pcm *pcm;
  770. int i, err;
  771. for (i = 0; i < 2; i++) {
  772. struct nm256_stream *s = &chip->streams[i];
  773. s->bufptr = chip->buffer + (s->buf - chip->buffer_start);
  774. s->bufptr_addr = chip->buffer_addr + (s->buf - chip->buffer_start);
  775. }
  776. err = snd_pcm_new(chip->card, chip->card->driver, device,
  777. 1, 1, &pcm);
  778. if (err < 0)
  779. return err;
  780. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_nm256_playback_ops);
  781. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_nm256_capture_ops);
  782. pcm->private_data = chip;
  783. pcm->info_flags = 0;
  784. chip->pcm = pcm;
  785. return 0;
  786. }
  787. /*
  788. * Initialize the hardware.
  789. */
  790. static void
  791. snd_nm256_init_chip(struct nm256 *chip)
  792. {
  793. /* Reset everything. */
  794. snd_nm256_writeb(chip, 0x0, 0x11);
  795. snd_nm256_writew(chip, 0x214, 0);
  796. /* stop sounds.. */
  797. //snd_nm256_playback_stop(chip);
  798. //snd_nm256_capture_stop(chip);
  799. }
  800. static irqreturn_t
  801. snd_nm256_intr_check(struct nm256 *chip)
  802. {
  803. if (chip->badintrcount++ > 1000) {
  804. /*
  805. * I'm not sure if the best thing is to stop the card from
  806. * playing or just release the interrupt (after all, we're in
  807. * a bad situation, so doing fancy stuff may not be such a good
  808. * idea).
  809. *
  810. * I worry about the card engine continuing to play noise
  811. * over and over, however--that could become a very
  812. * obnoxious problem. And we know that when this usually
  813. * happens things are fairly safe, it just means the user's
  814. * inserted a PCMCIA card and someone's spamming us with IRQ 9s.
  815. */
  816. if (chip->streams[SNDRV_PCM_STREAM_PLAYBACK].running)
  817. snd_nm256_playback_stop(chip);
  818. if (chip->streams[SNDRV_PCM_STREAM_CAPTURE].running)
  819. snd_nm256_capture_stop(chip);
  820. chip->badintrcount = 0;
  821. return IRQ_HANDLED;
  822. }
  823. return IRQ_NONE;
  824. }
  825. /*
  826. * Handle a potential interrupt for the device referred to by DEV_ID.
  827. *
  828. * I don't like the cut-n-paste job here either between the two routines,
  829. * but there are sufficient differences between the two interrupt handlers
  830. * that parameterizing it isn't all that great either. (Could use a macro,
  831. * I suppose...yucky bleah.)
  832. */
  833. static irqreturn_t
  834. snd_nm256_interrupt(int irq, void *dev_id)
  835. {
  836. struct nm256 *chip = dev_id;
  837. u16 status;
  838. u8 cbyte;
  839. status = snd_nm256_readw(chip, NM_INT_REG);
  840. /* Not ours. */
  841. if (status == 0)
  842. return snd_nm256_intr_check(chip);
  843. chip->badintrcount = 0;
  844. /* Rather boring; check for individual interrupts and process them. */
  845. spin_lock(&chip->reg_lock);
  846. if (status & NM_PLAYBACK_INT) {
  847. status &= ~NM_PLAYBACK_INT;
  848. NM_ACK_INT(chip, NM_PLAYBACK_INT);
  849. snd_nm256_playback_update(chip);
  850. }
  851. if (status & NM_RECORD_INT) {
  852. status &= ~NM_RECORD_INT;
  853. NM_ACK_INT(chip, NM_RECORD_INT);
  854. snd_nm256_capture_update(chip);
  855. }
  856. if (status & NM_MISC_INT_1) {
  857. status &= ~NM_MISC_INT_1;
  858. NM_ACK_INT(chip, NM_MISC_INT_1);
  859. dev_dbg(chip->card->dev, "NM256: Got misc interrupt #1\n");
  860. snd_nm256_writew(chip, NM_INT_REG, 0x8000);
  861. cbyte = snd_nm256_readb(chip, 0x400);
  862. snd_nm256_writeb(chip, 0x400, cbyte | 2);
  863. }
  864. if (status & NM_MISC_INT_2) {
  865. status &= ~NM_MISC_INT_2;
  866. NM_ACK_INT(chip, NM_MISC_INT_2);
  867. dev_dbg(chip->card->dev, "NM256: Got misc interrupt #2\n");
  868. cbyte = snd_nm256_readb(chip, 0x400);
  869. snd_nm256_writeb(chip, 0x400, cbyte & ~2);
  870. }
  871. /* Unknown interrupt. */
  872. if (status) {
  873. dev_dbg(chip->card->dev,
  874. "NM256: Fire in the hole! Unknown status 0x%x\n",
  875. status);
  876. /* Pray. */
  877. NM_ACK_INT(chip, status);
  878. }
  879. spin_unlock(&chip->reg_lock);
  880. return IRQ_HANDLED;
  881. }
  882. /*
  883. * Handle a potential interrupt for the device referred to by DEV_ID.
  884. * This handler is for the 256ZX, and is very similar to the non-ZX
  885. * routine.
  886. */
  887. static irqreturn_t
  888. snd_nm256_interrupt_zx(int irq, void *dev_id)
  889. {
  890. struct nm256 *chip = dev_id;
  891. u32 status;
  892. u8 cbyte;
  893. status = snd_nm256_readl(chip, NM_INT_REG);
  894. /* Not ours. */
  895. if (status == 0)
  896. return snd_nm256_intr_check(chip);
  897. chip->badintrcount = 0;
  898. /* Rather boring; check for individual interrupts and process them. */
  899. spin_lock(&chip->reg_lock);
  900. if (status & NM2_PLAYBACK_INT) {
  901. status &= ~NM2_PLAYBACK_INT;
  902. NM2_ACK_INT(chip, NM2_PLAYBACK_INT);
  903. snd_nm256_playback_update(chip);
  904. }
  905. if (status & NM2_RECORD_INT) {
  906. status &= ~NM2_RECORD_INT;
  907. NM2_ACK_INT(chip, NM2_RECORD_INT);
  908. snd_nm256_capture_update(chip);
  909. }
  910. if (status & NM2_MISC_INT_1) {
  911. status &= ~NM2_MISC_INT_1;
  912. NM2_ACK_INT(chip, NM2_MISC_INT_1);
  913. dev_dbg(chip->card->dev, "NM256: Got misc interrupt #1\n");
  914. cbyte = snd_nm256_readb(chip, 0x400);
  915. snd_nm256_writeb(chip, 0x400, cbyte | 2);
  916. }
  917. if (status & NM2_MISC_INT_2) {
  918. status &= ~NM2_MISC_INT_2;
  919. NM2_ACK_INT(chip, NM2_MISC_INT_2);
  920. dev_dbg(chip->card->dev, "NM256: Got misc interrupt #2\n");
  921. cbyte = snd_nm256_readb(chip, 0x400);
  922. snd_nm256_writeb(chip, 0x400, cbyte & ~2);
  923. }
  924. /* Unknown interrupt. */
  925. if (status) {
  926. dev_dbg(chip->card->dev,
  927. "NM256: Fire in the hole! Unknown status 0x%x\n",
  928. status);
  929. /* Pray. */
  930. NM2_ACK_INT(chip, status);
  931. }
  932. spin_unlock(&chip->reg_lock);
  933. return IRQ_HANDLED;
  934. }
  935. /*
  936. * AC97 interface
  937. */
  938. /*
  939. * Waits for the mixer to become ready to be written; returns a zero value
  940. * if it timed out.
  941. */
  942. static int
  943. snd_nm256_ac97_ready(struct nm256 *chip)
  944. {
  945. int timeout = 10;
  946. u32 testaddr;
  947. u16 testb;
  948. testaddr = chip->mixer_status_offset;
  949. testb = chip->mixer_status_mask;
  950. /*
  951. * Loop around waiting for the mixer to become ready.
  952. */
  953. while (timeout-- > 0) {
  954. if ((snd_nm256_readw(chip, testaddr) & testb) == 0)
  955. return 1;
  956. udelay(100);
  957. }
  958. return 0;
  959. }
  960. /*
  961. * Initial register values to be written to the AC97 mixer.
  962. * While most of these are identical to the reset values, we do this
  963. * so that we have most of the register contents cached--this avoids
  964. * reading from the mixer directly (which seems to be problematic,
  965. * probably due to ignorance).
  966. */
  967. struct initialValues {
  968. unsigned short reg;
  969. unsigned short value;
  970. };
  971. static const struct initialValues nm256_ac97_init_val[] =
  972. {
  973. { AC97_MASTER, 0x8000 },
  974. { AC97_HEADPHONE, 0x8000 },
  975. { AC97_MASTER_MONO, 0x8000 },
  976. { AC97_PC_BEEP, 0x8000 },
  977. { AC97_PHONE, 0x8008 },
  978. { AC97_MIC, 0x8000 },
  979. { AC97_LINE, 0x8808 },
  980. { AC97_CD, 0x8808 },
  981. { AC97_VIDEO, 0x8808 },
  982. { AC97_AUX, 0x8808 },
  983. { AC97_PCM, 0x8808 },
  984. { AC97_REC_SEL, 0x0000 },
  985. { AC97_REC_GAIN, 0x0B0B },
  986. { AC97_GENERAL_PURPOSE, 0x0000 },
  987. { AC97_3D_CONTROL, 0x8000 },
  988. { AC97_VENDOR_ID1, 0x8384 },
  989. { AC97_VENDOR_ID2, 0x7609 },
  990. };
  991. static int nm256_ac97_idx(unsigned short reg)
  992. {
  993. int i;
  994. for (i = 0; i < ARRAY_SIZE(nm256_ac97_init_val); i++)
  995. if (nm256_ac97_init_val[i].reg == reg)
  996. return i;
  997. return -1;
  998. }
  999. /*
  1000. * some nm256 easily crash when reading from mixer registers
  1001. * thus we're treating it as a write-only mixer and cache the
  1002. * written values
  1003. */
  1004. static unsigned short
  1005. snd_nm256_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  1006. {
  1007. struct nm256 *chip = ac97->private_data;
  1008. int idx = nm256_ac97_idx(reg);
  1009. if (idx < 0)
  1010. return 0;
  1011. return chip->ac97_regs[idx];
  1012. }
  1013. /*
  1014. */
  1015. static void
  1016. snd_nm256_ac97_write(struct snd_ac97 *ac97,
  1017. unsigned short reg, unsigned short val)
  1018. {
  1019. struct nm256 *chip = ac97->private_data;
  1020. int tries = 2;
  1021. int idx = nm256_ac97_idx(reg);
  1022. u32 base;
  1023. if (idx < 0)
  1024. return;
  1025. base = chip->mixer_base;
  1026. snd_nm256_ac97_ready(chip);
  1027. /* Wait for the write to take, too. */
  1028. while (tries-- > 0) {
  1029. snd_nm256_writew(chip, base + reg, val);
  1030. msleep(1); /* a little delay here seems better.. */
  1031. if (snd_nm256_ac97_ready(chip)) {
  1032. /* successful write: set cache */
  1033. chip->ac97_regs[idx] = val;
  1034. return;
  1035. }
  1036. }
  1037. dev_dbg(chip->card->dev, "nm256: ac97 codec not ready..\n");
  1038. }
  1039. /* static resolution table */
  1040. static const struct snd_ac97_res_table nm256_res_table[] = {
  1041. { AC97_MASTER, 0x1f1f },
  1042. { AC97_HEADPHONE, 0x1f1f },
  1043. { AC97_MASTER_MONO, 0x001f },
  1044. { AC97_PC_BEEP, 0x001f },
  1045. { AC97_PHONE, 0x001f },
  1046. { AC97_MIC, 0x001f },
  1047. { AC97_LINE, 0x1f1f },
  1048. { AC97_CD, 0x1f1f },
  1049. { AC97_VIDEO, 0x1f1f },
  1050. { AC97_AUX, 0x1f1f },
  1051. { AC97_PCM, 0x1f1f },
  1052. { AC97_REC_GAIN, 0x0f0f },
  1053. { } /* terminator */
  1054. };
  1055. /* initialize the ac97 into a known state */
  1056. static void
  1057. snd_nm256_ac97_reset(struct snd_ac97 *ac97)
  1058. {
  1059. struct nm256 *chip = ac97->private_data;
  1060. /* Reset the mixer. 'Tis magic! */
  1061. snd_nm256_writeb(chip, 0x6c0, 1);
  1062. if (! chip->reset_workaround) {
  1063. /* Dell latitude LS will lock up by this */
  1064. snd_nm256_writeb(chip, 0x6cc, 0x87);
  1065. }
  1066. if (! chip->reset_workaround_2) {
  1067. /* Dell latitude CSx will lock up by this */
  1068. snd_nm256_writeb(chip, 0x6cc, 0x80);
  1069. snd_nm256_writeb(chip, 0x6cc, 0x0);
  1070. }
  1071. if (! chip->in_resume) {
  1072. int i;
  1073. for (i = 0; i < ARRAY_SIZE(nm256_ac97_init_val); i++) {
  1074. /* preload the cache, so as to avoid even a single
  1075. * read of the mixer regs
  1076. */
  1077. snd_nm256_ac97_write(ac97, nm256_ac97_init_val[i].reg,
  1078. nm256_ac97_init_val[i].value);
  1079. }
  1080. }
  1081. }
  1082. /* create an ac97 mixer interface */
  1083. static int
  1084. snd_nm256_mixer(struct nm256 *chip)
  1085. {
  1086. struct snd_ac97_bus *pbus;
  1087. struct snd_ac97_template ac97;
  1088. int err;
  1089. static const struct snd_ac97_bus_ops ops = {
  1090. .reset = snd_nm256_ac97_reset,
  1091. .write = snd_nm256_ac97_write,
  1092. .read = snd_nm256_ac97_read,
  1093. };
  1094. chip->ac97_regs = devm_kcalloc(chip->card->dev,
  1095. ARRAY_SIZE(nm256_ac97_init_val),
  1096. sizeof(short), GFP_KERNEL);
  1097. if (! chip->ac97_regs)
  1098. return -ENOMEM;
  1099. err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus);
  1100. if (err < 0)
  1101. return err;
  1102. memset(&ac97, 0, sizeof(ac97));
  1103. ac97.scaps = AC97_SCAP_AUDIO; /* we support audio! */
  1104. ac97.private_data = chip;
  1105. ac97.res_table = nm256_res_table;
  1106. pbus->no_vra = 1;
  1107. err = snd_ac97_mixer(pbus, &ac97, &chip->ac97);
  1108. if (err < 0)
  1109. return err;
  1110. if (! (chip->ac97->id & (0xf0000000))) {
  1111. /* looks like an invalid id */
  1112. sprintf(chip->card->mixername, "%s AC97", chip->card->driver);
  1113. }
  1114. return 0;
  1115. }
  1116. /*
  1117. * See if the signature left by the NM256 BIOS is intact; if so, we use
  1118. * the associated address as the end of our audio buffer in the video
  1119. * RAM.
  1120. */
  1121. static int
  1122. snd_nm256_peek_for_sig(struct nm256 *chip)
  1123. {
  1124. /* The signature is located 1K below the end of video RAM. */
  1125. void __iomem *temp;
  1126. /* Default buffer end is 5120 bytes below the top of RAM. */
  1127. unsigned long pointer_found = chip->buffer_end - 0x1400;
  1128. u32 sig;
  1129. temp = ioremap(chip->buffer_addr + chip->buffer_end - 0x400, 16);
  1130. if (temp == NULL) {
  1131. dev_err(chip->card->dev,
  1132. "Unable to scan for card signature in video RAM\n");
  1133. return -EBUSY;
  1134. }
  1135. sig = readl(temp);
  1136. if ((sig & NM_SIG_MASK) == NM_SIGNATURE) {
  1137. u32 pointer = readl(temp + 4);
  1138. /*
  1139. * If it's obviously invalid, don't use it
  1140. */
  1141. if (pointer == 0xffffffff ||
  1142. pointer < chip->buffer_size ||
  1143. pointer > chip->buffer_end) {
  1144. dev_err(chip->card->dev,
  1145. "invalid signature found: 0x%x\n", pointer);
  1146. iounmap(temp);
  1147. return -ENODEV;
  1148. } else {
  1149. pointer_found = pointer;
  1150. dev_info(chip->card->dev,
  1151. "found card signature in video RAM: 0x%x\n",
  1152. pointer);
  1153. }
  1154. }
  1155. iounmap(temp);
  1156. chip->buffer_end = pointer_found;
  1157. return 0;
  1158. }
  1159. /*
  1160. * APM event handler, so the card is properly reinitialized after a power
  1161. * event.
  1162. */
  1163. static int nm256_suspend(struct device *dev)
  1164. {
  1165. struct snd_card *card = dev_get_drvdata(dev);
  1166. struct nm256 *chip = card->private_data;
  1167. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1168. snd_ac97_suspend(chip->ac97);
  1169. chip->coeffs_current = 0;
  1170. return 0;
  1171. }
  1172. static int nm256_resume(struct device *dev)
  1173. {
  1174. struct snd_card *card = dev_get_drvdata(dev);
  1175. struct nm256 *chip = card->private_data;
  1176. int i;
  1177. /* Perform a full reset on the hardware */
  1178. chip->in_resume = 1;
  1179. snd_nm256_init_chip(chip);
  1180. /* restore ac97 */
  1181. snd_ac97_resume(chip->ac97);
  1182. for (i = 0; i < 2; i++) {
  1183. struct nm256_stream *s = &chip->streams[i];
  1184. if (s->substream && s->suspended) {
  1185. spin_lock_irq(&chip->reg_lock);
  1186. snd_nm256_set_format(chip, s, s->substream);
  1187. spin_unlock_irq(&chip->reg_lock);
  1188. }
  1189. }
  1190. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1191. chip->in_resume = 0;
  1192. return 0;
  1193. }
  1194. static DEFINE_SIMPLE_DEV_PM_OPS(nm256_pm, nm256_suspend, nm256_resume);
  1195. static void snd_nm256_free(struct snd_card *card)
  1196. {
  1197. struct nm256 *chip = card->private_data;
  1198. if (chip->streams[SNDRV_PCM_STREAM_PLAYBACK].running)
  1199. snd_nm256_playback_stop(chip);
  1200. if (chip->streams[SNDRV_PCM_STREAM_CAPTURE].running)
  1201. snd_nm256_capture_stop(chip);
  1202. }
  1203. static int
  1204. snd_nm256_create(struct snd_card *card, struct pci_dev *pci)
  1205. {
  1206. struct nm256 *chip = card->private_data;
  1207. int err, pval;
  1208. u32 addr;
  1209. err = pcim_enable_device(pci);
  1210. if (err < 0)
  1211. return err;
  1212. chip->card = card;
  1213. chip->pci = pci;
  1214. chip->use_cache = use_cache;
  1215. spin_lock_init(&chip->reg_lock);
  1216. chip->irq = -1;
  1217. mutex_init(&chip->irq_mutex);
  1218. /* store buffer sizes in bytes */
  1219. chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize = playback_bufsize * 1024;
  1220. chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize = capture_bufsize * 1024;
  1221. /*
  1222. * The NM256 has two memory ports. The first port is nothing
  1223. * more than a chunk of video RAM, which is used as the I/O ring
  1224. * buffer. The second port has the actual juicy stuff (like the
  1225. * mixer and the playback engine control registers).
  1226. */
  1227. chip->buffer_addr = pci_resource_start(pci, 0);
  1228. chip->cport_addr = pci_resource_start(pci, 1);
  1229. err = pci_request_regions(pci, card->driver);
  1230. if (err < 0)
  1231. return err;
  1232. /* Init the memory port info. */
  1233. /* remap control port (#2) */
  1234. chip->cport = devm_ioremap(&pci->dev, chip->cport_addr, NM_PORT2_SIZE);
  1235. if (!chip->cport) {
  1236. dev_err(card->dev, "unable to map control port %lx\n",
  1237. chip->cport_addr);
  1238. return -ENOMEM;
  1239. }
  1240. if (!strcmp(card->driver, "NM256AV")) {
  1241. /* Ok, try to see if this is a non-AC97 version of the hardware. */
  1242. pval = snd_nm256_readw(chip, NM_MIXER_PRESENCE);
  1243. if ((pval & NM_PRESENCE_MASK) != NM_PRESENCE_VALUE) {
  1244. if (! force_ac97) {
  1245. dev_err(card->dev,
  1246. "no ac97 is found!\n");
  1247. dev_err(card->dev,
  1248. "force the driver to load by passing in the module parameter\n");
  1249. dev_err(card->dev,
  1250. " force_ac97=1\n");
  1251. dev_err(card->dev,
  1252. "or try sb16, opl3sa2, or cs423x drivers instead.\n");
  1253. return -ENXIO;
  1254. }
  1255. }
  1256. chip->buffer_end = 2560 * 1024;
  1257. chip->interrupt = snd_nm256_interrupt;
  1258. chip->mixer_status_offset = NM_MIXER_STATUS_OFFSET;
  1259. chip->mixer_status_mask = NM_MIXER_READY_MASK;
  1260. } else {
  1261. /* Not sure if there is any relevant detect for the ZX or not. */
  1262. if (snd_nm256_readb(chip, 0xa0b) != 0)
  1263. chip->buffer_end = 6144 * 1024;
  1264. else
  1265. chip->buffer_end = 4096 * 1024;
  1266. chip->interrupt = snd_nm256_interrupt_zx;
  1267. chip->mixer_status_offset = NM2_MIXER_STATUS_OFFSET;
  1268. chip->mixer_status_mask = NM2_MIXER_READY_MASK;
  1269. }
  1270. chip->buffer_size = chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize +
  1271. chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize;
  1272. if (chip->use_cache)
  1273. chip->buffer_size += NM_TOTAL_COEFF_COUNT * 4;
  1274. else
  1275. chip->buffer_size += NM_MAX_PLAYBACK_COEF_SIZE + NM_MAX_RECORD_COEF_SIZE;
  1276. if (buffer_top >= chip->buffer_size && buffer_top < chip->buffer_end)
  1277. chip->buffer_end = buffer_top;
  1278. else {
  1279. /* get buffer end pointer from signature */
  1280. err = snd_nm256_peek_for_sig(chip);
  1281. if (err < 0)
  1282. return err;
  1283. }
  1284. chip->buffer_start = chip->buffer_end - chip->buffer_size;
  1285. chip->buffer_addr += chip->buffer_start;
  1286. dev_info(card->dev, "Mapping port 1 from 0x%x - 0x%x\n",
  1287. chip->buffer_start, chip->buffer_end);
  1288. chip->buffer = devm_ioremap(&pci->dev, chip->buffer_addr,
  1289. chip->buffer_size);
  1290. if (!chip->buffer) {
  1291. dev_err(card->dev, "unable to map ring buffer at %lx\n",
  1292. chip->buffer_addr);
  1293. return -ENOMEM;
  1294. }
  1295. /* set offsets */
  1296. addr = chip->buffer_start;
  1297. chip->streams[SNDRV_PCM_STREAM_PLAYBACK].buf = addr;
  1298. addr += chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize;
  1299. chip->streams[SNDRV_PCM_STREAM_CAPTURE].buf = addr;
  1300. addr += chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize;
  1301. if (chip->use_cache) {
  1302. chip->all_coeff_buf = addr;
  1303. } else {
  1304. chip->coeff_buf[SNDRV_PCM_STREAM_PLAYBACK] = addr;
  1305. addr += NM_MAX_PLAYBACK_COEF_SIZE;
  1306. chip->coeff_buf[SNDRV_PCM_STREAM_CAPTURE] = addr;
  1307. }
  1308. /* Fixed setting. */
  1309. chip->mixer_base = NM_MIXER_OFFSET;
  1310. chip->coeffs_current = 0;
  1311. snd_nm256_init_chip(chip);
  1312. // pci_set_master(pci); /* needed? */
  1313. return 0;
  1314. }
  1315. enum { NM_IGNORED, NM_RESET_WORKAROUND, NM_RESET_WORKAROUND_2 };
  1316. static const struct snd_pci_quirk nm256_quirks[] = {
  1317. /* HP omnibook 4150 has cs4232 codec internally */
  1318. SND_PCI_QUIRK(0x103c, 0x0007, "HP omnibook 4150", NM_IGNORED),
  1319. /* Reset workarounds to avoid lock-ups */
  1320. SND_PCI_QUIRK(0x104d, 0x8041, "Sony PCG-F305", NM_RESET_WORKAROUND),
  1321. SND_PCI_QUIRK(0x1028, 0x0080, "Dell Latitude LS", NM_RESET_WORKAROUND),
  1322. SND_PCI_QUIRK(0x1028, 0x0091, "Dell Latitude CSx", NM_RESET_WORKAROUND_2),
  1323. { } /* terminator */
  1324. };
  1325. static int snd_nm256_probe(struct pci_dev *pci,
  1326. const struct pci_device_id *pci_id)
  1327. {
  1328. struct snd_card *card;
  1329. struct nm256 *chip;
  1330. int err;
  1331. const struct snd_pci_quirk *q;
  1332. q = snd_pci_quirk_lookup(pci, nm256_quirks);
  1333. if (q) {
  1334. dev_dbg(&pci->dev, "Enabled quirk for %s.\n",
  1335. snd_pci_quirk_name(q));
  1336. switch (q->value) {
  1337. case NM_IGNORED:
  1338. dev_info(&pci->dev,
  1339. "The device is on the denylist. Loading stopped\n");
  1340. return -ENODEV;
  1341. case NM_RESET_WORKAROUND_2:
  1342. reset_workaround_2 = 1;
  1343. fallthrough;
  1344. case NM_RESET_WORKAROUND:
  1345. reset_workaround = 1;
  1346. break;
  1347. }
  1348. }
  1349. err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,
  1350. sizeof(*chip), &card);
  1351. if (err < 0)
  1352. return err;
  1353. chip = card->private_data;
  1354. switch (pci->device) {
  1355. case PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO:
  1356. strcpy(card->driver, "NM256AV");
  1357. break;
  1358. case PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO:
  1359. strcpy(card->driver, "NM256ZX");
  1360. break;
  1361. case PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO:
  1362. strcpy(card->driver, "NM256XL+");
  1363. break;
  1364. default:
  1365. dev_err(&pci->dev, "invalid device id 0x%x\n", pci->device);
  1366. return -EINVAL;
  1367. }
  1368. if (vaio_hack)
  1369. buffer_top = 0x25a800; /* this avoids conflicts with XFree86 server */
  1370. if (playback_bufsize < 4)
  1371. playback_bufsize = 4;
  1372. if (playback_bufsize > 128)
  1373. playback_bufsize = 128;
  1374. if (capture_bufsize < 4)
  1375. capture_bufsize = 4;
  1376. if (capture_bufsize > 128)
  1377. capture_bufsize = 128;
  1378. err = snd_nm256_create(card, pci);
  1379. if (err < 0)
  1380. return err;
  1381. if (reset_workaround) {
  1382. dev_dbg(&pci->dev, "reset_workaround activated\n");
  1383. chip->reset_workaround = 1;
  1384. }
  1385. if (reset_workaround_2) {
  1386. dev_dbg(&pci->dev, "reset_workaround_2 activated\n");
  1387. chip->reset_workaround_2 = 1;
  1388. }
  1389. err = snd_nm256_pcm(chip, 0);
  1390. if (err < 0)
  1391. return err;
  1392. err = snd_nm256_mixer(chip);
  1393. if (err < 0)
  1394. return err;
  1395. sprintf(card->shortname, "NeoMagic %s", card->driver);
  1396. sprintf(card->longname, "%s at 0x%lx & 0x%lx, irq %d",
  1397. card->shortname,
  1398. chip->buffer_addr, chip->cport_addr, chip->irq);
  1399. err = snd_card_register(card);
  1400. if (err < 0)
  1401. return err;
  1402. card->private_free = snd_nm256_free;
  1403. pci_set_drvdata(pci, card);
  1404. return 0;
  1405. }
  1406. static struct pci_driver nm256_driver = {
  1407. .name = KBUILD_MODNAME,
  1408. .id_table = snd_nm256_ids,
  1409. .probe = snd_nm256_probe,
  1410. .driver = {
  1411. .pm = &nm256_pm,
  1412. },
  1413. };
  1414. module_pci_driver(nm256_driver);