acp63.c 8.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
  2. //
  3. // This file is provided under a dual BSD/GPLv2 license. When using or
  4. // redistributing this file, you may do so under either license.
  5. //
  6. // Copyright(c) 2023 Advanced Micro Devices, Inc.
  7. //
  8. // Authors: Syed Saba kareem <syed.sabakareem@amd.com>
  9. /*
  10. * Hardware interface for ACP6.3 block
  11. */
  12. #include <linux/platform_device.h>
  13. #include <linux/module.h>
  14. #include <linux/err.h>
  15. #include <linux/io.h>
  16. #include <sound/pcm_params.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dai.h>
  19. #include <linux/dma-mapping.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/pci.h>
  22. #include "amd.h"
  23. #include "acp-mach.h"
  24. #include "../mach-config.h"
  25. #define DRV_NAME "acp_asoc_acp63"
  26. #define CLK_PLL_PWR_REQ_N0 0X0006C2C0
  27. #define CLK_SPLL_FIELD_2_N0 0X0006C114
  28. #define CLK_PLL_REQ_N0 0X0006C0DC
  29. #define CLK_DFSBYPASS_CONTR 0X0006C2C8
  30. #define CLK_DFS_CNTL_N0 0X0006C1A4
  31. #define PLL_AUTO_STOP_REQ BIT(4)
  32. #define PLL_AUTO_START_REQ BIT(0)
  33. #define PLL_FRANCE_EN BIT(4)
  34. #define EXIT_DPF_BYPASS_0 BIT(16)
  35. #define EXIT_DPF_BYPASS_1 BIT(17)
  36. #define CLK0_DIVIDER 0X30
  37. union clk_pll_req_no {
  38. struct {
  39. u32 fb_mult_int : 9;
  40. u32 reserved : 3;
  41. u32 pll_spine_div : 4;
  42. u32 gb_mult_frac : 16;
  43. } bitfields, bits;
  44. u32 clk_pll_req_no_reg;
  45. };
  46. static struct acp_resource rsrc = {
  47. .offset = 0,
  48. .no_of_ctrls = 2,
  49. .irqp_used = 1,
  50. .soc_mclk = true,
  51. .irq_reg_offset = 0x1a00,
  52. .scratch_reg_offset = 0x12800,
  53. .sram_pte_offset = 0x03802800,
  54. };
  55. static struct snd_soc_acpi_mach snd_soc_acpi_amd_acp63_acp_machines[] = {
  56. {
  57. .id = "AMDI0052",
  58. .drv_name = "acp63-acp",
  59. },
  60. {},
  61. };
  62. static struct snd_soc_dai_driver acp63_dai[] = {
  63. {
  64. .name = "acp-i2s-sp",
  65. .id = I2S_SP_INSTANCE,
  66. .playback = {
  67. .stream_name = "I2S SP Playback",
  68. .rates = SNDRV_PCM_RATE_8000_96000,
  69. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
  70. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
  71. .channels_min = 2,
  72. .channels_max = 8,
  73. .rate_min = 8000,
  74. .rate_max = 96000,
  75. },
  76. .capture = {
  77. .stream_name = "I2S SP Capture",
  78. .rates = SNDRV_PCM_RATE_8000_48000,
  79. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
  80. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
  81. .channels_min = 2,
  82. .channels_max = 2,
  83. .rate_min = 8000,
  84. .rate_max = 48000,
  85. },
  86. .ops = &asoc_acp_cpu_dai_ops,
  87. },
  88. {
  89. .name = "acp-i2s-bt",
  90. .id = I2S_BT_INSTANCE,
  91. .playback = {
  92. .stream_name = "I2S BT Playback",
  93. .rates = SNDRV_PCM_RATE_8000_96000,
  94. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
  95. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
  96. .channels_min = 2,
  97. .channels_max = 8,
  98. .rate_min = 8000,
  99. .rate_max = 96000,
  100. },
  101. .capture = {
  102. .stream_name = "I2S BT Capture",
  103. .rates = SNDRV_PCM_RATE_8000_48000,
  104. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
  105. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
  106. .channels_min = 2,
  107. .channels_max = 2,
  108. .rate_min = 8000,
  109. .rate_max = 48000,
  110. },
  111. .ops = &asoc_acp_cpu_dai_ops,
  112. },
  113. {
  114. .name = "acp-i2s-hs",
  115. .id = I2S_HS_INSTANCE,
  116. .playback = {
  117. .stream_name = "I2S HS Playback",
  118. .rates = SNDRV_PCM_RATE_8000_96000,
  119. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
  120. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
  121. .channels_min = 2,
  122. .channels_max = 8,
  123. .rate_min = 8000,
  124. .rate_max = 96000,
  125. },
  126. .capture = {
  127. .stream_name = "I2S HS Capture",
  128. .rates = SNDRV_PCM_RATE_8000_48000,
  129. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
  130. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
  131. .channels_min = 2,
  132. .channels_max = 8,
  133. .rate_min = 8000,
  134. .rate_max = 48000,
  135. },
  136. .ops = &asoc_acp_cpu_dai_ops,
  137. },
  138. {
  139. .name = "acp-pdm-dmic",
  140. .id = DMIC_INSTANCE,
  141. .capture = {
  142. .rates = SNDRV_PCM_RATE_8000_48000,
  143. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  144. .channels_min = 2,
  145. .channels_max = 2,
  146. .rate_min = 8000,
  147. .rate_max = 48000,
  148. },
  149. .ops = &acp_dmic_dai_ops,
  150. },
  151. };
  152. static int acp63_i2s_master_clock_generate(struct acp_dev_data *adata)
  153. {
  154. u32 data;
  155. union clk_pll_req_no clk_pll;
  156. struct pci_dev *smn_dev;
  157. smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x14E8, NULL);
  158. if (!smn_dev)
  159. return -ENODEV;
  160. /* Clk5 pll register values to get mclk as 196.6MHz*/
  161. clk_pll.bits.fb_mult_int = 0x31;
  162. clk_pll.bits.pll_spine_div = 0;
  163. clk_pll.bits.gb_mult_frac = 0x26E9;
  164. data = smn_read(smn_dev, CLK_PLL_PWR_REQ_N0);
  165. smn_write(smn_dev, CLK_PLL_PWR_REQ_N0, data | PLL_AUTO_STOP_REQ);
  166. data = smn_read(smn_dev, CLK_SPLL_FIELD_2_N0);
  167. if (data & PLL_FRANCE_EN)
  168. smn_write(smn_dev, CLK_SPLL_FIELD_2_N0, data | PLL_FRANCE_EN);
  169. smn_write(smn_dev, CLK_PLL_REQ_N0, clk_pll.clk_pll_req_no_reg);
  170. data = smn_read(smn_dev, CLK_PLL_PWR_REQ_N0);
  171. smn_write(smn_dev, CLK_PLL_PWR_REQ_N0, data | PLL_AUTO_START_REQ);
  172. data = smn_read(smn_dev, CLK_DFSBYPASS_CONTR);
  173. smn_write(smn_dev, CLK_DFSBYPASS_CONTR, data | EXIT_DPF_BYPASS_0);
  174. smn_write(smn_dev, CLK_DFSBYPASS_CONTR, data | EXIT_DPF_BYPASS_1);
  175. smn_write(smn_dev, CLK_DFS_CNTL_N0, CLK0_DIVIDER);
  176. return 0;
  177. }
  178. static int acp63_audio_probe(struct platform_device *pdev)
  179. {
  180. struct device *dev = &pdev->dev;
  181. struct acp_chip_info *chip;
  182. struct acp_dev_data *adata;
  183. struct resource *res;
  184. int ret;
  185. chip = dev_get_platdata(&pdev->dev);
  186. if (!chip || !chip->base) {
  187. dev_err(&pdev->dev, "ACP chip data is NULL\n");
  188. return -ENODEV;
  189. }
  190. if (chip->acp_rev != ACP63_DEV) {
  191. dev_err(&pdev->dev, "Un-supported ACP Revision %d\n", chip->acp_rev);
  192. return -ENODEV;
  193. }
  194. adata = devm_kzalloc(dev, sizeof(struct acp_dev_data), GFP_KERNEL);
  195. if (!adata)
  196. return -ENOMEM;
  197. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "acp_mem");
  198. if (!res) {
  199. dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
  200. return -ENODEV;
  201. }
  202. adata->acp_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
  203. if (!adata->acp_base)
  204. return -ENOMEM;
  205. res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "acp_dai_irq");
  206. if (!res) {
  207. dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
  208. return -ENODEV;
  209. }
  210. adata->i2s_irq = res->start;
  211. adata->dev = dev;
  212. adata->dai_driver = acp63_dai;
  213. adata->num_dai = ARRAY_SIZE(acp63_dai);
  214. adata->rsrc = &rsrc;
  215. adata->platform = ACP63;
  216. adata->flag = chip->flag;
  217. adata->is_i2s_config = chip->is_i2s_config;
  218. adata->machines = snd_soc_acpi_amd_acp63_acp_machines;
  219. acp_machine_select(adata);
  220. dev_set_drvdata(dev, adata);
  221. if (chip->is_i2s_config && rsrc.soc_mclk) {
  222. ret = acp63_i2s_master_clock_generate(adata);
  223. if (ret)
  224. return ret;
  225. }
  226. acp_enable_interrupts(adata);
  227. acp_platform_register(dev);
  228. pm_runtime_set_autosuspend_delay(&pdev->dev, ACP_SUSPEND_DELAY_MS);
  229. pm_runtime_use_autosuspend(&pdev->dev);
  230. pm_runtime_mark_last_busy(&pdev->dev);
  231. pm_runtime_set_active(&pdev->dev);
  232. pm_runtime_enable(&pdev->dev);
  233. return 0;
  234. }
  235. static void acp63_audio_remove(struct platform_device *pdev)
  236. {
  237. struct device *dev = &pdev->dev;
  238. struct acp_dev_data *adata = dev_get_drvdata(dev);
  239. acp_disable_interrupts(adata);
  240. acp_platform_unregister(dev);
  241. pm_runtime_disable(&pdev->dev);
  242. }
  243. static int __maybe_unused acp63_pcm_resume(struct device *dev)
  244. {
  245. struct acp_dev_data *adata = dev_get_drvdata(dev);
  246. struct acp_stream *stream;
  247. struct snd_pcm_substream *substream;
  248. snd_pcm_uframes_t buf_in_frames;
  249. u64 buf_size;
  250. if (adata->is_i2s_config && adata->rsrc->soc_mclk)
  251. acp63_i2s_master_clock_generate(adata);
  252. spin_lock(&adata->acp_lock);
  253. list_for_each_entry(stream, &adata->stream_list, list) {
  254. substream = stream->substream;
  255. if (substream && substream->runtime) {
  256. buf_in_frames = (substream->runtime->buffer_size);
  257. buf_size = frames_to_bytes(substream->runtime, buf_in_frames);
  258. config_pte_for_stream(adata, stream);
  259. config_acp_dma(adata, stream, buf_size);
  260. if (stream->dai_id)
  261. restore_acp_i2s_params(substream, adata, stream);
  262. else
  263. restore_acp_pdm_params(substream, adata);
  264. }
  265. }
  266. spin_unlock(&adata->acp_lock);
  267. return 0;
  268. }
  269. static const struct dev_pm_ops acp63_dma_pm_ops = {
  270. SET_SYSTEM_SLEEP_PM_OPS(NULL, acp63_pcm_resume)
  271. };
  272. static struct platform_driver acp63_driver = {
  273. .probe = acp63_audio_probe,
  274. .remove = acp63_audio_remove,
  275. .driver = {
  276. .name = "acp_asoc_acp63",
  277. .pm = &acp63_dma_pm_ops,
  278. },
  279. };
  280. module_platform_driver(acp63_driver);
  281. MODULE_DESCRIPTION("AMD ACP acp63 Driver");
  282. MODULE_IMPORT_NS(SND_SOC_ACP_COMMON);
  283. MODULE_LICENSE("Dual BSD/GPL");
  284. MODULE_ALIAS("platform:" DRV_NAME);