ark1668ed_i2s.c 15 KB

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  1. /*
  2. * ark1668ed_i2s.c -- ALSA SoC Audio Layer
  3. */
  4. #include <linux/module.h>
  5. #include <linux/platform_device.h>
  6. #include <linux/dmaengine.h>
  7. #include <linux/slab.h>
  8. #include <sound/core.h>
  9. #include <sound/pcm.h>
  10. #include <sound/pcm_params.h>
  11. #include <sound/soc.h>
  12. #include <sound/dmaengine_pcm.h>
  13. #include <linux/clk.h>
  14. #include <linux/dma-mapping.h>
  15. #include "ark1668ed_i2s.h"
  16. #define DRV_NAME "ark1668ed-i2s"
  17. /* 平台私有数据结构 */
  18. struct ark1668ed_i2s_priv {
  19. struct device *dev;
  20. struct clk *clk;
  21. void __iomem *base;
  22. int irq;
  23. u32 nco_reg;
  24. u32 adc_nco_reg;
  25. int master;
  26. u32 fmt;
  27. int full_duplex_en;
  28. u32 index; // I2S控制器索引
  29. struct dma_chan *tx_chan;
  30. struct dma_chan *rx_chan;
  31. dma_addr_t dma_addr;
  32. struct snd_dmaengine_dai_dma_data playback_dma_data;
  33. struct snd_dmaengine_dai_dma_data capture_dma_data;
  34. bool has_capture;
  35. bool has_playback;
  36. //struct snd_soc_component_driver component_driver;
  37. };
  38. //static void i2s_enable(struct ark1668ed_i2s_priv *priv)
  39. //{
  40. // dev_info(priv->dev, "I2S-%d enabled\n", priv->index);
  41. //}
  42. //static void i2s_disable(struct ark1668ed_i2s_priv *priv)
  43. //{
  44. // dev_info(priv->dev, "I2S-%d disabled\n", priv->index);
  45. //}
  46. static irqreturn_t ark1668ed_irq_handler(int irq, void *dev_id)
  47. {
  48. struct ark1668ed_i2s_priv *i2s = dev_id;
  49. //uint32_t val;
  50. u32 status;
  51. status = readl(i2s->base + I2S_SASR0);
  52. writel(0xFF, i2s->base + I2S_SAICR);
  53. //writel(status, i2s->base + I2S_SAICR);
  54. writel(0, i2s->base + I2S_SAICR);
  55. // /* interrupt clear */
  56. // writel(0xFFFFFFFF, i2s->base + I2S_SAICR);
  57. // writel(0, i2s->base + I2S_SAICR);
  58. // /* interrupt enable */
  59. // val = readl(i2s->base + I2S_SAIMR);
  60. // val |= (SAIMR_TFS | SAIMR_TUR | SAIMR_ROR | SAIMR_RFS);
  61. // printk("+++++++%s,%d:val = 0x%x\n",__func__,__LINE__,val);
  62. // writel(val, i2s->base + I2S_SAIMR);
  63. return IRQ_HANDLED;
  64. }
  65. static int ark1668ed_i2s_probe(struct snd_soc_dai *dai)
  66. {
  67. struct ark1668ed_i2s_priv *i2s = snd_soc_dai_get_drvdata(dai);
  68. snd_soc_dai_init_dma_data(dai,
  69. i2s->has_playback ? &i2s->playback_dma_data : NULL,
  70. i2s->has_capture ? &i2s->capture_dma_data : NULL);
  71. // dai->capture_dma_data = &i2s->capture_dma_data;
  72. // dai->playback_dma_data = &i2s->playback_dma_data;
  73. return 0;
  74. }
  75. static int ark1668ed_i2s_startup(
  76. struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
  77. {
  78. struct ark1668ed_i2s_priv *i2s = snd_soc_dai_get_drvdata(dai);
  79. //struct snd_dmaengine_dai_dma_data *dma_data;
  80. uint32_t val = 0;
  81. if (readl(i2s->base + I2S_SACR0) & SACR0_ENB)
  82. return 0;
  83. /* reset */
  84. writel(SACR0_RST, i2s->base + I2S_SACR0);
  85. udelay(1);
  86. writel(0, i2s->base + I2S_SACR0);
  87. if (i2s->full_duplex_en) {
  88. val = SACR0_TFIFOFIRSTBIT | SACR0_CHANLOCK | SACR0_TFTH(14) | SACR0_TDMAEN;
  89. val |= SACR0_RFIFIFIRSTBIT | SACR0_CHANLOCK | SACR0_RFTH(17) | SACR0_RDMAEN;
  90. //printk("####################i2s->master = %d\n",i2s->master);
  91. if (i2s->master)
  92. val |= SACR0_BCKD | SACR0_SYNCD;
  93. else
  94. val &= ~(SACR0_BCKD | SACR0_SYNCD);
  95. writel(val, i2s->base + I2S_SACR0);
  96. val = readl(i2s->base + I2S_SACR1);
  97. val &= ~(SACR1_DRPL_DAT | SACR1_DREC_DAT | SACR1_TDMENB);
  98. writel(val, i2s->base + I2S_SACR1);
  99. writel(0x7f, i2s->base + I2S_SAICR);
  100. writel(0, i2s->base + I2S_SAICR);
  101. } else {
  102. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  103. val = SACR0_TFIFOFIRSTBIT | SACR0_CHANLOCK | SACR0_TFTH(14) | SACR0_TDMAEN;
  104. //printk("PLAYBACK####################i2s->master = %d\n",i2s->master);
  105. if (i2s->master)
  106. val |= SACR0_BCKD | SACR0_SYNCD;
  107. else
  108. val &= ~(SACR0_BCKD | SACR0_SYNCD);
  109. writel(val, i2s->base + I2S_SACR0);
  110. val = readl(i2s->base + I2S_SACR1);
  111. val &= ~(SACR1_DRPL_DAT | SACR1_TDMENB);
  112. writel(val, i2s->base + I2S_SACR1);
  113. writel(0x7f, i2s->base + I2S_SAICR);
  114. writel(0, i2s->base + I2S_SAICR);
  115. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  116. val = SACR0_RFIFIFIRSTBIT | SACR0_CHANLOCK | SACR0_RFTH(17) | SACR0_RDMAEN;
  117. //printk("CAPTURE####################i2s->master = %d\n",i2s->master);
  118. if (i2s->master)
  119. val |= SACR0_BCKD | SACR0_SYNCD;
  120. else
  121. val &= ~(SACR0_BCKD | SACR0_SYNCD);
  122. writel(val, i2s->base + I2S_SACR0);
  123. val = readl(i2s->base + I2S_SACR1);
  124. val &= ~(SACR1_DREC_DAT | SACR1_TDMENB);
  125. writel(val, i2s->base + I2S_SACR1);
  126. writel(0x7f, i2s->base + I2S_SAICR);
  127. writel(0, i2s->base + I2S_SAICR);
  128. }
  129. }
  130. udelay(1);
  131. // val = readl(i2s->base + I2S_SACR0);
  132. // val &= ~SACR0_CHANLOCK;
  133. // writel(val, i2s->base + I2S_SACR0);
  134. //snd_soc_dai_set_dma_data(dai, substream, dma_data);
  135. return 0;
  136. }
  137. static int ark1668ed_hw_params(struct snd_pcm_substream *substream,
  138. struct snd_pcm_hw_params *params,
  139. struct snd_soc_dai *dai)
  140. {
  141. //struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
  142. struct ark1668ed_i2s_priv *i2s = snd_soc_dai_get_drvdata(dai);
  143. //struct dma_chan *chan = snd_dmaengine_pcm_get_chan(substream);
  144. u32 rate = params_rate(params);
  145. u32 step = 256 * 2, modulo;
  146. u32 freq;
  147. u32 val;
  148. void *sysreg;
  149. //int ret;
  150. int channels = params_channels(params);
  151. int width = snd_pcm_format_physical_width(params_format(params));
  152. dev_info(i2s->dev, "Configuring stream: %s, %d channels, %d-bit\n",
  153. substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "Playback" : "Capture",
  154. channels, width);
  155. if ((!i2s->nco_reg) || (!i2s->adc_nco_reg))
  156. return 0;
  157. /* mclk = rate * 256, mclk = freq * step / (2 * modulo) */
  158. freq = clk_get_rate(i2s->clk);
  159. modulo = freq / rate;
  160. val = (step << 16) | modulo;
  161. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  162. //printk("##############i2s->nco_reg = 0x%x\n",i2s->nco_reg);
  163. sysreg = ioremap(i2s->nco_reg, 0x10);
  164. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  165. //printk("##############i2s->adc_nco_reg = 0x%x\n",i2s->adc_nco_reg);
  166. sysreg = ioremap(i2s->adc_nco_reg, 0x10);
  167. }
  168. if (sysreg) {
  169. writel(val, sysreg);
  170. iounmap(sysreg);
  171. }
  172. //mdelay(1);
  173. // 设置采样率、位深、通道数等
  174. val = readl(i2s->base + I2S_SACR0);
  175. switch (params_format(params)) {
  176. case SNDRV_PCM_FORMAT_S16_LE:
  177. //printk("##############SNDRV_PCM_FORMAT_S16_LE\n");
  178. val &= ~SACR0_32BIT_MODE;
  179. //val &= ~(SACR0_RFTH_MASK | SACR0_TFTH_MASK);
  180. //val |= SACR0_TFTH(7) | SACR0_RFTH(8);
  181. break;
  182. case SNDRV_PCM_FORMAT_S24_LE:
  183. case SNDRV_PCM_FORMAT_S32_LE:
  184. //printk("##############SNDRV_PCM_FORMAT_S32_LE\n");
  185. val |= SACR0_32BIT_MODE;
  186. val &= ~(SACR0_RFTH_MASK | SACR0_TFTH_MASK);
  187. val |= SACR0_TFTH(7) | SACR0_RFTH(8);
  188. break;
  189. default:
  190. return -EINVAL;
  191. }
  192. if ((channels > 0) && (channels <= 2)) {
  193. val |= (1 << 29);
  194. } else if ((channels > 2) && (channels <= 4)) {
  195. val |= (2 << 29);
  196. } else if ((channels > 4) && (channels <= 6)) {
  197. val |= (3 << 29);
  198. }
  199. //if (channels % 2)
  200. if (params_channels(params) == 1)
  201. val |= SACR0_SCBIT;
  202. else
  203. val &= ~SACR0_SCBIT;
  204. val &= ~SACR0_SAMERATE_ENB;
  205. writel(val, i2s->base + I2S_SACR0);
  206. val = readl(i2s->base + I2S_WRCTL);
  207. val &= ~(0xffffffff);
  208. val |= ((1 << 0) | (2 << 8) | (3 << 16));
  209. writel((1 << 0) | (2 << 8) | (3 << 16), i2s->base + I2S_WRCTL);
  210. val = readl(i2s->base + I2S_RDCTL);
  211. val &= ~(0xffffffff);
  212. val |= ((1 << 0) | (2 << 8) | (3 << 16));
  213. writel((1 << 0) | (2 << 8) | (3 << 16), i2s->base + I2S_RDCTL);
  214. //printk("################\n");
  215. return 0;
  216. }
  217. static int ark1668ed_trigger(struct snd_pcm_substream *substream,
  218. int cmd, struct snd_soc_dai *dai)
  219. {
  220. struct ark1668ed_i2s_priv *i2s = snd_soc_dai_get_drvdata(dai);
  221. //pr_info("DMA buffer req size: %zu,align=%d\n", substream->runtime->dma_bytes, dma_get_cache_alignment());
  222. if (!substream->runtime->dma_area) {
  223. printk("DMA buffer not allocated!");
  224. return -ENOMEM;
  225. }
  226. switch (cmd) {
  227. case SNDRV_PCM_TRIGGER_START:
  228. case SNDRV_PCM_TRIGGER_RESUME:
  229. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  230. dev_info(i2s->dev, "Start stream: %s\n",
  231. substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "Playback" : "Capture");
  232. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  233. writel(readl(i2s->base + I2S_SACR1) & ~SACR1_DRPL, i2s->base + I2S_SACR1);
  234. } else {
  235. writel(readl(i2s->base + I2S_SACR1) & ~SACR1_DREC, i2s->base + I2S_SACR1);
  236. }
  237. writel(readl(i2s->base + I2S_SACR0) | SACR0_ENB, i2s->base + I2S_SACR0);
  238. break;
  239. case SNDRV_PCM_TRIGGER_STOP:
  240. case SNDRV_PCM_TRIGGER_SUSPEND:
  241. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  242. // dev_info(i2s->dev, "Stop stream: %s\n",
  243. // substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "Playback" : "Capture");
  244. // if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  245. // writel(readl(i2s->base + I2S_SACR1) | SACR1_DRPL, i2s->base + I2S_SACR1);
  246. // else
  247. // writel(readl(i2s->base + I2S_SACR1) | SACR1_DREC, i2s->base + I2S_SACR1);
  248. // writel(readl(i2s->base + I2S_SACR0) & ~SACR0_ENB, i2s->base + I2S_SACR0);
  249. break;
  250. default:
  251. return -EINVAL;
  252. }
  253. return 0;
  254. }
  255. static int ark1668ed_i2s_set_fmt(
  256. struct snd_soc_dai *dai, unsigned int fmt)
  257. {//printk("#########%s(%d)\n", __func__, __LINE__);
  258. struct ark1668ed_i2s_priv *i2s = snd_soc_dai_get_drvdata(dai);
  259. /* 设置数据格式 */
  260. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  261. case SND_SOC_DAIFMT_I2S:
  262. i2s->fmt = 0;
  263. break;
  264. case SND_SOC_DAIFMT_RIGHT_J:
  265. break;
  266. case SND_SOC_DAIFMT_LEFT_J:
  267. break;
  268. case SND_SOC_DAIFMT_DSP_A:
  269. break;
  270. case SND_SOC_DAIFMT_DSP_B:
  271. break;
  272. default:
  273. return -EINVAL;
  274. }
  275. switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  276. case SND_SOC_DAIFMT_BP_FP:
  277. printk("######### i2s master#########\n");
  278. i2s->master = 1;
  279. break;
  280. case SND_SOC_DAIFMT_BC_FC:
  281. printk("#########i2s slave#########\n");
  282. i2s->master = 0;
  283. break;
  284. default:
  285. return -EINVAL;
  286. }
  287. return 0;
  288. }
  289. /* I2S supported rate and format */
  290. #define ARK1668ED_I2S_RATES \
  291. (SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
  292. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
  293. SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
  294. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 | SNDRV_PCM_RATE_8000)
  295. static const struct snd_soc_dai_ops ark1668ed_dai_ops = {
  296. .probe = ark1668ed_i2s_probe,
  297. .startup = ark1668ed_i2s_startup,
  298. .hw_params = ark1668ed_hw_params,
  299. .trigger = ark1668ed_trigger,
  300. .set_fmt = ark1668ed_i2s_set_fmt,
  301. };
  302. static struct snd_soc_dai_driver ark1668ed_dai = {
  303. .name = "ark1668ed-i2s",
  304. .playback = {
  305. .stream_name = "Playback",
  306. .channels_min = 1,
  307. .channels_max = 2,
  308. .rates = ARK1668ED_I2S_RATES,
  309. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  310. SNDRV_PCM_FMTBIT_S24_LE |
  311. SNDRV_PCM_FMTBIT_S32_LE,
  312. },
  313. .capture = {
  314. .stream_name = "Capture",
  315. .channels_min = 1,
  316. .channels_max = 2,
  317. .rates = ARK1668ED_I2S_RATES,
  318. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  319. SNDRV_PCM_FMTBIT_S24_LE |
  320. SNDRV_PCM_FMTBIT_S32_LE,
  321. },
  322. .ops = &ark1668ed_dai_ops,
  323. .symmetric_rate = 1,
  324. };
  325. static struct snd_pcm_hardware ark1668ed_pcm_hardware = {
  326. .info = (SNDRV_PCM_INFO_MMAP |
  327. SNDRV_PCM_INFO_MMAP_VALID |
  328. SNDRV_PCM_INFO_PAUSE |
  329. SNDRV_PCM_INFO_RESUME |
  330. SNDRV_PCM_INFO_INTERLEAVED |
  331. SNDRV_PCM_INFO_BLOCK_TRANSFER),
  332. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
  333. SNDRV_PCM_FMTBIT_S32_LE,
  334. .rates = (SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 |
  335. SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 |
  336. SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
  337. SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 |
  338. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
  339. SNDRV_PCM_RATE_192000 | SNDRV_PCM_RATE_8000),
  340. .rate_min = 8000,
  341. .rate_max = 192000,
  342. .channels_min = 1,
  343. .channels_max = 2,
  344. .buffer_bytes_max = 128 * 1024,
  345. .period_bytes_min = 64,
  346. .period_bytes_max = 64 * 1024,//(0xfff & ~0x3)
  347. .periods_min = 2,
  348. .periods_max = 64,
  349. .fifo_size = 32,
  350. };
  351. static const struct snd_dmaengine_pcm_config
  352. ark1668ed_i2s_dmaengine_pcm_config = {
  353. .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
  354. .pcm_hardware = &ark1668ed_pcm_hardware,
  355. };
  356. static const struct snd_soc_component_driver ark1668ed_i2s_component = {
  357. .name = DRV_NAME,
  358. .legacy_dai_naming = 1,
  359. };
  360. static int ark1668ed_i2s_drv_probe(struct platform_device *pdev)
  361. {
  362. struct ark1668ed_i2s_priv *i2s;
  363. struct device_node *np = pdev->dev.of_node;
  364. //struct snd_dmaengine_pcm_config *dmaengine_cfg;
  365. struct resource *res;
  366. u32 val;
  367. int ret;
  368. //struct snd_soc_dai_driver *dai;
  369. i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
  370. if (!i2s)
  371. return -ENOMEM;
  372. i2s->dev = &pdev->dev;
  373. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  374. i2s->base = devm_ioremap_resource(&pdev->dev, res);
  375. if (IS_ERR(i2s->base))
  376. return PTR_ERR(i2s->base);
  377. i2s->dma_addr = res->start;
  378. if (!of_property_read_u32(pdev->dev.of_node, "nco-reg", &val))
  379. i2s->nco_reg = val;
  380. if (!of_property_read_u32(pdev->dev.of_node, "adc-nco-reg", &val))
  381. i2s->adc_nco_reg = val;
  382. if (of_property_read_bool(pdev->dev.of_node, "full-duplex-mode"))
  383. i2s->full_duplex_en = 1;
  384. //printk(">>>>>>>>>>>>>>>>>>i2s->full_duplex_en = %d\n",i2s->full_duplex_en);
  385. i2s->clk = of_clk_get(pdev->dev.of_node, 0);
  386. if (IS_ERR(i2s->clk))
  387. return PTR_ERR(i2s->clk);
  388. i2s->irq = platform_get_irq(pdev, 0);
  389. if (i2s->irq < 0)
  390. return i2s->irq;
  391. ret = devm_request_irq(&pdev->dev, i2s->irq, ark1668ed_irq_handler,
  392. IRQF_SHARED, DRV_NAME, i2s);
  393. if (ret) {
  394. dev_err(&pdev->dev, "Failed to request IRQ: %d\n", ret);
  395. return ret;
  396. }
  397. ret = of_property_read_u32(np, "index", &i2s->index);
  398. if (ret) {
  399. //dev_info(&pdev->dev, "Using calculated index: %u\n", i2s->index);
  400. } else {
  401. //dev_info(&pdev->dev, "Using device tree index: %u\n", i2s->index);
  402. }
  403. ark1668ed_dai.id = i2s->index;
  404. struct property *dma_names;
  405. const char *dma_name;
  406. struct device_node *node = i2s->dev->of_node;
  407. of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
  408. if (!strcmp(dma_name, "tx")) {
  409. i2s->has_playback = true; }
  410. if (!strcmp(dma_name, "rx")) {
  411. i2s->has_capture = true; }
  412. }
  413. i2s->playback_dma_data.addr = res->start + I2S_SADR;
  414. i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  415. i2s->playback_dma_data.maxburst = 16;
  416. i2s->capture_dma_data.addr = res->start + I2S_SADR;
  417. i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  418. i2s->capture_dma_data.maxburst = 16;
  419. ret = devm_snd_soc_register_component(&pdev->dev,
  420. &ark1668ed_i2s_component,
  421. &ark1668ed_dai, 1);
  422. if (ret) {
  423. printk(">>>>>>>Failed to register DAI: %d\n", ret);
  424. return ret;
  425. }
  426. platform_set_drvdata(pdev, i2s);
  427. ret = devm_snd_dmaengine_pcm_register(&pdev->dev, &ark1668ed_i2s_dmaengine_pcm_config, 0);
  428. if (ret) {
  429. dev_err(&pdev->dev, "Failed to register PCM: %d\n", ret);
  430. return ret;
  431. }
  432. dev_info(&pdev->dev, "Virtual Platform Driver probed successfully\n");
  433. return 0;
  434. }
  435. static const struct of_device_id ark1668ed_match[] = {
  436. { .compatible = "arkmicro,ark1668ed-i2s", },
  437. {}
  438. };
  439. MODULE_DEVICE_TABLE(of, ark1668ed_match);
  440. static struct platform_driver ark1668ed_driver = {
  441. .probe = ark1668ed_i2s_drv_probe,
  442. .driver = {
  443. .name = DRV_NAME,
  444. .of_match_table = ark1668ed_match,
  445. },
  446. };
  447. module_platform_driver(ark1668ed_driver);
  448. MODULE_AUTHOR("ark");
  449. MODULE_DESCRIPTION("Virtual Platform Driver for Linux 6.12.116");
  450. MODULE_LICENSE("GPL");
  451. MODULE_ALIAS("platform:" DRV_NAME);