fsl_aud2htx.h 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright 2020 NXP
  4. */
  5. #ifndef _FSL_AUD2HTX_H
  6. #define _FSL_AUD2HTX_H
  7. #define FSL_AUD2HTX_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
  8. SNDRV_PCM_FMTBIT_S32_LE)
  9. /* AUD2HTX Register Map */
  10. #define AUD2HTX_CTRL 0x0 /* AUD2HTX Control Register */
  11. #define AUD2HTX_CTRL_EXT 0x4 /* AUD2HTX Control Extended Register */
  12. #define AUD2HTX_WR 0x8 /* AUD2HTX Write Register */
  13. #define AUD2HTX_STATUS 0xC /* AUD2HTX Status Register */
  14. #define AUD2HTX_IRQ_NOMASK 0x10 /* AUD2HTX Nonmasked Interrupt Flags Register */
  15. #define AUD2HTX_IRQ_MASKED 0x14 /* AUD2HTX Masked Interrupt Flags Register */
  16. #define AUD2HTX_IRQ_MASK 0x18 /* AUD2HTX IRQ Masks Register */
  17. /* AUD2HTX Control Register */
  18. #define AUD2HTX_CTRL_EN BIT(0)
  19. /* AUD2HTX Control Extended Register */
  20. #define AUD2HTX_CTRE_DE BIT(0)
  21. #define AUD2HTX_CTRE_DT_SHIFT 0x1
  22. #define AUD2HTX_CTRE_DT_WIDTH 0x2
  23. #define AUD2HTX_CTRE_DT_MASK ((BIT(AUD2HTX_CTRE_DT_WIDTH) - 1) \
  24. << AUD2HTX_CTRE_DT_SHIFT)
  25. #define AUD2HTX_CTRE_WL_SHIFT 16
  26. #define AUD2HTX_CTRE_WL_WIDTH 5
  27. #define AUD2HTX_CTRE_WL_MASK ((BIT(AUD2HTX_CTRE_WL_WIDTH) - 1) \
  28. << AUD2HTX_CTRE_WL_SHIFT)
  29. #define AUD2HTX_CTRE_WH_SHIFT 24
  30. #define AUD2HTX_CTRE_WH_WIDTH 5
  31. #define AUD2HTX_CTRE_WH_MASK ((BIT(AUD2HTX_CTRE_WH_WIDTH) - 1) \
  32. << AUD2HTX_CTRE_WH_SHIFT)
  33. /* AUD2HTX IRQ Masks Register */
  34. #define AUD2HTX_WM_HIGH_IRQ_MASK BIT(2)
  35. #define AUD2HTX_WM_LOW_IRQ_MASK BIT(1)
  36. #define AUD2HTX_OVF_MASK BIT(0)
  37. #define AUD2HTX_FIFO_DEPTH 0x20
  38. #define AUD2HTX_WTMK_LOW 0x10
  39. #define AUD2HTX_WTMK_HIGH 0x10
  40. #define AUD2HTX_MAXBURST 0x10
  41. /**
  42. * fsl_aud2htx: AUD2HTX private data
  43. *
  44. * @pdev: platform device pointer
  45. * @regmap: regmap handler
  46. * @bus_clk: clock source to access register
  47. * @dma_params_rx: DMA parameters for receive channel
  48. * @dma_params_tx: DMA parameters for transmit channel
  49. */
  50. struct fsl_aud2htx {
  51. struct platform_device *pdev;
  52. struct regmap *regmap;
  53. struct clk *bus_clk;
  54. struct snd_dmaengine_dai_dma_data dma_params_rx;
  55. struct snd_dmaengine_dai_dma_data dma_params_tx;
  56. };
  57. #endif /* _FSL_AUD2HTX_H */