lpass-apq8016.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
  4. *
  5. * lpass-apq8016.c -- ALSA SoC CPU DAI driver for APQ8016 LPASS
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/device.h>
  9. #include <linux/err.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/platform_device.h>
  14. #include <sound/pcm.h>
  15. #include <sound/pcm_params.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dai.h>
  18. #include <dt-bindings/sound/apq8016-lpass.h>
  19. #include "lpass-lpaif-reg.h"
  20. #include "lpass.h"
  21. static struct snd_soc_dai_driver apq8016_lpass_cpu_dai_driver[] = {
  22. [MI2S_PRIMARY] = {
  23. .id = MI2S_PRIMARY,
  24. .name = "Primary MI2S",
  25. .playback = {
  26. .stream_name = "Primary Playback",
  27. .formats = SNDRV_PCM_FMTBIT_S16 |
  28. SNDRV_PCM_FMTBIT_S24 |
  29. SNDRV_PCM_FMTBIT_S32,
  30. .rates = SNDRV_PCM_RATE_8000 |
  31. SNDRV_PCM_RATE_16000 |
  32. SNDRV_PCM_RATE_32000 |
  33. SNDRV_PCM_RATE_48000 |
  34. SNDRV_PCM_RATE_96000,
  35. .rate_min = 8000,
  36. .rate_max = 96000,
  37. .channels_min = 1,
  38. .channels_max = 8,
  39. },
  40. .ops = &asoc_qcom_lpass_cpu_dai_ops,
  41. },
  42. [MI2S_SECONDARY] = {
  43. .id = MI2S_SECONDARY,
  44. .name = "Secondary MI2S",
  45. .playback = {
  46. .stream_name = "Secondary Playback",
  47. .formats = SNDRV_PCM_FMTBIT_S16 |
  48. SNDRV_PCM_FMTBIT_S24 |
  49. SNDRV_PCM_FMTBIT_S32,
  50. .rates = SNDRV_PCM_RATE_8000 |
  51. SNDRV_PCM_RATE_16000 |
  52. SNDRV_PCM_RATE_32000 |
  53. SNDRV_PCM_RATE_48000 |
  54. SNDRV_PCM_RATE_96000,
  55. .rate_min = 8000,
  56. .rate_max = 96000,
  57. .channels_min = 1,
  58. .channels_max = 8,
  59. },
  60. .ops = &asoc_qcom_lpass_cpu_dai_ops,
  61. },
  62. [MI2S_TERTIARY] = {
  63. .id = MI2S_TERTIARY,
  64. .name = "Tertiary MI2S",
  65. .capture = {
  66. .stream_name = "Tertiary Capture",
  67. .formats = SNDRV_PCM_FMTBIT_S16 |
  68. SNDRV_PCM_FMTBIT_S24 |
  69. SNDRV_PCM_FMTBIT_S32,
  70. .rates = SNDRV_PCM_RATE_8000 |
  71. SNDRV_PCM_RATE_16000 |
  72. SNDRV_PCM_RATE_32000 |
  73. SNDRV_PCM_RATE_48000 |
  74. SNDRV_PCM_RATE_96000,
  75. .rate_min = 8000,
  76. .rate_max = 96000,
  77. .channels_min = 1,
  78. .channels_max = 8,
  79. },
  80. .ops = &asoc_qcom_lpass_cpu_dai_ops,
  81. },
  82. [MI2S_QUATERNARY] = {
  83. .id = MI2S_QUATERNARY,
  84. .name = "Quatenary MI2S",
  85. .playback = {
  86. .stream_name = "Quatenary Playback",
  87. .formats = SNDRV_PCM_FMTBIT_S16 |
  88. SNDRV_PCM_FMTBIT_S24 |
  89. SNDRV_PCM_FMTBIT_S32,
  90. .rates = SNDRV_PCM_RATE_8000 |
  91. SNDRV_PCM_RATE_16000 |
  92. SNDRV_PCM_RATE_32000 |
  93. SNDRV_PCM_RATE_48000 |
  94. SNDRV_PCM_RATE_96000,
  95. .rate_min = 8000,
  96. .rate_max = 96000,
  97. .channels_min = 1,
  98. .channels_max = 8,
  99. },
  100. .capture = {
  101. .stream_name = "Quatenary Capture",
  102. .formats = SNDRV_PCM_FMTBIT_S16 |
  103. SNDRV_PCM_FMTBIT_S24 |
  104. SNDRV_PCM_FMTBIT_S32,
  105. .rates = SNDRV_PCM_RATE_8000 |
  106. SNDRV_PCM_RATE_16000 |
  107. SNDRV_PCM_RATE_32000 |
  108. SNDRV_PCM_RATE_48000 |
  109. SNDRV_PCM_RATE_96000,
  110. .rate_min = 8000,
  111. .rate_max = 96000,
  112. .channels_min = 1,
  113. .channels_max = 8,
  114. },
  115. .ops = &asoc_qcom_lpass_cpu_dai_ops,
  116. },
  117. };
  118. static int apq8016_lpass_alloc_dma_channel(struct lpass_data *drvdata,
  119. int direction, unsigned int dai_id)
  120. {
  121. const struct lpass_variant *v = drvdata->variant;
  122. int chan = 0;
  123. if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
  124. chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
  125. v->rdma_channels);
  126. if (chan >= v->rdma_channels)
  127. return -EBUSY;
  128. } else {
  129. chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
  130. v->wrdma_channel_start +
  131. v->wrdma_channels,
  132. v->wrdma_channel_start);
  133. if (chan >= v->wrdma_channel_start + v->wrdma_channels)
  134. return -EBUSY;
  135. }
  136. set_bit(chan, &drvdata->dma_ch_bit_map);
  137. return chan;
  138. }
  139. static int apq8016_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
  140. {
  141. clear_bit(chan, &drvdata->dma_ch_bit_map);
  142. return 0;
  143. }
  144. static int apq8016_lpass_init(struct platform_device *pdev)
  145. {
  146. struct lpass_data *drvdata = platform_get_drvdata(pdev);
  147. const struct lpass_variant *variant = drvdata->variant;
  148. struct device *dev = &pdev->dev;
  149. int ret, i;
  150. drvdata->clks = devm_kcalloc(dev, variant->num_clks,
  151. sizeof(*drvdata->clks), GFP_KERNEL);
  152. if (!drvdata->clks)
  153. return -ENOMEM;
  154. drvdata->num_clks = variant->num_clks;
  155. for (i = 0; i < drvdata->num_clks; i++)
  156. drvdata->clks[i].id = variant->clk_name[i];
  157. ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
  158. if (ret) {
  159. dev_err(dev, "Failed to get clocks %d\n", ret);
  160. return ret;
  161. }
  162. ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
  163. if (ret) {
  164. dev_err(dev, "apq8016 clk_enable failed\n");
  165. return ret;
  166. }
  167. drvdata->ahbix_clk = devm_clk_get(dev, "ahbix-clk");
  168. if (IS_ERR(drvdata->ahbix_clk)) {
  169. dev_err(dev, "error getting ahbix-clk: %ld\n",
  170. PTR_ERR(drvdata->ahbix_clk));
  171. ret = PTR_ERR(drvdata->ahbix_clk);
  172. goto err_ahbix_clk;
  173. }
  174. ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY);
  175. if (ret) {
  176. dev_err(dev, "error setting rate on ahbix_clk: %d\n", ret);
  177. goto err_ahbix_clk;
  178. }
  179. dev_dbg(dev, "set ahbix_clk rate to %lu\n",
  180. clk_get_rate(drvdata->ahbix_clk));
  181. ret = clk_prepare_enable(drvdata->ahbix_clk);
  182. if (ret) {
  183. dev_err(dev, "error enabling ahbix_clk: %d\n", ret);
  184. goto err_ahbix_clk;
  185. }
  186. return 0;
  187. err_ahbix_clk:
  188. clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
  189. return ret;
  190. }
  191. static int apq8016_lpass_exit(struct platform_device *pdev)
  192. {
  193. struct lpass_data *drvdata = platform_get_drvdata(pdev);
  194. clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
  195. clk_disable_unprepare(drvdata->ahbix_clk);
  196. return 0;
  197. }
  198. static const struct lpass_variant apq8016_data = {
  199. .i2sctrl_reg_base = 0x1000,
  200. .i2sctrl_reg_stride = 0x1000,
  201. .i2s_ports = 4,
  202. .irq_reg_base = 0x6000,
  203. .irq_reg_stride = 0x1000,
  204. .irq_ports = 3,
  205. .rdma_reg_base = 0x8400,
  206. .rdma_reg_stride = 0x1000,
  207. .rdma_channels = 2,
  208. .dmactl_audif_start = 1,
  209. .wrdma_reg_base = 0xB000,
  210. .wrdma_reg_stride = 0x1000,
  211. .wrdma_channel_start = 5,
  212. .wrdma_channels = 2,
  213. .loopback = REG_FIELD_ID(0x1000, 15, 15, 4, 0x1000),
  214. .spken = REG_FIELD_ID(0x1000, 14, 14, 4, 0x1000),
  215. .spkmode = REG_FIELD_ID(0x1000, 10, 13, 4, 0x1000),
  216. .spkmono = REG_FIELD_ID(0x1000, 9, 9, 4, 0x1000),
  217. .micen = REG_FIELD_ID(0x1000, 8, 8, 4, 0x1000),
  218. .micmode = REG_FIELD_ID(0x1000, 4, 7, 4, 0x1000),
  219. .micmono = REG_FIELD_ID(0x1000, 3, 3, 4, 0x1000),
  220. .wssrc = REG_FIELD_ID(0x1000, 2, 2, 4, 0x1000),
  221. .bitwidth = REG_FIELD_ID(0x1000, 0, 1, 4, 0x1000),
  222. .rdma_dyncclk = REG_FIELD_ID(0x8400, 12, 12, 2, 0x1000),
  223. .rdma_bursten = REG_FIELD_ID(0x8400, 11, 11, 2, 0x1000),
  224. .rdma_wpscnt = REG_FIELD_ID(0x8400, 8, 10, 2, 0x1000),
  225. .rdma_intf = REG_FIELD_ID(0x8400, 4, 7, 2, 0x1000),
  226. .rdma_fifowm = REG_FIELD_ID(0x8400, 1, 3, 2, 0x1000),
  227. .rdma_enable = REG_FIELD_ID(0x8400, 0, 0, 2, 0x1000),
  228. .wrdma_dyncclk = REG_FIELD_ID(0xB000, 12, 12, 2, 0x1000),
  229. .wrdma_bursten = REG_FIELD_ID(0xB000, 11, 11, 2, 0x1000),
  230. .wrdma_wpscnt = REG_FIELD_ID(0xB000, 8, 10, 2, 0x1000),
  231. .wrdma_intf = REG_FIELD_ID(0xB000, 4, 7, 2, 0x1000),
  232. .wrdma_fifowm = REG_FIELD_ID(0xB000, 1, 3, 2, 0x1000),
  233. .wrdma_enable = REG_FIELD_ID(0xB000, 0, 0, 2, 0x1000),
  234. .clk_name = (const char*[]) {
  235. "pcnoc-mport-clk",
  236. "pcnoc-sway-clk",
  237. },
  238. .num_clks = 2,
  239. .dai_driver = apq8016_lpass_cpu_dai_driver,
  240. .num_dai = ARRAY_SIZE(apq8016_lpass_cpu_dai_driver),
  241. .dai_osr_clk_names = (const char *[]) {
  242. "mi2s-osr-clk0",
  243. "mi2s-osr-clk1",
  244. "mi2s-osr-clk2",
  245. "mi2s-osr-clk3",
  246. },
  247. .dai_bit_clk_names = (const char *[]) {
  248. "mi2s-bit-clk0",
  249. "mi2s-bit-clk1",
  250. "mi2s-bit-clk2",
  251. "mi2s-bit-clk3",
  252. },
  253. .init = apq8016_lpass_init,
  254. .exit = apq8016_lpass_exit,
  255. .alloc_dma_channel = apq8016_lpass_alloc_dma_channel,
  256. .free_dma_channel = apq8016_lpass_free_dma_channel,
  257. };
  258. static const struct of_device_id apq8016_lpass_cpu_device_id[] __maybe_unused = {
  259. { .compatible = "qcom,lpass-cpu-apq8016", .data = &apq8016_data },
  260. { .compatible = "qcom,apq8016-lpass-cpu", .data = &apq8016_data },
  261. {}
  262. };
  263. MODULE_DEVICE_TABLE(of, apq8016_lpass_cpu_device_id);
  264. static struct platform_driver apq8016_lpass_cpu_platform_driver = {
  265. .driver = {
  266. .name = "apq8016-lpass-cpu",
  267. .of_match_table = of_match_ptr(apq8016_lpass_cpu_device_id),
  268. },
  269. .probe = asoc_qcom_lpass_cpu_platform_probe,
  270. .remove = asoc_qcom_lpass_cpu_platform_remove,
  271. };
  272. module_platform_driver(apq8016_lpass_cpu_platform_driver);
  273. MODULE_DESCRIPTION("APQ8016 LPASS CPU Driver");
  274. MODULE_LICENSE("GPL");