omap-mcbsp-st.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * McBSP Sidetone support
  4. *
  5. * Copyright (C) 2004 Nokia Corporation
  6. * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
  7. *
  8. * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
  9. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  10. */
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/device.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/err.h>
  17. #include <linux/clk.h>
  18. #include <linux/delay.h>
  19. #include <linux/io.h>
  20. #include <linux/slab.h>
  21. #include "omap-mcbsp.h"
  22. #include "omap-mcbsp-priv.h"
  23. /* OMAP3 sidetone control registers */
  24. #define OMAP_ST_REG_REV 0x00
  25. #define OMAP_ST_REG_SYSCONFIG 0x10
  26. #define OMAP_ST_REG_IRQSTATUS 0x18
  27. #define OMAP_ST_REG_IRQENABLE 0x1C
  28. #define OMAP_ST_REG_SGAINCR 0x24
  29. #define OMAP_ST_REG_SFIRCR 0x28
  30. #define OMAP_ST_REG_SSELCR 0x2C
  31. /********************** McBSP SSELCR bit definitions ***********************/
  32. #define SIDETONEEN BIT(10)
  33. /********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
  34. #define ST_AUTOIDLE BIT(0)
  35. /********************** McBSP Sidetone SGAINCR bit definitions *************/
  36. #define ST_CH0GAIN(value) ((value) & 0xffff) /* Bits 0:15 */
  37. #define ST_CH1GAIN(value) (((value) & 0xffff) << 16) /* Bits 16:31 */
  38. /********************** McBSP Sidetone SFIRCR bit definitions **************/
  39. #define ST_FIRCOEFF(value) ((value) & 0xffff) /* Bits 0:15 */
  40. /********************** McBSP Sidetone SSELCR bit definitions **************/
  41. #define ST_SIDETONEEN BIT(0)
  42. #define ST_COEFFWREN BIT(1)
  43. #define ST_COEFFWRDONE BIT(2)
  44. struct omap_mcbsp_st_data {
  45. void __iomem *io_base_st;
  46. struct clk *mcbsp_iclk;
  47. bool running;
  48. bool enabled;
  49. s16 taps[128]; /* Sidetone filter coefficients */
  50. int nr_taps; /* Number of filter coefficients in use */
  51. s16 ch0gain;
  52. s16 ch1gain;
  53. };
  54. static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  55. {
  56. writel_relaxed(val, mcbsp->st_data->io_base_st + reg);
  57. }
  58. static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  59. {
  60. return readl_relaxed(mcbsp->st_data->io_base_st + reg);
  61. }
  62. #define MCBSP_ST_READ(mcbsp, reg) omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  63. #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  64. omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  65. static void omap_mcbsp_st_on(struct omap_mcbsp *mcbsp)
  66. {
  67. unsigned int w;
  68. if (mcbsp->pdata->force_ick_on)
  69. mcbsp->pdata->force_ick_on(mcbsp->st_data->mcbsp_iclk, true);
  70. /* Disable Sidetone clock auto-gating for normal operation */
  71. w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
  72. MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
  73. /* Enable McBSP Sidetone */
  74. w = MCBSP_READ(mcbsp, SSELCR);
  75. MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
  76. /* Enable Sidetone from Sidetone Core */
  77. w = MCBSP_ST_READ(mcbsp, SSELCR);
  78. MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
  79. }
  80. static void omap_mcbsp_st_off(struct omap_mcbsp *mcbsp)
  81. {
  82. unsigned int w;
  83. w = MCBSP_ST_READ(mcbsp, SSELCR);
  84. MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
  85. w = MCBSP_READ(mcbsp, SSELCR);
  86. MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
  87. /* Enable Sidetone clock auto-gating to reduce power consumption */
  88. w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
  89. MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
  90. if (mcbsp->pdata->force_ick_on)
  91. mcbsp->pdata->force_ick_on(mcbsp->st_data->mcbsp_iclk, false);
  92. }
  93. static void omap_mcbsp_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
  94. {
  95. u16 val, i;
  96. val = MCBSP_ST_READ(mcbsp, SSELCR);
  97. if (val & ST_COEFFWREN)
  98. MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
  99. MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
  100. for (i = 0; i < 128; i++)
  101. MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
  102. i = 0;
  103. val = MCBSP_ST_READ(mcbsp, SSELCR);
  104. while (!(val & ST_COEFFWRDONE) && (++i < 1000))
  105. val = MCBSP_ST_READ(mcbsp, SSELCR);
  106. MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
  107. if (i == 1000)
  108. dev_err(mcbsp->dev, "McBSP FIR load error!\n");
  109. }
  110. static void omap_mcbsp_st_chgain(struct omap_mcbsp *mcbsp)
  111. {
  112. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  113. MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) |
  114. ST_CH1GAIN(st_data->ch1gain));
  115. }
  116. static int omap_mcbsp_st_set_chgain(struct omap_mcbsp *mcbsp, int channel,
  117. s16 chgain)
  118. {
  119. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  120. int ret = 0;
  121. if (!st_data)
  122. return -ENOENT;
  123. spin_lock_irq(&mcbsp->lock);
  124. if (channel == 0)
  125. st_data->ch0gain = chgain;
  126. else if (channel == 1)
  127. st_data->ch1gain = chgain;
  128. else
  129. ret = -EINVAL;
  130. if (st_data->enabled)
  131. omap_mcbsp_st_chgain(mcbsp);
  132. spin_unlock_irq(&mcbsp->lock);
  133. return ret;
  134. }
  135. static int omap_mcbsp_st_get_chgain(struct omap_mcbsp *mcbsp, int channel,
  136. s16 *chgain)
  137. {
  138. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  139. int ret = 0;
  140. if (!st_data)
  141. return -ENOENT;
  142. spin_lock_irq(&mcbsp->lock);
  143. if (channel == 0)
  144. *chgain = st_data->ch0gain;
  145. else if (channel == 1)
  146. *chgain = st_data->ch1gain;
  147. else
  148. ret = -EINVAL;
  149. spin_unlock_irq(&mcbsp->lock);
  150. return ret;
  151. }
  152. static int omap_mcbsp_st_enable(struct omap_mcbsp *mcbsp)
  153. {
  154. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  155. if (!st_data)
  156. return -ENODEV;
  157. spin_lock_irq(&mcbsp->lock);
  158. st_data->enabled = 1;
  159. omap_mcbsp_st_start(mcbsp);
  160. spin_unlock_irq(&mcbsp->lock);
  161. return 0;
  162. }
  163. static int omap_mcbsp_st_disable(struct omap_mcbsp *mcbsp)
  164. {
  165. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  166. int ret = 0;
  167. if (!st_data)
  168. return -ENODEV;
  169. spin_lock_irq(&mcbsp->lock);
  170. omap_mcbsp_st_stop(mcbsp);
  171. st_data->enabled = 0;
  172. spin_unlock_irq(&mcbsp->lock);
  173. return ret;
  174. }
  175. static int omap_mcbsp_st_is_enabled(struct omap_mcbsp *mcbsp)
  176. {
  177. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  178. if (!st_data)
  179. return -ENODEV;
  180. return st_data->enabled;
  181. }
  182. static ssize_t st_taps_show(struct device *dev,
  183. struct device_attribute *attr, char *buf)
  184. {
  185. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
  186. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  187. ssize_t status = 0;
  188. int i;
  189. spin_lock_irq(&mcbsp->lock);
  190. for (i = 0; i < st_data->nr_taps; i++)
  191. status += sysfs_emit_at(buf, status, (i ? ", %d" : "%d"),
  192. st_data->taps[i]);
  193. if (i)
  194. status += sysfs_emit_at(buf, status, "\n");
  195. spin_unlock_irq(&mcbsp->lock);
  196. return status;
  197. }
  198. static ssize_t st_taps_store(struct device *dev,
  199. struct device_attribute *attr,
  200. const char *buf, size_t size)
  201. {
  202. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
  203. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  204. int val, tmp, status, i = 0;
  205. spin_lock_irq(&mcbsp->lock);
  206. memset(st_data->taps, 0, sizeof(st_data->taps));
  207. st_data->nr_taps = 0;
  208. do {
  209. status = sscanf(buf, "%d%n", &val, &tmp);
  210. if (status < 0 || status == 0) {
  211. size = -EINVAL;
  212. goto out;
  213. }
  214. if (val < -32768 || val > 32767) {
  215. size = -EINVAL;
  216. goto out;
  217. }
  218. st_data->taps[i++] = val;
  219. buf += tmp;
  220. if (*buf != ',')
  221. break;
  222. buf++;
  223. } while (1);
  224. st_data->nr_taps = i;
  225. out:
  226. spin_unlock_irq(&mcbsp->lock);
  227. return size;
  228. }
  229. static DEVICE_ATTR_RW(st_taps);
  230. static const struct attribute *sidetone_attrs[] = {
  231. &dev_attr_st_taps.attr,
  232. NULL,
  233. };
  234. static const struct attribute_group sidetone_attr_group = {
  235. .attrs = (struct attribute **)sidetone_attrs,
  236. };
  237. int omap_mcbsp_st_start(struct omap_mcbsp *mcbsp)
  238. {
  239. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  240. if (st_data->enabled && !st_data->running) {
  241. omap_mcbsp_st_fir_write(mcbsp, st_data->taps);
  242. omap_mcbsp_st_chgain(mcbsp);
  243. if (!mcbsp->free) {
  244. omap_mcbsp_st_on(mcbsp);
  245. st_data->running = 1;
  246. }
  247. }
  248. return 0;
  249. }
  250. int omap_mcbsp_st_stop(struct omap_mcbsp *mcbsp)
  251. {
  252. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  253. if (st_data->running) {
  254. if (!mcbsp->free) {
  255. omap_mcbsp_st_off(mcbsp);
  256. st_data->running = 0;
  257. }
  258. }
  259. return 0;
  260. }
  261. int omap_mcbsp_st_init(struct platform_device *pdev)
  262. {
  263. struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
  264. struct omap_mcbsp_st_data *st_data;
  265. struct resource *res;
  266. int ret;
  267. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
  268. if (!res)
  269. return 0;
  270. st_data = devm_kzalloc(mcbsp->dev, sizeof(*mcbsp->st_data), GFP_KERNEL);
  271. if (!st_data)
  272. return -ENOMEM;
  273. st_data->mcbsp_iclk = devm_clk_get(mcbsp->dev, "ick");
  274. if (IS_ERR(st_data->mcbsp_iclk)) {
  275. dev_warn(mcbsp->dev,
  276. "Failed to get ick, sidetone might be broken\n");
  277. st_data->mcbsp_iclk = NULL;
  278. }
  279. st_data->io_base_st = devm_ioremap(mcbsp->dev, res->start,
  280. resource_size(res));
  281. if (!st_data->io_base_st)
  282. return -ENOMEM;
  283. ret = devm_device_add_group(mcbsp->dev, &sidetone_attr_group);
  284. if (ret)
  285. return ret;
  286. mcbsp->st_data = st_data;
  287. return 0;
  288. }
  289. static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
  290. struct snd_ctl_elem_info *uinfo)
  291. {
  292. struct soc_mixer_control *mc =
  293. (struct soc_mixer_control *)kcontrol->private_value;
  294. int max = mc->max;
  295. int min = mc->min;
  296. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  297. uinfo->count = 1;
  298. uinfo->value.integer.min = min;
  299. uinfo->value.integer.max = max;
  300. return 0;
  301. }
  302. #define OMAP_MCBSP_ST_CHANNEL_VOLUME(channel) \
  303. static int \
  304. omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
  305. struct snd_ctl_elem_value *uc) \
  306. { \
  307. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \
  308. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \
  309. struct soc_mixer_control *mc = \
  310. (struct soc_mixer_control *)kc->private_value; \
  311. int max = mc->max; \
  312. int min = mc->min; \
  313. int val = uc->value.integer.value[0]; \
  314. \
  315. if (val < min || val > max) \
  316. return -EINVAL; \
  317. \
  318. /* OMAP McBSP implementation uses index values 0..4 */ \
  319. return omap_mcbsp_st_set_chgain(mcbsp, channel, val); \
  320. } \
  321. \
  322. static int \
  323. omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
  324. struct snd_ctl_elem_value *uc) \
  325. { \
  326. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \
  327. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \
  328. s16 chgain; \
  329. \
  330. if (omap_mcbsp_st_get_chgain(mcbsp, channel, &chgain)) \
  331. return -EAGAIN; \
  332. \
  333. uc->value.integer.value[0] = chgain; \
  334. return 0; \
  335. }
  336. OMAP_MCBSP_ST_CHANNEL_VOLUME(0)
  337. OMAP_MCBSP_ST_CHANNEL_VOLUME(1)
  338. static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
  339. struct snd_ctl_elem_value *ucontrol)
  340. {
  341. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  342. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  343. u8 value = ucontrol->value.integer.value[0];
  344. if (value == omap_mcbsp_st_is_enabled(mcbsp))
  345. return 0;
  346. if (value)
  347. omap_mcbsp_st_enable(mcbsp);
  348. else
  349. omap_mcbsp_st_disable(mcbsp);
  350. return 1;
  351. }
  352. static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
  353. struct snd_ctl_elem_value *ucontrol)
  354. {
  355. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  356. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  357. ucontrol->value.integer.value[0] = omap_mcbsp_st_is_enabled(mcbsp);
  358. return 0;
  359. }
  360. #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
  361. xhandler_get, xhandler_put) \
  362. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  363. .info = omap_mcbsp_st_info_volsw, \
  364. .get = xhandler_get, .put = xhandler_put, \
  365. .private_value = (unsigned long)&(struct soc_mixer_control) \
  366. {.min = xmin, .max = xmax} }
  367. #define OMAP_MCBSP_ST_CONTROLS(port) \
  368. static const struct snd_kcontrol_new omap_mcbsp##port##_st_controls[] = { \
  369. SOC_SINGLE_EXT("McBSP" #port " Sidetone Switch", 1, 0, 1, 0, \
  370. omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), \
  371. OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 0 Volume", \
  372. -32768, 32767, \
  373. omap_mcbsp_get_st_ch0_volume, \
  374. omap_mcbsp_set_st_ch0_volume), \
  375. OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 1 Volume", \
  376. -32768, 32767, \
  377. omap_mcbsp_get_st_ch1_volume, \
  378. omap_mcbsp_set_st_ch1_volume), \
  379. }
  380. OMAP_MCBSP_ST_CONTROLS(2);
  381. OMAP_MCBSP_ST_CONTROLS(3);
  382. int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd, int port_id)
  383. {
  384. struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
  385. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  386. if (!mcbsp->st_data) {
  387. dev_warn(mcbsp->dev, "No sidetone data for port\n");
  388. return 0;
  389. }
  390. switch (port_id) {
  391. case 2: /* McBSP 2 */
  392. return snd_soc_add_dai_controls(cpu_dai,
  393. omap_mcbsp2_st_controls,
  394. ARRAY_SIZE(omap_mcbsp2_st_controls));
  395. case 3: /* McBSP 3 */
  396. return snd_soc_add_dai_controls(cpu_dai,
  397. omap_mcbsp3_st_controls,
  398. ARRAY_SIZE(omap_mcbsp3_st_controls));
  399. default:
  400. dev_err(mcbsp->dev, "Port %d not supported\n", port_id);
  401. break;
  402. }
  403. return -EINVAL;
  404. }
  405. EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);