mcf54xx.dtsi 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
  4. */
  5. / {
  6. compatible = "fsl,mcf54x5";
  7. aliases {
  8. /* TO DO, clarify on serial, this SoC seems to have SPC and
  9. * no UARTS.
  10. */
  11. spi0 = &dspi0;
  12. fec0 = &fec0;
  13. fec1 = &fec1;
  14. };
  15. soc {
  16. compatible = "simple-bus";
  17. #address-cells = <1>;
  18. #size-cells = <1>;
  19. mbar: mbar@80000000 {
  20. compatible = "simple-bus";
  21. #address-cells = <1>;
  22. #size-cells = <1>;
  23. ranges = <0x00000000 0x80000000 0x10000>;
  24. reg = <0x80000000 0x10000>;
  25. dspi0: dspi@8a00 {
  26. compatible = "fsl,mcf-dspi";
  27. #address-cells = <1>;
  28. #size-cells = <0>;
  29. reg = <0x8a00 0x100>;
  30. spi-max-frequency = <50000000>;
  31. num-cs = <4>;
  32. spi-mode = <0>;
  33. status = "disabled";
  34. };
  35. fec0: ethernet@9000 {
  36. compatible = "fsl,mcf-dma-fec";
  37. reg = <0x9000 0x800>;
  38. mii-base = <0>;
  39. max-speed = <100>;
  40. timeout-loop = <50000>;
  41. rx-task = <0>;
  42. tx-task = <1>;
  43. rx-piority = <6>;
  44. tx-piority = <7>;
  45. rx-init = <16>;
  46. tx-init = <17>;
  47. status = "disabled";
  48. };
  49. fec1: ethernet@9800 {
  50. compatible = "fsl,mcf-dma-fec";
  51. reg = <0x9800 0x800>;
  52. mii-base = <1>;
  53. max-speed = <100>;
  54. timeout-loop = <50000>;
  55. rx-task = <2>;
  56. tx-task = <3>;
  57. rx-piority = <6>;
  58. tx-piority = <7>;
  59. rx-init = <30>;
  60. tx-init = <31>;
  61. status = "disabled";
  62. };
  63. };
  64. };
  65. };