icore_mx8mm.c 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Amarula Solutions B.V.
  4. * Copyright (C) 2016 Engicam S.r.l.
  5. * Author: Jagan Teki <jagan@amarulasolutions.com>
  6. */
  7. #include <common.h>
  8. #include <miiphy.h>
  9. #include <netdev.h>
  10. #include <asm/io.h>
  11. #include <asm-generic/gpio.h>
  12. #include <linux/delay.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/imx8mm_pins.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/mach-imx/gpio.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #if IS_ENABLED(CONFIG_FEC_MXC)
  20. #define FEC_RST_PAD IMX_GPIO_NR(3, 7)
  21. static iomux_v3_cfg_t const fec1_rst_pads[] = {
  22. IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
  23. };
  24. static void setup_fec(void)
  25. {
  26. imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
  27. ARRAY_SIZE(fec1_rst_pads));
  28. gpio_request(FEC_RST_PAD, "fec1_rst");
  29. gpio_direction_output(FEC_RST_PAD, 0);
  30. udelay(500);
  31. gpio_direction_output(FEC_RST_PAD, 1);
  32. }
  33. int board_phy_config(struct phy_device *phydev)
  34. {
  35. /* enable rgmii rxc skew and phy mode select to RGMII copper */
  36. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  37. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  38. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
  39. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
  40. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  41. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  42. if (phydev->drv->config)
  43. phydev->drv->config(phydev);
  44. return 0;
  45. }
  46. #endif
  47. int board_init(void)
  48. {
  49. if (IS_ENABLED(CONFIG_FEC_MXC))
  50. setup_fec();
  51. return 0;
  52. }
  53. int board_mmc_get_env_dev(int devno)
  54. {
  55. return devno;
  56. }