brcm,brcmstb-gpio.yaml 2.9 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Broadcom STB "UPG GIO" GPIO controller
  7. description: >
  8. The controller's registers are organized as sets of eight 32-bit
  9. registers with each set controlling a bank of up to 32 pins. A single
  10. interrupt is shared for all of the banks handled by the controller.
  11. maintainers:
  12. - Doug Berger <opendmb@gmail.com>
  13. - Florian Fainelli <f.fainelli@gmail.com>
  14. properties:
  15. compatible:
  16. items:
  17. - enum:
  18. - brcm,bcm7445-gpio
  19. - const: brcm,brcmstb-gpio
  20. reg:
  21. maxItems: 1
  22. description: >
  23. Define the base and range of the I/O address space containing
  24. the brcmstb GPIO controller registers
  25. "#gpio-cells":
  26. const: 2
  27. description: >
  28. The first cell is the pin number (within the controller's
  29. pin space), and the second is used for the following:
  30. bit[0]: polarity (0 for active-high, 1 for active-low)
  31. gpio-controller: true
  32. brcm,gpio-bank-widths:
  33. $ref: /schemas/types.yaml#/definitions/uint32-array
  34. description: >
  35. Number of GPIO lines for each bank. Number of elements must
  36. correspond to number of banks suggested by the 'reg' property.
  37. interrupts:
  38. maxItems: 1
  39. description: >
  40. The interrupt shared by all GPIO lines for this controller.
  41. "#interrupt-cells":
  42. const: 2
  43. description: |
  44. The first cell is the GPIO number, the second should specify
  45. flags. The following subset of flags is supported:
  46. - bits[3:0] trigger type and level flags
  47. 1 = low-to-high edge triggered
  48. 2 = high-to-low edge triggered
  49. 4 = active high level-sensitive
  50. 8 = active low level-sensitive
  51. Valid combinations are 1, 2, 3, 4, 8.
  52. interrupt-controller: true
  53. gpio-ranges: true
  54. wakeup-source:
  55. type: boolean
  56. description: >
  57. GPIOs for this controller can be used as a wakeup source
  58. required:
  59. - compatible
  60. - reg
  61. - gpio-controller
  62. - "#gpio-cells"
  63. - brcm,gpio-bank-widths
  64. additionalProperties: false
  65. examples:
  66. - |
  67. upg_gio: gpio@f040a700 {
  68. #gpio-cells = <2>;
  69. #interrupt-cells = <2>;
  70. compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
  71. gpio-controller;
  72. interrupt-controller;
  73. reg = <0xf040a700 0x80>;
  74. interrupt-parent = <&irq0_intc>;
  75. interrupts = <0x6>;
  76. brcm,gpio-bank-widths = <32 32 32 24>;
  77. gpio-ranges = <&pinctrl 0 0 120>;
  78. };
  79. upg_gio_aon: gpio@f04172c0 {
  80. #gpio-cells = <2>;
  81. #interrupt-cells = <2>;
  82. compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
  83. gpio-controller;
  84. interrupt-controller;
  85. reg = <0xf04172c0 0x40>;
  86. interrupt-parent = <&irq0_aon_intc>;
  87. interrupts = <0x6>;
  88. wakeup-source;
  89. brcm,gpio-bank-widths = <18 4>;
  90. };