nvidia,tegra234-nvdec.yaml 4.2 KB

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  1. # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: NVIDIA Tegra234 NVDEC
  7. description: |
  8. NVDEC is the hardware video decoder present on NVIDIA Tegra210
  9. and newer chips. It is located on the Host1x bus and typically
  10. programmed through Host1x channels.
  11. maintainers:
  12. - Thierry Reding <treding@gmail.com>
  13. - Mikko Perttunen <mperttunen@nvidia.com>
  14. properties:
  15. $nodename:
  16. pattern: "^nvdec@[0-9a-f]*$"
  17. compatible:
  18. enum:
  19. - nvidia,tegra234-nvdec
  20. reg:
  21. maxItems: 1
  22. clocks:
  23. maxItems: 3
  24. clock-names:
  25. items:
  26. - const: nvdec
  27. - const: fuse
  28. - const: tsec_pka
  29. resets:
  30. maxItems: 1
  31. reset-names:
  32. items:
  33. - const: nvdec
  34. power-domains:
  35. maxItems: 1
  36. iommus:
  37. maxItems: 1
  38. dma-coherent: true
  39. interconnects:
  40. items:
  41. - description: DMA read memory client
  42. - description: DMA write memory client
  43. interconnect-names:
  44. items:
  45. - const: dma-mem
  46. - const: write
  47. nvidia,memory-controller:
  48. $ref: /schemas/types.yaml#/definitions/phandle
  49. description:
  50. phandle to the memory controller for determining information for the NVDEC
  51. firmware secure carveout. This carveout is configured by the bootloader and
  52. not accessible to CPU.
  53. nvidia,bl-manifest-offset:
  54. $ref: /schemas/types.yaml#/definitions/uint32
  55. description:
  56. Offset to bootloader manifest from beginning of firmware that was configured by
  57. the bootloader.
  58. nvidia,bl-code-offset:
  59. $ref: /schemas/types.yaml#/definitions/uint32
  60. description:
  61. Offset to bootloader code section from beginning of firmware that was configured by
  62. the bootloader.
  63. nvidia,bl-data-offset:
  64. $ref: /schemas/types.yaml#/definitions/uint32
  65. description:
  66. Offset to bootloader data section from beginning of firmware that was configured by
  67. the bootloader.
  68. nvidia,os-manifest-offset:
  69. $ref: /schemas/types.yaml#/definitions/uint32
  70. description:
  71. Offset to operating system manifest from beginning of firmware that was configured by
  72. the bootloader.
  73. nvidia,os-code-offset:
  74. $ref: /schemas/types.yaml#/definitions/uint32
  75. description:
  76. Offset to operating system code section from beginning of firmware that was configured by
  77. the bootloader.
  78. nvidia,os-data-offset:
  79. $ref: /schemas/types.yaml#/definitions/uint32
  80. description:
  81. Offset to operating system data section from beginning of firmware that was configured
  82. by the bootloader.
  83. required:
  84. - compatible
  85. - reg
  86. - clocks
  87. - clock-names
  88. - resets
  89. - reset-names
  90. - power-domains
  91. - nvidia,memory-controller
  92. - nvidia,bl-manifest-offset
  93. - nvidia,bl-code-offset
  94. - nvidia,bl-data-offset
  95. - nvidia,os-manifest-offset
  96. - nvidia,os-code-offset
  97. - nvidia,os-data-offset
  98. additionalProperties: false
  99. examples:
  100. - |
  101. #include <dt-bindings/clock/tegra234-clock.h>
  102. #include <dt-bindings/memory/tegra234-mc.h>
  103. #include <dt-bindings/power/tegra234-powergate.h>
  104. #include <dt-bindings/reset/tegra234-reset.h>
  105. nvdec@15480000 {
  106. compatible = "nvidia,tegra234-nvdec";
  107. reg = <0x15480000 0x00040000>;
  108. clocks = <&bpmp TEGRA234_CLK_NVDEC>,
  109. <&bpmp TEGRA234_CLK_FUSE>,
  110. <&bpmp TEGRA234_CLK_TSEC_PKA>;
  111. clock-names = "nvdec", "fuse", "tsec_pka";
  112. resets = <&bpmp TEGRA234_RESET_NVDEC>;
  113. reset-names = "nvdec";
  114. power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
  115. interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
  116. <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
  117. interconnect-names = "dma-mem", "write";
  118. iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
  119. dma-coherent;
  120. nvidia,memory-controller = <&mc>;
  121. /* Placeholder values, to be replaced with values from overlay */
  122. nvidia,bl-manifest-offset = <0>;
  123. nvidia,bl-data-offset = <0>;
  124. nvidia,bl-code-offset = <0>;
  125. nvidia,os-manifest-offset = <0>;
  126. nvidia,os-data-offset = <0>;
  127. nvidia,os-code-offset = <0>;
  128. };