cdns,i2c-r1p10.yaml 1.5 KB

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  1. # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Cadence I2C controller
  7. maintainers:
  8. - Michal Simek <michal.simek@amd.com>
  9. allOf:
  10. - $ref: /schemas/i2c/i2c-controller.yaml#
  11. properties:
  12. compatible:
  13. enum:
  14. - cdns,i2c-r1p10 # cadence i2c controller version 1.0
  15. - cdns,i2c-r1p14 # cadence i2c controller version 1.4
  16. reg:
  17. maxItems: 1
  18. clocks:
  19. minItems: 1
  20. resets:
  21. maxItems: 1
  22. interrupts:
  23. maxItems: 1
  24. clock-frequency:
  25. minimum: 1
  26. maximum: 400000
  27. description: |
  28. Desired operating frequency, in Hz, of the bus.
  29. clock-name:
  30. const: pclk
  31. description: |
  32. Input clock name.
  33. fifo-depth:
  34. description:
  35. Size of the data FIFO in bytes.
  36. $ref: /schemas/types.yaml#/definitions/uint32
  37. default: 16
  38. enum: [2, 4, 8, 16, 32, 64, 128, 256]
  39. power-domains:
  40. maxItems: 1
  41. required:
  42. - compatible
  43. - reg
  44. - clocks
  45. - interrupts
  46. unevaluatedProperties: false
  47. examples:
  48. - |
  49. #include <dt-bindings/interrupt-controller/arm-gic.h>
  50. i2c@e0004000 {
  51. compatible = "cdns,i2c-r1p10";
  52. clocks = <&clkc 38>;
  53. resets = <&rstc 288>;
  54. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  55. reg = <0xe0004000 0x1000>;
  56. clock-frequency = <400000>;
  57. #address-cells = <1>;
  58. #size-cells = <0>;
  59. fifo-depth = <8>;
  60. };