snps,designware-i2c.yaml 3.5 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Synopsys DesignWare APB I2C Controller
  7. maintainers:
  8. - Jarkko Nikula <jarkko.nikula@linux.intel.com>
  9. allOf:
  10. - $ref: /schemas/i2c/i2c-controller.yaml#
  11. - if:
  12. properties:
  13. compatible:
  14. not:
  15. contains:
  16. const: mscc,ocelot-i2c
  17. then:
  18. properties:
  19. reg:
  20. maxItems: 1
  21. properties:
  22. compatible:
  23. oneOf:
  24. - description: Generic Synopsys DesignWare I2C controller
  25. const: snps,designware-i2c
  26. - description: Microsemi Ocelot SoCs I2C controller
  27. items:
  28. - const: mscc,ocelot-i2c
  29. - const: snps,designware-i2c
  30. - description: Baikal-T1 SoC System I2C controller
  31. const: baikal,bt1-sys-i2c
  32. - description: T-HEAD TH1520 SoCs I2C controller
  33. items:
  34. - const: thead,th1520-i2c
  35. - const: snps,designware-i2c
  36. reg:
  37. minItems: 1
  38. items:
  39. - description: DW APB I2C controller memory mapped registers
  40. - description: |
  41. ICPU_CFG:TWI_DELAY registers to setup the SDA hold time.
  42. This registers are specific to the Ocelot I2C-controller.
  43. interrupts:
  44. maxItems: 1
  45. clocks:
  46. minItems: 1
  47. items:
  48. - description: I2C controller reference clock source
  49. - description: APB interface clock source
  50. clock-names:
  51. minItems: 1
  52. items:
  53. - const: ref
  54. - const: pclk
  55. resets:
  56. maxItems: 1
  57. clock-frequency:
  58. description: Desired I2C bus clock frequency in Hz
  59. enum: [100000, 400000, 1000000, 3400000]
  60. default: 400000
  61. i2c-sda-hold-time-ns:
  62. description: |
  63. The property should contain the SDA hold time in nanoseconds. This option
  64. is only supported in hardware blocks version 1.11a or newer or on
  65. Microsemi SoCs.
  66. i2c-scl-falling-time-ns:
  67. description: |
  68. The property should contain the SCL falling time in nanoseconds.
  69. This value is used to compute the tLOW period.
  70. default: 300
  71. i2c-sda-falling-time-ns:
  72. description: |
  73. The property should contain the SDA falling time in nanoseconds.
  74. This value is used to compute the tHIGH period.
  75. default: 300
  76. dmas:
  77. items:
  78. - description: TX DMA Channel
  79. - description: RX DMA Channel
  80. dma-names:
  81. items:
  82. - const: tx
  83. - const: rx
  84. unevaluatedProperties: false
  85. required:
  86. - compatible
  87. - reg
  88. - interrupts
  89. examples:
  90. - |
  91. i2c@f0000 {
  92. compatible = "snps,designware-i2c";
  93. reg = <0xf0000 0x1000>;
  94. interrupts = <11>;
  95. clock-frequency = <400000>;
  96. };
  97. - |
  98. i2c@1120000 {
  99. compatible = "snps,designware-i2c";
  100. reg = <0x1120000 0x1000>;
  101. interrupts = <12 1>;
  102. clock-frequency = <400000>;
  103. i2c-sda-hold-time-ns = <300>;
  104. i2c-sda-falling-time-ns = <300>;
  105. i2c-scl-falling-time-ns = <300>;
  106. };
  107. - |
  108. i2c@2000 {
  109. compatible = "snps,designware-i2c";
  110. reg = <0x2000 0x100>;
  111. #address-cells = <1>;
  112. #size-cells = <0>;
  113. clock-frequency = <400000>;
  114. clocks = <&i2cclk>;
  115. interrupts = <0>;
  116. eeprom@64 {
  117. compatible = "atmel,24c02";
  118. reg = <0x64>;
  119. };
  120. };
  121. - |
  122. i2c@100400 {
  123. compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
  124. reg = <0x100400 0x100>, <0x198 0x8>;
  125. pinctrl-0 = <&i2c_pins>;
  126. pinctrl-names = "default";
  127. interrupts = <8>;
  128. clocks = <&ahb_clk>;
  129. };
  130. ...