rockchip-dw-mshc.yaml 3.7 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Rockchip designware mobile storage host controller
  7. description:
  8. Rockchip uses the Synopsys designware mobile storage host controller
  9. to interface a SoC with storage medium such as eMMC or SD/MMC cards.
  10. This file documents the combined properties for the core Synopsys dw mshc
  11. controller that are not already included in the synopsys-dw-mshc-common.yaml
  12. file and the Rockchip specific extensions.
  13. allOf:
  14. - $ref: synopsys-dw-mshc-common.yaml#
  15. maintainers:
  16. - Heiko Stuebner <heiko@sntech.de>
  17. # Everything else is described in the common file
  18. properties:
  19. compatible:
  20. oneOf:
  21. # for Rockchip RK2928 and before RK3288
  22. - const: rockchip,rk2928-dw-mshc
  23. # for Rockchip RK3288
  24. - const: rockchip,rk3288-dw-mshc
  25. - items:
  26. - enum:
  27. - rockchip,px30-dw-mshc
  28. - rockchip,rk1808-dw-mshc
  29. - rockchip,rk3036-dw-mshc
  30. - rockchip,rk3128-dw-mshc
  31. - rockchip,rk3228-dw-mshc
  32. - rockchip,rk3308-dw-mshc
  33. - rockchip,rk3328-dw-mshc
  34. - rockchip,rk3368-dw-mshc
  35. - rockchip,rk3399-dw-mshc
  36. - rockchip,rk3568-dw-mshc
  37. - rockchip,rk3588-dw-mshc
  38. - rockchip,rv1108-dw-mshc
  39. - rockchip,rv1126-dw-mshc
  40. - const: rockchip,rk3288-dw-mshc
  41. # for Rockchip RK3576 with phase tuning inside the controller
  42. - const: rockchip,rk3576-dw-mshc
  43. reg:
  44. maxItems: 1
  45. interrupts:
  46. maxItems: 1
  47. clocks:
  48. minItems: 2
  49. maxItems: 4
  50. description:
  51. Handle to "biu" and "ciu" clocks for the bus interface unit clock and
  52. the card interface unit clock. If "ciu-drive" and "ciu-sample" are
  53. specified in clock-names, it should also contain
  54. handles to these clocks.
  55. clock-names:
  56. minItems: 2
  57. items:
  58. - const: biu
  59. - const: ciu
  60. - const: ciu-drive
  61. - const: ciu-sample
  62. description:
  63. Apart from the clock-names "biu" and "ciu" two more clocks
  64. "ciu-drive" and "ciu-sample" are supported. They are used
  65. to control the clock phases, "ciu-sample" is required for tuning
  66. high speed modes.
  67. power-domains:
  68. maxItems: 1
  69. rockchip,default-sample-phase:
  70. $ref: /schemas/types.yaml#/definitions/uint32
  71. minimum: 0
  72. maximum: 360
  73. default: 0
  74. description:
  75. The default phase to set "ciu-sample" at probing,
  76. low speeds or in case where all phases work at tuning time.
  77. If not specified 0 deg will be used.
  78. rockchip,desired-num-phases:
  79. $ref: /schemas/types.yaml#/definitions/uint32
  80. minimum: 0
  81. maximum: 360
  82. default: 360
  83. description:
  84. The desired number of times that the host execute tuning when needed.
  85. If not specified, the host will do tuning for 360 times,
  86. namely tuning for each degree.
  87. required:
  88. - compatible
  89. - reg
  90. - interrupts
  91. - clocks
  92. - clock-names
  93. unevaluatedProperties: false
  94. examples:
  95. - |
  96. #include <dt-bindings/clock/rk3288-cru.h>
  97. #include <dt-bindings/interrupt-controller/arm-gic.h>
  98. #include <dt-bindings/interrupt-controller/irq.h>
  99. sdmmc: mmc@ff0c0000 {
  100. compatible = "rockchip,rk3288-dw-mshc";
  101. reg = <0xff0c0000 0x4000>;
  102. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  103. clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
  104. <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
  105. clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  106. resets = <&cru SRST_MMC0>;
  107. reset-names = "reset";
  108. fifo-depth = <0x100>;
  109. max-frequency = <150000000>;
  110. };
  111. ...