mediatek,dsi-phy.yaml 2.2 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. # Copyright (c) 2020 MediaTek
  3. %YAML 1.2
  4. ---
  5. $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
  6. $schema: http://devicetree.org/meta-schemas/core.yaml#
  7. title: MediaTek MIPI Display Serial Interface (DSI) PHY
  8. maintainers:
  9. - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  10. - Philipp Zabel <p.zabel@pengutronix.de>
  11. - Chunfeng Yun <chunfeng.yun@mediatek.com>
  12. description: The MIPI DSI PHY supports up to 4-lane output.
  13. properties:
  14. $nodename:
  15. pattern: "^dsi-phy@[0-9a-f]+$"
  16. compatible:
  17. oneOf:
  18. - items:
  19. - enum:
  20. - mediatek,mt7623-mipi-tx
  21. - const: mediatek,mt2701-mipi-tx
  22. - items:
  23. - enum:
  24. - mediatek,mt6795-mipi-tx
  25. - const: mediatek,mt8173-mipi-tx
  26. - items:
  27. - enum:
  28. - mediatek,mt8188-mipi-tx
  29. - mediatek,mt8195-mipi-tx
  30. - mediatek,mt8365-mipi-tx
  31. - const: mediatek,mt8183-mipi-tx
  32. - const: mediatek,mt2701-mipi-tx
  33. - const: mediatek,mt8173-mipi-tx
  34. - const: mediatek,mt8183-mipi-tx
  35. reg:
  36. maxItems: 1
  37. clocks:
  38. items:
  39. - description: PLL reference clock
  40. clock-output-names:
  41. maxItems: 1
  42. "#phy-cells":
  43. const: 0
  44. "#clock-cells":
  45. const: 0
  46. nvmem-cells:
  47. maxItems: 1
  48. description: A phandle to the calibration data provided by a nvmem device,
  49. if unspecified, default values shall be used.
  50. nvmem-cell-names:
  51. items:
  52. - const: calibration-data
  53. drive-strength-microamp:
  54. description: adjust driving current
  55. multipleOf: 200
  56. minimum: 2000
  57. maximum: 6000
  58. default: 4600
  59. required:
  60. - compatible
  61. - reg
  62. - clocks
  63. - clock-output-names
  64. - "#phy-cells"
  65. - "#clock-cells"
  66. additionalProperties: false
  67. examples:
  68. - |
  69. #include <dt-bindings/clock/mt8173-clk.h>
  70. dsi-phy@10215000 {
  71. compatible = "mediatek,mt8173-mipi-tx";
  72. reg = <0x10215000 0x1000>;
  73. clocks = <&clk26m>;
  74. clock-output-names = "mipi_tx0_pll";
  75. drive-strength-microamp = <4000>;
  76. nvmem-cells = <&mipi_tx_calibration>;
  77. nvmem-cell-names = "calibration-data";
  78. #clock-cells = <0>;
  79. #phy-cells = <0>;
  80. };
  81. ...