phy-tegra194-p2u.yaml 1.4 KB

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  1. # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: NVIDIA Tegra194 & Tegra234 P2U
  7. maintainers:
  8. - Thierry Reding <treding@nvidia.com>
  9. description: >
  10. Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
  11. Speed) each interfacing with 12 and 8 P2U instances respectively.
  12. Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet)
  13. each interfacing with 8, 8 and 8 P2U instances respectively.
  14. A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
  15. interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one
  16. PCIe lane.
  17. properties:
  18. compatible:
  19. enum:
  20. - nvidia,tegra194-p2u
  21. - nvidia,tegra234-p2u
  22. reg:
  23. maxItems: 1
  24. description: Should be the physical address space and length of respective each P2U instance.
  25. reg-names:
  26. items:
  27. - const: ctl
  28. nvidia,skip-sz-protect-en:
  29. description: Should be present if two PCIe retimers are present between
  30. the root port and its immediate downstream device.
  31. type: boolean
  32. '#phy-cells':
  33. const: 0
  34. additionalProperties: false
  35. examples:
  36. - |
  37. p2u_hsio_0: phy@3e10000 {
  38. compatible = "nvidia,tegra194-p2u";
  39. reg = <0x03e10000 0x10000>;
  40. reg-names = "ctl";
  41. #phy-cells = <0>;
  42. };