qcom,usb-ss.yaml 1.8 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
  7. maintainers:
  8. - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
  9. description: |
  10. Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
  11. properties:
  12. compatible:
  13. enum:
  14. - qcom,usb-ss-28nm-phy
  15. reg:
  16. maxItems: 1
  17. "#phy-cells":
  18. const: 0
  19. clocks:
  20. items:
  21. - description: rpmcc clock
  22. - description: PHY AHB clock
  23. - description: SuperSpeed pipe clock
  24. clock-names:
  25. items:
  26. - const: ref
  27. - const: ahb
  28. - const: pipe
  29. vdd-supply:
  30. description: phandle to the regulator VDD supply node.
  31. vdda1p8-supply:
  32. description: phandle to the regulator 1.8V supply node.
  33. resets:
  34. items:
  35. - description: COM reset
  36. - description: PHY reset line
  37. reset-names:
  38. items:
  39. - const: com
  40. - const: phy
  41. required:
  42. - compatible
  43. - reg
  44. - "#phy-cells"
  45. - clocks
  46. - clock-names
  47. - vdd-supply
  48. - vdda1p8-supply
  49. additionalProperties: false
  50. examples:
  51. - |
  52. #include <dt-bindings/clock/qcom,gcc-qcs404.h>
  53. #include <dt-bindings/clock/qcom,rpmcc.h>
  54. usb3_phy: usb3-phy@78000 {
  55. compatible = "qcom,usb-ss-28nm-phy";
  56. reg = <0x78000 0x400>;
  57. #phy-cells = <0>;
  58. clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
  59. <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
  60. <&gcc GCC_USB3_PHY_PIPE_CLK>;
  61. clock-names = "ref", "ahb", "pipe";
  62. resets = <&gcc GCC_USB3_PHY_BCR>,
  63. <&gcc GCC_USB3PHY_PHY_BCR>;
  64. reset-names = "com", "phy";
  65. vdd-supply = <&vreg_l3_1p05>;
  66. vdda1p8-supply = <&vreg_l5_1p8>;
  67. };
  68. ...