renesas,usb2-phy.yaml 3.3 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Renesas R-Car generation 3 USB 2.0 PHY
  7. maintainers:
  8. - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  9. properties:
  10. compatible:
  11. oneOf:
  12. - items:
  13. - enum:
  14. - renesas,usb2-phy-r8a77470 # RZ/G1C
  15. - renesas,usb2-phy-r9a08g045 # RZ/G3S
  16. - items:
  17. - enum:
  18. - renesas,usb2-phy-r7s9210 # RZ/A2
  19. - renesas,usb2-phy-r8a774a1 # RZ/G2M
  20. - renesas,usb2-phy-r8a774b1 # RZ/G2N
  21. - renesas,usb2-phy-r8a774c0 # RZ/G2E
  22. - renesas,usb2-phy-r8a774e1 # RZ/G2H
  23. - renesas,usb2-phy-r8a7795 # R-Car H3
  24. - renesas,usb2-phy-r8a7796 # R-Car M3-W
  25. - renesas,usb2-phy-r8a77961 # R-Car M3-W+
  26. - renesas,usb2-phy-r8a77965 # R-Car M3-N
  27. - renesas,usb2-phy-r8a77990 # R-Car E3
  28. - renesas,usb2-phy-r8a77995 # R-Car D3
  29. - const: renesas,rcar-gen3-usb2-phy
  30. - items:
  31. - enum:
  32. - renesas,usb2-phy-r9a07g043 # RZ/G2UL
  33. - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
  34. - renesas,usb2-phy-r9a07g054 # RZ/V2L
  35. - const: renesas,rzg2l-usb2-phy
  36. reg:
  37. maxItems: 1
  38. clocks:
  39. minItems: 1
  40. maxItems: 2
  41. clock-names:
  42. minItems: 1
  43. items:
  44. - const: fck
  45. - const: usb_x1
  46. '#phy-cells':
  47. enum: [0, 1] # and 0 is deprecated.
  48. description: |
  49. The phandle's argument in the PHY specifier is the INT_STATUS bit of
  50. controller.
  51. - 1 = USBH_INTA (OHCI)
  52. - 2 = USBH_INTB (EHCI)
  53. - 3 = UCOM_INT (OTG and BC)
  54. interrupts:
  55. maxItems: 1
  56. power-domains:
  57. maxItems: 1
  58. resets:
  59. minItems: 1
  60. items:
  61. - description: reset of USB 2.0 host side
  62. - description: reset of USB 2.0 peripheral side
  63. vbus-supply:
  64. description: |
  65. Phandle to a regulator that provides power to the VBUS. This regulator
  66. will be managed during the PHY power on/off sequence.
  67. renesas,no-otg-pins:
  68. $ref: /schemas/types.yaml#/definitions/flag
  69. description: |
  70. specify when a board does not provide proper otg pins.
  71. dr_mode: true
  72. if:
  73. properties:
  74. compatible:
  75. contains:
  76. const: renesas,usb2-phy-r7s9210
  77. then:
  78. required:
  79. - clock-names
  80. required:
  81. - compatible
  82. - reg
  83. - clocks
  84. - '#phy-cells'
  85. allOf:
  86. - if:
  87. properties:
  88. compatible:
  89. contains:
  90. const: renesas,rzg2l-usb2-phy
  91. then:
  92. required:
  93. - resets
  94. additionalProperties: false
  95. examples:
  96. - |
  97. #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
  98. #include <dt-bindings/interrupt-controller/arm-gic.h>
  99. #include <dt-bindings/power/r8a7795-sysc.h>
  100. usb-phy@ee080200 {
  101. compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";
  102. reg = <0xee080200 0x700>;
  103. interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  104. clocks = <&cpg CPG_MOD 703>;
  105. #phy-cells = <1>;
  106. };
  107. usb-phy@ee0a0200 {
  108. compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";
  109. reg = <0xee0a0200 0x700>;
  110. clocks = <&cpg CPG_MOD 702>;
  111. #phy-cells = <1>;
  112. };