rockchip-inno-csi-dphy.yaml 1.9 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Rockchip SoC MIPI RX0 D-PHY
  7. maintainers:
  8. - Heiko Stuebner <heiko@sntech.de>
  9. description: |
  10. The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
  11. connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
  12. properties:
  13. compatible:
  14. enum:
  15. - rockchip,px30-csi-dphy
  16. - rockchip,rk1808-csi-dphy
  17. - rockchip,rk3326-csi-dphy
  18. - rockchip,rk3368-csi-dphy
  19. - rockchip,rk3568-csi-dphy
  20. reg:
  21. maxItems: 1
  22. clocks:
  23. maxItems: 1
  24. clock-names:
  25. const: pclk
  26. '#phy-cells':
  27. const: 0
  28. power-domains:
  29. description: Video in/out power domain.
  30. maxItems: 1
  31. resets:
  32. items:
  33. - description: exclusive PHY reset line
  34. reset-names:
  35. items:
  36. - const: apb
  37. rockchip,grf:
  38. $ref: /schemas/types.yaml#/definitions/phandle
  39. description:
  40. Some additional phy settings are access through GRF regs.
  41. required:
  42. - compatible
  43. - reg
  44. - clocks
  45. - clock-names
  46. - '#phy-cells'
  47. - resets
  48. - reset-names
  49. - rockchip,grf
  50. allOf:
  51. - if:
  52. properties:
  53. compatible:
  54. contains:
  55. enum:
  56. - rockchip,px30-csi-dphy
  57. - rockchip,rk1808-csi-dphy
  58. - rockchip,rk3326-csi-dphy
  59. - rockchip,rk3368-csi-dphy
  60. then:
  61. required:
  62. - power-domains
  63. additionalProperties: false
  64. examples:
  65. - |
  66. csi_dphy: phy@ff2f0000 {
  67. compatible = "rockchip,px30-csi-dphy";
  68. reg = <0xff2f0000 0x4000>;
  69. clocks = <&cru 1>;
  70. clock-names = "pclk";
  71. #phy-cells = <0>;
  72. power-domains = <&power 1>;
  73. resets = <&cru 1>;
  74. reset-names = "apb";
  75. rockchip,grf = <&grf>;
  76. };