samsung,ufs-phy.yaml 2.6 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Samsung SoC series UFS PHY
  7. maintainers:
  8. - Alim Akhtar <alim.akhtar@samsung.com>
  9. properties:
  10. "#phy-cells":
  11. const: 0
  12. compatible:
  13. enum:
  14. - google,gs101-ufs-phy
  15. - samsung,exynos7-ufs-phy
  16. - samsung,exynosautov9-ufs-phy
  17. - tesla,fsd-ufs-phy
  18. reg:
  19. maxItems: 1
  20. reg-names:
  21. items:
  22. - const: phy-pma
  23. clocks:
  24. minItems: 1
  25. maxItems: 4
  26. clock-names:
  27. minItems: 1
  28. maxItems: 4
  29. samsung,pmu-syscon:
  30. $ref: /schemas/types.yaml#/definitions/phandle-array
  31. maxItems: 1
  32. items:
  33. minItems: 1
  34. items:
  35. - description: phandle for PMU system controller interface, used to
  36. control pmu registers bits for ufs m-phy
  37. - description: offset of the pmu control register
  38. description:
  39. It can be phandle/offset pair. The second cell which can represent an
  40. offset is optional.
  41. required:
  42. - "#phy-cells"
  43. - compatible
  44. - reg
  45. - reg-names
  46. - clocks
  47. - clock-names
  48. - samsung,pmu-syscon
  49. allOf:
  50. - if:
  51. properties:
  52. compatible:
  53. contains:
  54. const: samsung,exynos7-ufs-phy
  55. then:
  56. properties:
  57. clocks:
  58. items:
  59. - description: PLL reference clock
  60. - description: symbol clock for input symbol (rx0-ch0 symbol clock)
  61. - description: symbol clock for input symbol (rx1-ch1 symbol clock)
  62. - description: symbol clock for output symbol (tx0 symbol clock)
  63. clock-names:
  64. items:
  65. - const: ref_clk
  66. - const: rx1_symbol_clk
  67. - const: rx0_symbol_clk
  68. - const: tx0_symbol_clk
  69. else:
  70. properties:
  71. clocks:
  72. items:
  73. - description: PLL reference clock
  74. clock-names:
  75. items:
  76. - const: ref_clk
  77. additionalProperties: false
  78. examples:
  79. - |
  80. #include <dt-bindings/clock/exynos7-clk.h>
  81. ufs_phy: ufs-phy@15571800 {
  82. compatible = "samsung,exynos7-ufs-phy";
  83. reg = <0x15571800 0x240>;
  84. reg-names = "phy-pma";
  85. samsung,pmu-syscon = <&pmu_system_controller>;
  86. #phy-cells = <0>;
  87. clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
  88. <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
  89. <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
  90. <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
  91. clock-names = "ref_clk", "rx1_symbol_clk",
  92. "rx0_symbol_clk", "tx0_symbol_clk";
  93. };
  94. ...