samsung,usb3-drd-phy.yaml 5.0 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
  7. maintainers:
  8. - Krzysztof Kozlowski <krzk@kernel.org>
  9. - Marek Szyprowski <m.szyprowski@samsung.com>
  10. - Sylwester Nawrocki <s.nawrocki@samsung.com>
  11. description: |
  12. For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
  13. compatible PHYs, the second cell in the PHY specifier identifies the
  14. PHY id, which is interpreted as follows::
  15. 0 - UTMI+ type phy,
  16. 1 - PIPE3 type phy.
  17. For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
  18. 'usbdrd_phy' nodes should have numbered alias in the aliases node, in the
  19. form of usbdrdphyN, N = 0, 1... (depending on number of controllers).
  20. properties:
  21. compatible:
  22. enum:
  23. - google,gs101-usb31drd-phy
  24. - samsung,exynos5250-usbdrd-phy
  25. - samsung,exynos5420-usbdrd-phy
  26. - samsung,exynos5433-usbdrd-phy
  27. - samsung,exynos7-usbdrd-phy
  28. - samsung,exynos850-usbdrd-phy
  29. clocks:
  30. minItems: 2
  31. maxItems: 5
  32. clock-names:
  33. minItems: 2
  34. maxItems: 5
  35. description: |
  36. At least two clocks::
  37. - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
  38. for register access.
  39. - PHY reference clock (usually crystal clock), used for PHY operations,
  40. associated by phy name. It is used to determine bit values for clock
  41. settings register. For Exynos5420 this is given as 'sclk_usbphy30'
  42. in the CMU.
  43. "#phy-cells":
  44. const: 1
  45. port:
  46. $ref: /schemas/graph.yaml#/properties/port
  47. description:
  48. Any connector to the data bus of this controller should be modelled using
  49. the OF graph bindings specified.
  50. reg:
  51. minItems: 1
  52. maxItems: 3
  53. reg-names:
  54. minItems: 1
  55. items:
  56. - const: phy
  57. - const: pcs
  58. - const: pma
  59. samsung,pmu-syscon:
  60. $ref: /schemas/types.yaml#/definitions/phandle
  61. description:
  62. Phandle to PMU system controller interface.
  63. vbus-supply:
  64. description:
  65. VBUS power source.
  66. vbus-boost-supply:
  67. description:
  68. VBUS Boost 5V power source.
  69. pll-supply:
  70. description: Power supply for the USB PLL.
  71. dvdd-usb20-supply:
  72. description: DVDD power supply for the USB 2.0 phy.
  73. vddh-usb20-supply:
  74. description: VDDh power supply for the USB 2.0 phy.
  75. vdd33-usb20-supply:
  76. description: 3.3V power supply for the USB 2.0 phy.
  77. vdda-usbdp-supply:
  78. description: VDDa power supply for the USB DP phy.
  79. vddh-usbdp-supply:
  80. description: VDDh power supply for the USB DP phy.
  81. required:
  82. - compatible
  83. - clocks
  84. - clock-names
  85. - "#phy-cells"
  86. - reg
  87. - samsung,pmu-syscon
  88. allOf:
  89. - if:
  90. properties:
  91. compatible:
  92. contains:
  93. const: google,gs101-usb31drd-phy
  94. then:
  95. properties:
  96. clocks:
  97. items:
  98. - description: Gate of main PHY clock
  99. - description: Gate of PHY reference clock
  100. - description: Gate of control interface AXI clock
  101. - description: Gate of control interface APB clock
  102. - description: Gate of SCL APB clock
  103. clock-names:
  104. items:
  105. - const: phy
  106. - const: ref
  107. - const: ctrl_aclk
  108. - const: ctrl_pclk
  109. - const: scl_pclk
  110. reg:
  111. minItems: 3
  112. reg-names:
  113. minItems: 3
  114. required:
  115. - reg-names
  116. - pll-supply
  117. - dvdd-usb20-supply
  118. - vddh-usb20-supply
  119. - vdd33-usb20-supply
  120. - vdda-usbdp-supply
  121. - vddh-usbdp-supply
  122. - if:
  123. properties:
  124. compatible:
  125. contains:
  126. enum:
  127. - samsung,exynos5433-usbdrd-phy
  128. - samsung,exynos7-usbdrd-phy
  129. then:
  130. properties:
  131. clocks:
  132. minItems: 5
  133. maxItems: 5
  134. clock-names:
  135. items:
  136. - const: phy
  137. - const: ref
  138. - const: phy_utmi
  139. - const: phy_pipe
  140. - const: itp
  141. reg:
  142. maxItems: 1
  143. reg-names:
  144. maxItems: 1
  145. - if:
  146. properties:
  147. compatible:
  148. contains:
  149. enum:
  150. - samsung,exynos5250-usbdrd-phy
  151. - samsung,exynos5420-usbdrd-phy
  152. - samsung,exynos850-usbdrd-phy
  153. then:
  154. properties:
  155. clocks:
  156. minItems: 2
  157. maxItems: 2
  158. clock-names:
  159. items:
  160. - const: phy
  161. - const: ref
  162. reg:
  163. maxItems: 1
  164. reg-names:
  165. maxItems: 1
  166. additionalProperties: false
  167. examples:
  168. - |
  169. #include <dt-bindings/clock/exynos5420.h>
  170. phy@12100000 {
  171. compatible = "samsung,exynos5420-usbdrd-phy";
  172. reg = <0x12100000 0x100>;
  173. #phy-cells = <1>;
  174. clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
  175. clock-names = "phy", "ref";
  176. samsung,pmu-syscon = <&pmu_system_controller>;
  177. vbus-supply = <&usb300_vbus_reg>;
  178. };