fsl-imx-uart.yaml 3.8 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
  7. maintainers:
  8. - Fabio Estevam <festevam@gmail.com>
  9. properties:
  10. compatible:
  11. oneOf:
  12. - const: fsl,imx1-uart
  13. - const: fsl,imx21-uart
  14. - items:
  15. - enum:
  16. - fsl,imx25-uart
  17. - fsl,imx27-uart
  18. - fsl,imx31-uart
  19. - fsl,imx35-uart
  20. - fsl,imx50-uart
  21. - fsl,imx51-uart
  22. - fsl,imx53-uart
  23. - fsl,imx6q-uart
  24. - const: fsl,imx21-uart
  25. - items:
  26. - enum:
  27. - fsl,imx6sl-uart
  28. - fsl,imx6sll-uart
  29. - fsl,imx6sx-uart
  30. - const: fsl,imx6q-uart
  31. - const: fsl,imx21-uart
  32. - items:
  33. - enum:
  34. - fsl,imx6ul-uart
  35. - fsl,imx7d-uart
  36. - fsl,imx8mm-uart
  37. - fsl,imx8mn-uart
  38. - fsl,imx8mp-uart
  39. - fsl,imx8mq-uart
  40. - const: fsl,imx6q-uart
  41. reg:
  42. maxItems: 1
  43. clocks:
  44. maxItems: 2
  45. clock-names:
  46. items:
  47. - const: ipg
  48. - const: per
  49. dmas:
  50. items:
  51. - description: DMA controller phandle and request line for RX
  52. - description: DMA controller phandle and request line for TX
  53. dma-names:
  54. items:
  55. - const: rx
  56. - const: tx
  57. interrupts:
  58. items:
  59. - description: UART RX Interrupt
  60. - description: UART TX Interrupt
  61. - description: UART RTS Interrupt
  62. minItems: 1
  63. wakeup-source: true
  64. fsl,dte-mode:
  65. $ref: /schemas/types.yaml#/definitions/flag
  66. description: |
  67. Indicate the uart works in DTE mode. The uart works in DCE mode by default.
  68. fsl,inverted-tx:
  69. $ref: /schemas/types.yaml#/definitions/flag
  70. description: |
  71. Indicate that the hardware attached to the peripheral inverts the signal
  72. transmitted, and that the peripheral should invert its output using the
  73. INVT registers.
  74. fsl,inverted-rx:
  75. $ref: /schemas/types.yaml#/definitions/flag
  76. description: |
  77. Indicate that the hardware attached to the peripheral inverts the signal
  78. received, and that the peripheral should invert its input using the
  79. INVR registers.
  80. fsl,dma-info:
  81. $ref: /schemas/types.yaml#/definitions/uint32-array
  82. minItems: 2
  83. maxItems: 2
  84. description: |
  85. First cell contains the size of DMA buffer chunks, second cell contains
  86. the amount of chunks used for the device. Multiplying both numbers is
  87. the total size of memory used for receiving data.
  88. When not being configured the system will use default settings, which
  89. are sensible for most use cases. If you need low latency processing on
  90. slow connections this needs to be configured appropriately.
  91. required:
  92. - compatible
  93. - reg
  94. - clocks
  95. - clock-names
  96. - interrupts
  97. allOf:
  98. - $ref: serial.yaml#
  99. - $ref: rs485.yaml#
  100. - if:
  101. properties:
  102. compatible:
  103. contains:
  104. const: fsl,imx1-uart
  105. then:
  106. properties:
  107. interrupts:
  108. minItems: 3
  109. maxItems: 3
  110. else:
  111. properties:
  112. interrupts:
  113. maxItems: 1
  114. unevaluatedProperties: false
  115. examples:
  116. - |
  117. #include <dt-bindings/clock/imx5-clock.h>
  118. aliases {
  119. serial0 = &uart1;
  120. };
  121. uart1: serial@73fbc000 {
  122. compatible = "fsl,imx51-uart", "fsl,imx21-uart";
  123. reg = <0x73fbc000 0x4000>;
  124. interrupts = <31>;
  125. clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
  126. <&clks IMX5_CLK_UART1_PER_GATE>;
  127. clock-names = "ipg", "per";
  128. dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
  129. dma-names = "rx", "tx";
  130. uart-has-rtscts;
  131. fsl,dte-mode;
  132. };