nvidia,tegra124-soctherm.yaml 13 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: NVIDIA Tegra124 SOCTHERM Thermal Management System
  7. maintainers:
  8. - Thierry Reding <thierry.reding@gmail.com>
  9. - Jon Hunter <jonathanh@nvidia.com>
  10. description: The SOCTHERM IP block contains thermal sensors, support for
  11. polled or interrupt-based thermal monitoring, CPU and GPU throttling based
  12. on temperature trip points, and handling external overcurrent notifications.
  13. It is also used to manage emergency shutdown in an overheating situation.
  14. properties:
  15. compatible:
  16. enum:
  17. - nvidia,tegra124-soctherm
  18. - nvidia,tegra132-soctherm
  19. - nvidia,tegra210-soctherm
  20. reg:
  21. maxItems: 2
  22. reg-names:
  23. maxItems: 2
  24. interrupts:
  25. items:
  26. - description: module interrupt
  27. - description: EDP interrupt
  28. interrupt-names:
  29. items:
  30. - const: thermal
  31. - const: edp
  32. clocks:
  33. items:
  34. - description: thermal sensor clock
  35. - description: module clock
  36. clock-names:
  37. items:
  38. - const: tsensor
  39. - const: soctherm
  40. resets:
  41. items:
  42. - description: module reset
  43. reset-names:
  44. items:
  45. - const: soctherm
  46. "#thermal-sensor-cells":
  47. const: 1
  48. throttle-cfgs:
  49. $ref: thermal-cooling-devices.yaml
  50. description: A sub-node which is a container of configuration for each
  51. hardware throttle events. These events can be set as cooling devices.
  52. Throttle event sub-nodes must be named as "light" or "heavy".
  53. unevaluatedProperties: false
  54. patternProperties:
  55. "^(light|heavy|oc1)$":
  56. type: object
  57. additionalProperties: false
  58. properties:
  59. "#cooling-cells":
  60. const: 2
  61. nvidia,priority:
  62. $ref: /schemas/types.yaml#/definitions/uint32
  63. minimum: 1
  64. maximum: 100
  65. description: Each throttles has its own throttle settings, so the
  66. SW need to set priorities for various throttle, the HW arbiter
  67. can select the final throttle settings. Bigger value indicates
  68. higher priority, In general, higher priority translates to lower
  69. target frequency. SW needs to ensure that critical thermal
  70. alarms are given higher priority, and ensure that there is no
  71. race if priority of two vectors is set to the same value.
  72. nvidia,cpu-throt-percent:
  73. description: This property is for Tegra124 and Tegra210. It is the
  74. throttling depth of pulse skippers, it's the percentage
  75. throttling.
  76. minimum: 0
  77. maximum: 100
  78. nvidia,cpu-throt-level:
  79. $ref: /schemas/types.yaml#/definitions/uint32
  80. description: This property is only for Tegra132, it is the level
  81. of pulse skippers, which used to throttle clock frequencies. It
  82. indicates cpu clock throttling depth, and the depth can be
  83. programmed.
  84. enum:
  85. # none (TEGRA_SOCTHERM_THROT_LEVEL_NONE)
  86. - 0
  87. # low (TEGRA_SOCTHERM_THROT_LEVEL_LOW)
  88. - 1
  89. # medium (TEGRA_SOCTHERM_THROT_LEVEL_MED)
  90. - 2
  91. # high (TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
  92. - 3
  93. nvidia,gpu-throt-level:
  94. $ref: /schemas/types.yaml#/definitions/uint32
  95. description: This property is for Tegra124 and Tegra210. It is the
  96. level of pulse skippers, which used to throttle clock
  97. frequencies. It indicates gpu clock throttling depth and can be
  98. programmed to any of the following values which represent a
  99. throttling percentage.
  100. enum:
  101. # none (0%, TEGRA_SOCTHERM_THROT_LEVEL_NONE)
  102. - 0
  103. # low (50%, TEGRA_SOCTHERM_THROT_LEVEL_LOW)
  104. - 1
  105. # medium (75%, TEGRA_SOCTHERM_THROT_LEVEL_MED)
  106. - 2
  107. # high (85%, TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
  108. - 3
  109. # optional
  110. # Tegra210 specific and valid only for OCx throttle events
  111. nvidia,count-threshold:
  112. $ref: /schemas/types.yaml#/definitions/uint32
  113. description: Specifies the number of OC events that are required
  114. for triggering an interrupt. Interrupts are not triggered if the
  115. property is missing. A value of 0 will interrupt on every OC
  116. alarm.
  117. nvidia,polarity-active-low:
  118. $ref: /schemas/types.yaml#/definitions/flag
  119. description: Configures the polarity of the OC alaram signal. If
  120. present, this means assert low, otherwise assert high.
  121. nvidia,alarm-filter:
  122. $ref: /schemas/types.yaml#/definitions/uint32
  123. description: Number of clocks to filter event. When the filter
  124. expires (which means the OC event has not occurred for a long
  125. time), the counter is cleared and filter is rearmed.
  126. default: 0
  127. nvidia,throttle-period-us:
  128. description: Specifies the number of microseconds for which
  129. throttling is engaged after the OC event is deasserted.
  130. default: 0
  131. # optional
  132. nvidia,thermtrips:
  133. $ref: /schemas/types.yaml#/definitions/uint32-matrix
  134. description: |
  135. When present, this property specifies the temperature at which the
  136. SOCTHERM hardware will assert the thermal trigger signal to the Power
  137. Management IC, which can be configured to reset or shutdown the device.
  138. It is an array of pairs where each pair represents a tsensor ID followed
  139. by a temperature in milli Celcius. In the absence of this property the
  140. critical trip point will be used for thermtrip temperature.
  141. Note:
  142. - the "critical" type trip points will be used to set the temperature at
  143. which the SOCTHERM hardware will assert a thermal trigger if the
  144. "nvidia,thermtrips" property is missing. When the thermtrips property
  145. is present, the breach of a critical trip point is reported back to
  146. the thermal framework to implement software shutdown.
  147. - the "hot" type trip points will be set to SOCTHERM hardware as the
  148. throttle temperature. Once the temperature of this thermal zone is
  149. higher than it, it will trigger the HW throttle event.
  150. items:
  151. items:
  152. - description: sensor ID
  153. oneOf:
  154. - description: CPU sensor
  155. const: 0
  156. - description: MEM sensor
  157. const: 1
  158. - description: GPU sensor
  159. const: 2
  160. - description: PLLX sensor
  161. const: 3
  162. - description: temperature threshold (in millidegree Celsius)
  163. required:
  164. - compatible
  165. - reg
  166. - reg-names
  167. - interrupts
  168. - interrupt-names
  169. - clocks
  170. - clock-names
  171. - resets
  172. - reset-names
  173. allOf:
  174. - $ref: thermal-sensor.yaml
  175. - if:
  176. properties:
  177. compatible:
  178. contains:
  179. enum:
  180. - nvidia,tegra124-soctherm
  181. - nvidia,tegra210-soctherm
  182. then:
  183. properties:
  184. reg:
  185. items:
  186. - description: SOCTHERM register set
  187. - description: clock and reset controller registers
  188. reg-names:
  189. items:
  190. - const: soctherm-reg
  191. - const: car-reg
  192. else:
  193. properties:
  194. reg:
  195. items:
  196. - description: SOCTHERM register set
  197. - description: CCROC registers
  198. reg-names:
  199. items:
  200. - const: soctherm-reg
  201. - const: ccroc-reg
  202. additionalProperties: false
  203. examples:
  204. - |
  205. #include <dt-bindings/clock/tegra124-car.h>
  206. #include <dt-bindings/interrupt-controller/arm-gic.h>
  207. #include <dt-bindings/thermal/tegra124-soctherm.h>
  208. soctherm@700e2000 {
  209. compatible = "nvidia,tegra124-soctherm";
  210. reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */
  211. <0x60006000 0x400>; /* CAR reg_base */
  212. reg-names = "soctherm-reg", "car-reg";
  213. interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
  214. <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
  215. interrupt-names = "thermal", "edp";
  216. clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
  217. <&tegra_car TEGRA124_CLK_SOC_THERM>;
  218. clock-names = "tsensor", "soctherm";
  219. resets = <&tegra_car 78>;
  220. reset-names = "soctherm";
  221. #thermal-sensor-cells = <1>;
  222. nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500>,
  223. <TEGRA124_SOCTHERM_SENSOR_GPU 103000>;
  224. throttle-cfgs {
  225. /*
  226. * When the "heavy" cooling device triggered,
  227. * the HW will skip cpu clock's pulse in 85% depth,
  228. * skip gpu clock's pulse in 85% level
  229. */
  230. heavy {
  231. nvidia,priority = <100>;
  232. nvidia,cpu-throt-percent = <85>;
  233. nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
  234. #cooling-cells = <2>;
  235. };
  236. /*
  237. * When the "light" cooling device triggered,
  238. * the HW will skip cpu clock's pulse in 50% depth,
  239. * skip gpu clock's pulse in 50% level
  240. */
  241. light {
  242. nvidia,priority = <80>;
  243. nvidia,cpu-throt-percent = <50>;
  244. nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>;
  245. #cooling-cells = <2>;
  246. };
  247. /*
  248. * If these two devices are triggered in same time, the HW throttle
  249. * arbiter will select the highest priority as the final throttle
  250. * settings to skip cpu pulse.
  251. */
  252. oc1 {
  253. nvidia,priority = <50>;
  254. nvidia,polarity-active-low;
  255. nvidia,count-threshold = <100>;
  256. nvidia,alarm-filter = <5100000>;
  257. nvidia,throttle-period-us = <0>;
  258. nvidia,cpu-throt-percent = <75>;
  259. nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
  260. };
  261. };
  262. };
  263. # referring to Tegra132's "reg", "reg-names" and "throttle-cfgs"
  264. - |
  265. thermal-sensor@700e2000 {
  266. compatible = "nvidia,tegra132-soctherm";
  267. reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */
  268. <0x70040000 0x200>; /* CCROC reg_base */
  269. reg-names = "soctherm-reg", "ccroc-reg";
  270. interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
  271. <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
  272. interrupt-names = "thermal", "edp";
  273. clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
  274. <&tegra_car TEGRA124_CLK_SOC_THERM>;
  275. clock-names = "tsensor", "soctherm";
  276. resets = <&tegra_car 78>;
  277. reset-names = "soctherm";
  278. #thermal-sensor-cells = <1>;
  279. throttle-cfgs {
  280. /*
  281. * When the "heavy" cooling device triggered,
  282. * the HW will skip cpu clock's pulse in HIGH level
  283. */
  284. heavy {
  285. nvidia,priority = <100>;
  286. nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
  287. #cooling-cells = <2>;
  288. };
  289. /*
  290. * When the "light" cooling device triggered,
  291. * the HW will skip cpu clock's pulse in MED level
  292. */
  293. light {
  294. nvidia,priority = <80>;
  295. nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
  296. #cooling-cells = <2>;
  297. };
  298. /*
  299. * If these two devices are triggered in same time, the HW throttle
  300. * arbiter will select the highest priority as the final throttle
  301. * settings to skip cpu pulse.
  302. */
  303. };
  304. };
  305. # referring to thermal sensors
  306. - |
  307. thermal-zones {
  308. cpu-thermal {
  309. polling-delay-passive = <1000>;
  310. polling-delay = <1000>;
  311. thermal-sensors = <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
  312. trips {
  313. cpu_shutdown_trip: shutdown-trip {
  314. temperature = <102500>;
  315. hysteresis = <1000>;
  316. type = "critical";
  317. };
  318. cpu_throttle_trip: throttle-trip {
  319. temperature = <100000>;
  320. hysteresis = <1000>;
  321. type = "hot";
  322. };
  323. };
  324. cooling-maps {
  325. map0 {
  326. trip = <&cpu_throttle_trip>;
  327. cooling-device = <&throttle_heavy 1 1>;
  328. };
  329. };
  330. };
  331. };