cdns,ttc.yaml 1.3 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/timer/cdns,ttc.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Cadence TTC - Triple Timer Counter
  7. maintainers:
  8. - Michal Simek <michal.simek@amd.com>
  9. properties:
  10. compatible:
  11. const: cdns,ttc
  12. reg:
  13. maxItems: 1
  14. interrupts:
  15. maxItems: 3
  16. description: |
  17. A list of 3 interrupts; one per timer channel.
  18. clocks:
  19. maxItems: 1
  20. power-domains:
  21. maxItems: 1
  22. timer-width:
  23. $ref: /schemas/types.yaml#/definitions/uint32
  24. description: |
  25. Bit width of the timer, necessary if not 16.
  26. "#pwm-cells":
  27. const: 3
  28. required:
  29. - compatible
  30. - reg
  31. - clocks
  32. allOf:
  33. - if:
  34. not:
  35. required:
  36. - "#pwm-cells"
  37. then:
  38. required:
  39. - interrupts
  40. additionalProperties: false
  41. examples:
  42. - |
  43. ttc0: ttc0@f8001000 {
  44. interrupt-parent = <&intc>;
  45. interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
  46. compatible = "cdns,ttc";
  47. reg = <0xF8001000 0x1000>;
  48. clocks = <&cpu_clk 3>;
  49. timer-width = <32>;
  50. };
  51. - |
  52. pwm: pwm@f8002000 {
  53. compatible = "cdns,ttc";
  54. reg = <0xf8002000 0x1000>;
  55. clocks = <&cpu_clk 3>;
  56. timer-width = <32>;
  57. #pwm-cells = <3>;
  58. };