mm-imx3.c 3.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 1999,2000 Arm Limited
  4. * Copyright (C) 2000 Deep Blue Solutions Ltd
  5. * Copyright (C) 2002 Shane Nay (shane@minirl.com)
  6. * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  7. * - add MX31 specific definitions
  8. */
  9. #include <linux/mm.h>
  10. #include <linux/init.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/of_address.h>
  14. #include <asm/system_misc.h>
  15. #include <asm/hardware/cache-l2x0.h>
  16. #include <asm/mach/map.h>
  17. #include "common.h"
  18. #include "crmregs-imx3.h"
  19. #include "hardware.h"
  20. void __iomem *mx3_ccm_base;
  21. static void imx3_idle(void)
  22. {
  23. unsigned long reg = 0;
  24. __asm__ __volatile__(
  25. /* disable I and D cache */
  26. "mrc p15, 0, %0, c1, c0, 0\n"
  27. "bic %0, %0, #0x00001000\n"
  28. "bic %0, %0, #0x00000004\n"
  29. "mcr p15, 0, %0, c1, c0, 0\n"
  30. /* invalidate I cache */
  31. "mov %0, #0\n"
  32. "mcr p15, 0, %0, c7, c5, 0\n"
  33. /* clear and invalidate D cache */
  34. "mov %0, #0\n"
  35. "mcr p15, 0, %0, c7, c14, 0\n"
  36. /* WFI */
  37. "mov %0, #0\n"
  38. "mcr p15, 0, %0, c7, c0, 4\n"
  39. "nop\n" "nop\n" "nop\n" "nop\n"
  40. "nop\n" "nop\n" "nop\n"
  41. /* enable I and D cache */
  42. "mrc p15, 0, %0, c1, c0, 0\n"
  43. "orr %0, %0, #0x00001000\n"
  44. "orr %0, %0, #0x00000004\n"
  45. "mcr p15, 0, %0, c1, c0, 0\n"
  46. : "=r" (reg));
  47. }
  48. static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
  49. unsigned int mtype, void *caller)
  50. {
  51. if (mtype == MT_DEVICE) {
  52. /*
  53. * Access all peripherals below 0x80000000 as nonshared device
  54. * on mx3, but leave l2cc alone. Otherwise cache corruptions
  55. * can occur.
  56. */
  57. if (phys_addr < 0x80000000 &&
  58. !addr_in_module(phys_addr, MX3x_L2CC))
  59. mtype = MT_DEVICE_NONSHARED;
  60. }
  61. return __arm_ioremap_caller(phys_addr, size, mtype, caller);
  62. }
  63. #ifdef CONFIG_SOC_IMX31
  64. static struct map_desc mx31_io_desc[] __initdata = {
  65. imx_map_entry(MX31, X_MEMC, MT_DEVICE),
  66. imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
  67. imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
  68. imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
  69. imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
  70. };
  71. /*
  72. * This function initializes the memory map. It is called during the
  73. * system startup to create static physical to virtual memory mappings
  74. * for the IO modules.
  75. */
  76. void __init mx31_map_io(void)
  77. {
  78. iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
  79. }
  80. static void imx31_idle(void)
  81. {
  82. int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
  83. reg &= ~MXC_CCM_CCMR_LPM_MASK;
  84. imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
  85. imx3_idle();
  86. }
  87. void __init imx31_init_early(void)
  88. {
  89. struct device_node *np;
  90. mxc_set_cpu_type(MXC_CPU_MX31);
  91. arch_ioremap_caller = imx3_ioremap_caller;
  92. arm_pm_idle = imx31_idle;
  93. np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
  94. mx3_ccm_base = of_iomap(np, 0);
  95. BUG_ON(!mx3_ccm_base);
  96. }
  97. #endif /* ifdef CONFIG_SOC_IMX31 */
  98. #ifdef CONFIG_SOC_IMX35
  99. static struct map_desc mx35_io_desc[] __initdata = {
  100. imx_map_entry(MX35, X_MEMC, MT_DEVICE),
  101. imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
  102. imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
  103. imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
  104. imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
  105. };
  106. void __init mx35_map_io(void)
  107. {
  108. iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
  109. }
  110. static void imx35_idle(void)
  111. {
  112. int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
  113. reg &= ~MXC_CCM_CCMR_LPM_MASK;
  114. reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
  115. imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
  116. imx3_idle();
  117. }
  118. void __init imx35_init_early(void)
  119. {
  120. struct device_node *np;
  121. mxc_set_cpu_type(MXC_CPU_MX35);
  122. arm_pm_idle = imx35_idle;
  123. arch_ioremap_caller = imx3_ioremap_caller;
  124. np = of_find_compatible_node(NULL, NULL, "fsl,imx35-ccm");
  125. mx3_ccm_base = of_iomap(np, 0);
  126. BUG_ON(!mx3_ccm_base);
  127. }
  128. #endif /* ifdef CONFIG_SOC_IMX35 */