mt7986a-rfb.dts 6.1 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright (C) 2021 MediaTek Inc.
  4. * Author: Sam.Shih <sam.shih@mediatek.com>
  5. */
  6. /dts-v1/;
  7. #include <dt-bindings/pinctrl/mt65xx.h>
  8. #include "mt7986a.dtsi"
  9. / {
  10. model = "MediaTek MT7986a RFB";
  11. chassis-type = "embedded";
  12. compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
  13. aliases {
  14. serial0 = &uart0;
  15. };
  16. chosen {
  17. stdout-path = "serial0:115200n8";
  18. };
  19. memory@40000000 {
  20. device_type = "memory";
  21. reg = <0 0x40000000 0 0x40000000>;
  22. };
  23. reg_1p8v: regulator-1p8v {
  24. compatible = "regulator-fixed";
  25. regulator-name = "fixed-1.8V";
  26. regulator-min-microvolt = <1800000>;
  27. regulator-max-microvolt = <1800000>;
  28. regulator-boot-on;
  29. regulator-always-on;
  30. };
  31. reg_3p3v: regulator-3p3v {
  32. compatible = "regulator-fixed";
  33. regulator-name = "fixed-3.3V";
  34. regulator-min-microvolt = <3300000>;
  35. regulator-max-microvolt = <3300000>;
  36. regulator-boot-on;
  37. regulator-always-on;
  38. };
  39. };
  40. &crypto {
  41. status = "okay";
  42. };
  43. &eth {
  44. status = "okay";
  45. gmac0: mac@0 {
  46. compatible = "mediatek,eth-mac";
  47. reg = <0>;
  48. phy-mode = "2500base-x";
  49. fixed-link {
  50. speed = <2500>;
  51. full-duplex;
  52. pause;
  53. };
  54. };
  55. gmac1: mac@1 {
  56. compatible = "mediatek,eth-mac";
  57. reg = <1>;
  58. phy-mode = "rgmii";
  59. fixed-link {
  60. speed = <1000>;
  61. full-duplex;
  62. pause;
  63. };
  64. };
  65. mdio: mdio-bus {
  66. #address-cells = <1>;
  67. #size-cells = <0>;
  68. };
  69. };
  70. &mdio {
  71. switch: switch@0 {
  72. compatible = "mediatek,mt7531";
  73. reg = <31>;
  74. reset-gpios = <&pio 5 0>;
  75. };
  76. };
  77. &mmc0 {
  78. pinctrl-names = "default", "state_uhs";
  79. pinctrl-0 = <&mmc0_pins_default>;
  80. pinctrl-1 = <&mmc0_pins_uhs>;
  81. bus-width = <8>;
  82. max-frequency = <200000000>;
  83. cap-mmc-highspeed;
  84. mmc-hs200-1_8v;
  85. mmc-hs400-1_8v;
  86. hs400-ds-delay = <0x14014>;
  87. vmmc-supply = <&reg_3p3v>;
  88. vqmmc-supply = <&reg_1p8v>;
  89. non-removable;
  90. no-sd;
  91. no-sdio;
  92. };
  93. &pcie {
  94. pinctrl-names = "default";
  95. pinctrl-0 = <&pcie_pins>;
  96. status = "okay";
  97. };
  98. &pcie_phy {
  99. status = "okay";
  100. };
  101. &pio {
  102. mmc0_pins_default: mmc0-pins {
  103. mux {
  104. function = "emmc";
  105. groups = "emmc_51";
  106. };
  107. conf-cmd-dat {
  108. pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
  109. "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
  110. "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
  111. input-enable;
  112. drive-strength = <4>;
  113. bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
  114. };
  115. conf-clk {
  116. pins = "EMMC_CK";
  117. drive-strength = <6>;
  118. bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
  119. };
  120. conf-ds {
  121. pins = "EMMC_DSL";
  122. bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
  123. };
  124. conf-rst {
  125. pins = "EMMC_RSTB";
  126. drive-strength = <4>;
  127. bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
  128. };
  129. };
  130. mmc0_pins_uhs: mmc0-uhs-pins {
  131. mux {
  132. function = "emmc";
  133. groups = "emmc_51";
  134. };
  135. conf-cmd-dat {
  136. pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
  137. "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
  138. "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
  139. input-enable;
  140. drive-strength = <4>;
  141. bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
  142. };
  143. conf-clk {
  144. pins = "EMMC_CK";
  145. drive-strength = <6>;
  146. bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
  147. };
  148. conf-ds {
  149. pins = "EMMC_DSL";
  150. bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
  151. };
  152. conf-rst {
  153. pins = "EMMC_RSTB";
  154. drive-strength = <4>;
  155. bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
  156. };
  157. };
  158. pcie_pins: pcie-pins {
  159. mux {
  160. function = "pcie";
  161. groups = "pcie_clk", "pcie_wake", "pcie_pereset";
  162. };
  163. };
  164. spi_flash_pins: spi-flash-pins {
  165. mux {
  166. function = "spi";
  167. groups = "spi0", "spi0_wp_hold";
  168. };
  169. };
  170. spic_pins: spic-pins {
  171. mux {
  172. function = "spi";
  173. groups = "spi1_2";
  174. };
  175. };
  176. uart1_pins: uart1-pins {
  177. mux {
  178. function = "uart";
  179. groups = "uart1";
  180. };
  181. };
  182. uart2_pins: uart2-pins {
  183. mux {
  184. function = "uart";
  185. groups = "uart2";
  186. };
  187. };
  188. wf_2g_5g_pins: wf-2g-5g-pins {
  189. mux {
  190. function = "wifi";
  191. groups = "wf_2g", "wf_5g";
  192. };
  193. conf {
  194. pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  195. "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  196. "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  197. "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
  198. "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
  199. "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
  200. "WF1_TOP_CLK", "WF1_TOP_DATA";
  201. drive-strength = <4>;
  202. };
  203. };
  204. wf_dbdc_pins: wf-dbdc-pins {
  205. mux {
  206. function = "wifi";
  207. groups = "wf_dbdc";
  208. };
  209. conf {
  210. pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  211. "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  212. "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  213. "WF0_TOP_CLK", "WF0_TOP_DATA";
  214. drive-strength = <4>;
  215. };
  216. };
  217. };
  218. &spi0 {
  219. pinctrl-names = "default";
  220. pinctrl-0 = <&spi_flash_pins>;
  221. cs-gpios = <0>, <0>;
  222. status = "okay";
  223. spi_nand: flash@0 {
  224. compatible = "spi-nand";
  225. reg = <0>;
  226. spi-max-frequency = <10000000>;
  227. spi-tx-bus-width = <4>;
  228. spi-rx-bus-width = <4>;
  229. };
  230. };
  231. &spi1 {
  232. pinctrl-names = "default";
  233. pinctrl-0 = <&spic_pins>;
  234. cs-gpios = <0>, <0>;
  235. status = "okay";
  236. };
  237. &ssusb {
  238. status = "okay";
  239. };
  240. &switch {
  241. ports {
  242. #address-cells = <1>;
  243. #size-cells = <0>;
  244. port@0 {
  245. reg = <0>;
  246. label = "lan0";
  247. };
  248. port@1 {
  249. reg = <1>;
  250. label = "lan1";
  251. };
  252. port@2 {
  253. reg = <2>;
  254. label = "lan2";
  255. };
  256. port@3 {
  257. reg = <3>;
  258. label = "lan3";
  259. };
  260. port@4 {
  261. reg = <4>;
  262. label = "lan4";
  263. };
  264. port@5 {
  265. reg = <5>;
  266. ethernet = <&gmac1>;
  267. phy-mode = "rgmii";
  268. fixed-link {
  269. speed = <1000>;
  270. full-duplex;
  271. pause;
  272. };
  273. };
  274. port@6 {
  275. reg = <6>;
  276. label = "cpu";
  277. ethernet = <&gmac0>;
  278. phy-mode = "2500base-x";
  279. fixed-link {
  280. speed = <2500>;
  281. full-duplex;
  282. pause;
  283. };
  284. };
  285. };
  286. };
  287. &uart0 {
  288. status = "okay";
  289. };
  290. &uart1 {
  291. pinctrl-names = "default";
  292. pinctrl-0 = <&uart1_pins>;
  293. status = "okay";
  294. };
  295. &uart2 {
  296. pinctrl-names = "default";
  297. pinctrl-0 = <&uart2_pins>;
  298. status = "okay";
  299. };
  300. &usb_phy {
  301. status = "okay";
  302. };
  303. &wifi {
  304. status = "okay";
  305. pinctrl-names = "default", "dbdc";
  306. pinctrl-0 = <&wf_2g_5g_pins>;
  307. pinctrl-1 = <&wf_dbdc_pins>;
  308. };