cacheflush.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
  3. #include <linux/cache.h>
  4. #include <linux/highmem.h>
  5. #include <linux/mm.h>
  6. #include <asm/cache.h>
  7. #include <asm/tlbflush.h>
  8. void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
  9. unsigned long address, pte_t *pte, unsigned int nr)
  10. {
  11. unsigned long pfn = pte_pfn(*pte);
  12. struct folio *folio;
  13. unsigned int i;
  14. flush_tlb_page(vma, address);
  15. if (!pfn_valid(pfn))
  16. return;
  17. folio = page_folio(pfn_to_page(pfn));
  18. if (test_and_set_bit(PG_dcache_clean, &folio->flags))
  19. return;
  20. icache_inv_range(address, address + nr*PAGE_SIZE);
  21. for (i = 0; i < folio_nr_pages(folio); i++) {
  22. unsigned long addr = (unsigned long) kmap_local_folio(folio,
  23. i * PAGE_SIZE);
  24. dcache_wb_range(addr, addr + PAGE_SIZE);
  25. if (vma->vm_flags & VM_EXEC)
  26. icache_inv_range(addr, addr + PAGE_SIZE);
  27. kunmap_local((void *) addr);
  28. }
  29. }
  30. void flush_icache_deferred(struct mm_struct *mm)
  31. {
  32. unsigned int cpu = smp_processor_id();
  33. cpumask_t *mask = &mm->context.icache_stale_mask;
  34. if (cpumask_test_cpu(cpu, mask)) {
  35. cpumask_clear_cpu(cpu, mask);
  36. /*
  37. * Ensure the remote hart's writes are visible to this hart.
  38. * This pairs with a barrier in flush_icache_mm.
  39. */
  40. smp_mb();
  41. local_icache_inv_all(NULL);
  42. }
  43. }
  44. void flush_icache_mm_range(struct mm_struct *mm,
  45. unsigned long start, unsigned long end)
  46. {
  47. unsigned int cpu;
  48. cpumask_t others, *mask;
  49. preempt_disable();
  50. #ifdef CONFIG_CPU_HAS_ICACHE_INS
  51. if (mm == current->mm) {
  52. icache_inv_range(start, end);
  53. preempt_enable();
  54. return;
  55. }
  56. #endif
  57. /* Mark every hart's icache as needing a flush for this MM. */
  58. mask = &mm->context.icache_stale_mask;
  59. cpumask_setall(mask);
  60. /* Flush this hart's I$ now, and mark it as flushed. */
  61. cpu = smp_processor_id();
  62. cpumask_clear_cpu(cpu, mask);
  63. local_icache_inv_all(NULL);
  64. /*
  65. * Flush the I$ of other harts concurrently executing, and mark them as
  66. * flushed.
  67. */
  68. cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
  69. if (mm != current->active_mm || !cpumask_empty(&others)) {
  70. on_each_cpu_mask(&others, local_icache_inv_all, NULL, 1);
  71. cpumask_clear(mask);
  72. }
  73. preempt_enable();
  74. }