switch_to_64.h 2.4 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __SPARC64_SWITCH_TO_64_H
  3. #define __SPARC64_SWITCH_TO_64_H
  4. #include <asm/visasm.h>
  5. #define prepare_arch_switch(next) \
  6. do { \
  7. flushw_all(); \
  8. } while (0)
  9. /* See what happens when you design the chip correctly?
  10. *
  11. * We tell gcc we clobber all non-fixed-usage registers except
  12. * for l0/l1. It will use one for 'next' and the other to hold
  13. * the output value of 'last'. 'next' is not referenced again
  14. * past the invocation of switch_to in the scheduler, so we need
  15. * not preserve its value. Hairy, but it lets us remove 2 loads
  16. * and 2 stores in this critical code path. -DaveM
  17. */
  18. #define switch_to(prev, next, last) \
  19. do { save_and_clear_fpu(); \
  20. __asm__ __volatile__("wr %%g0, %0, %%asi" \
  21. : : "r" (ASI_AIUS)); \
  22. trap_block[current_thread_info()->cpu].thread = \
  23. task_thread_info(next); \
  24. __asm__ __volatile__( \
  25. "mov %%g4, %%g7\n\t" \
  26. "stx %%i6, [%%sp + 2047 + 0x70]\n\t" \
  27. "stx %%i7, [%%sp + 2047 + 0x78]\n\t" \
  28. "rdpr %%wstate, %%o5\n\t" \
  29. "stx %%o6, [%%g6 + %6]\n\t" \
  30. "stb %%o5, [%%g6 + %5]\n\t" \
  31. "rdpr %%cwp, %%o5\n\t" \
  32. "stb %%o5, [%%g6 + %8]\n\t" \
  33. "wrpr %%g0, 15, %%pil\n\t" \
  34. "mov %4, %%g6\n\t" \
  35. "ldub [%4 + %8], %%g1\n\t" \
  36. "wrpr %%g1, %%cwp\n\t" \
  37. "ldx [%%g6 + %6], %%o6\n\t" \
  38. "ldub [%%g6 + %5], %%o5\n\t" \
  39. "ldub [%%g6 + %7], %%o7\n\t" \
  40. "wrpr %%o5, 0x0, %%wstate\n\t" \
  41. "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \
  42. "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \
  43. "ldx [%%g6 + %9], %%g4\n\t" \
  44. "wrpr %%g0, 14, %%pil\n\t" \
  45. "brz,pt %%o7, switch_to_pc\n\t" \
  46. " mov %%g7, %0\n\t" \
  47. "sethi %%hi(ret_from_fork), %%g1\n\t" \
  48. "jmpl %%g1 + %%lo(ret_from_fork), %%g0\n\t" \
  49. " nop\n\t" \
  50. ".globl switch_to_pc\n\t" \
  51. "switch_to_pc:\n\t" \
  52. : "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \
  53. "=r" (__local_per_cpu_offset) \
  54. : "0" (task_thread_info(next)), \
  55. "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \
  56. "i" (TI_CWP), "i" (TI_TASK) \
  57. : "cc", \
  58. "g1", "g2", "g3", "g7", \
  59. "l1", "l2", "l3", "l4", "l5", "l6", "l7", \
  60. "i0", "i1", "i2", "i3", "i4", "i5", \
  61. "o0", "o1", "o2", "o3", "o4", "o5", "o7"); \
  62. } while(0)
  63. void synchronize_user_stack(void);
  64. struct pt_regs;
  65. void fault_in_user_windows(struct pt_regs *);
  66. #endif /* __SPARC64_SWITCH_TO_64_H */