ahci_mtk.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * MediaTek AHCI SATA driver
  4. *
  5. * Copyright (c) 2017 MediaTek Inc.
  6. * Author: Ryder Lee <ryder.lee@mediatek.com>
  7. */
  8. #include <linux/ahci_platform.h>
  9. #include <linux/kernel.h>
  10. #include <linux/libata.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm.h>
  16. #include <linux/regmap.h>
  17. #include <linux/reset.h>
  18. #include "ahci.h"
  19. #define DRV_NAME "ahci-mtk"
  20. #define SYS_CFG 0x14
  21. #define SYS_CFG_SATA_MSK GENMASK(31, 30)
  22. #define SYS_CFG_SATA_EN BIT(31)
  23. struct mtk_ahci_plat {
  24. struct regmap *mode;
  25. struct reset_control *axi_rst;
  26. struct reset_control *sw_rst;
  27. struct reset_control *reg_rst;
  28. };
  29. static const struct ata_port_info ahci_port_info = {
  30. .flags = AHCI_FLAG_COMMON,
  31. .pio_mask = ATA_PIO4,
  32. .udma_mask = ATA_UDMA6,
  33. .port_ops = &ahci_platform_ops,
  34. };
  35. static const struct scsi_host_template ahci_platform_sht = {
  36. AHCI_SHT(DRV_NAME),
  37. };
  38. static int mtk_ahci_platform_resets(struct ahci_host_priv *hpriv,
  39. struct device *dev)
  40. {
  41. struct mtk_ahci_plat *plat = hpriv->plat_data;
  42. int err;
  43. /* reset AXI bus and PHY part */
  44. plat->axi_rst = devm_reset_control_get_optional_exclusive(dev, "axi");
  45. if (PTR_ERR(plat->axi_rst) == -EPROBE_DEFER)
  46. return PTR_ERR(plat->axi_rst);
  47. plat->sw_rst = devm_reset_control_get_optional_exclusive(dev, "sw");
  48. if (PTR_ERR(plat->sw_rst) == -EPROBE_DEFER)
  49. return PTR_ERR(plat->sw_rst);
  50. plat->reg_rst = devm_reset_control_get_optional_exclusive(dev, "reg");
  51. if (PTR_ERR(plat->reg_rst) == -EPROBE_DEFER)
  52. return PTR_ERR(plat->reg_rst);
  53. err = reset_control_assert(plat->axi_rst);
  54. if (err) {
  55. dev_err(dev, "failed to assert AXI bus\n");
  56. return err;
  57. }
  58. err = reset_control_assert(plat->sw_rst);
  59. if (err) {
  60. dev_err(dev, "failed to assert PHY digital part\n");
  61. return err;
  62. }
  63. err = reset_control_assert(plat->reg_rst);
  64. if (err) {
  65. dev_err(dev, "failed to assert PHY register part\n");
  66. return err;
  67. }
  68. err = reset_control_deassert(plat->reg_rst);
  69. if (err) {
  70. dev_err(dev, "failed to deassert PHY register part\n");
  71. return err;
  72. }
  73. err = reset_control_deassert(plat->sw_rst);
  74. if (err) {
  75. dev_err(dev, "failed to deassert PHY digital part\n");
  76. return err;
  77. }
  78. err = reset_control_deassert(plat->axi_rst);
  79. if (err) {
  80. dev_err(dev, "failed to deassert AXI bus\n");
  81. return err;
  82. }
  83. return 0;
  84. }
  85. static int mtk_ahci_parse_property(struct ahci_host_priv *hpriv,
  86. struct device *dev)
  87. {
  88. struct mtk_ahci_plat *plat = hpriv->plat_data;
  89. struct device_node *np = dev->of_node;
  90. /* enable SATA function if needed */
  91. if (of_property_present(np, "mediatek,phy-mode")) {
  92. plat->mode = syscon_regmap_lookup_by_phandle(
  93. np, "mediatek,phy-mode");
  94. if (IS_ERR(plat->mode)) {
  95. dev_err(dev, "missing phy-mode phandle\n");
  96. return PTR_ERR(plat->mode);
  97. }
  98. regmap_update_bits(plat->mode, SYS_CFG, SYS_CFG_SATA_MSK,
  99. SYS_CFG_SATA_EN);
  100. }
  101. return 0;
  102. }
  103. static int mtk_ahci_probe(struct platform_device *pdev)
  104. {
  105. struct device *dev = &pdev->dev;
  106. struct mtk_ahci_plat *plat;
  107. struct ahci_host_priv *hpriv;
  108. int err;
  109. plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL);
  110. if (!plat)
  111. return -ENOMEM;
  112. hpriv = ahci_platform_get_resources(pdev, 0);
  113. if (IS_ERR(hpriv))
  114. return PTR_ERR(hpriv);
  115. hpriv->plat_data = plat;
  116. err = mtk_ahci_parse_property(hpriv, dev);
  117. if (err)
  118. return err;
  119. err = mtk_ahci_platform_resets(hpriv, dev);
  120. if (err)
  121. return err;
  122. err = ahci_platform_enable_resources(hpriv);
  123. if (err)
  124. return err;
  125. err = ahci_platform_init_host(pdev, hpriv, &ahci_port_info,
  126. &ahci_platform_sht);
  127. if (err)
  128. goto disable_resources;
  129. return 0;
  130. disable_resources:
  131. ahci_platform_disable_resources(hpriv);
  132. return err;
  133. }
  134. static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
  135. ahci_platform_resume);
  136. static const struct of_device_id ahci_of_match[] = {
  137. { .compatible = "mediatek,mtk-ahci", },
  138. { /* sentinel */ }
  139. };
  140. MODULE_DEVICE_TABLE(of, ahci_of_match);
  141. static struct platform_driver mtk_ahci_driver = {
  142. .probe = mtk_ahci_probe,
  143. .remove_new = ata_platform_remove_one,
  144. .driver = {
  145. .name = DRV_NAME,
  146. .of_match_table = ahci_of_match,
  147. .pm = &ahci_pm_ops,
  148. },
  149. };
  150. module_platform_driver(mtk_ahci_driver);
  151. MODULE_DESCRIPTION("MediaTek SATA AHCI Driver");
  152. MODULE_LICENSE("GPL v2");