hci_qca.c 68 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Bluetooth Software UART Qualcomm protocol
  4. *
  5. * HCI_IBS (HCI In-Band Sleep) is Qualcomm's power management
  6. * protocol extension to H4.
  7. *
  8. * Copyright (C) 2007 Texas Instruments, Inc.
  9. * Copyright (c) 2010, 2012, 2018 The Linux Foundation. All rights reserved.
  10. *
  11. * Acknowledgements:
  12. * This file is based on hci_ll.c, which was...
  13. * Written by Ohad Ben-Cohen <ohad@bencohen.org>
  14. * which was in turn based on hci_h4.c, which was written
  15. * by Maxim Krasnyansky and Marcel Holtmann.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/clk.h>
  19. #include <linux/completion.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/delay.h>
  22. #include <linux/devcoredump.h>
  23. #include <linux/device.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/mod_devicetable.h>
  26. #include <linux/module.h>
  27. #include <linux/of.h>
  28. #include <linux/acpi.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/pwrseq/consumer.h>
  31. #include <linux/regulator/consumer.h>
  32. #include <linux/serdev.h>
  33. #include <linux/mutex.h>
  34. #include <linux/unaligned.h>
  35. #include <net/bluetooth/bluetooth.h>
  36. #include <net/bluetooth/hci_core.h>
  37. #include "hci_uart.h"
  38. #include "btqca.h"
  39. /* HCI_IBS protocol messages */
  40. #define HCI_IBS_SLEEP_IND 0xFE
  41. #define HCI_IBS_WAKE_IND 0xFD
  42. #define HCI_IBS_WAKE_ACK 0xFC
  43. #define HCI_MAX_IBS_SIZE 10
  44. #define IBS_WAKE_RETRANS_TIMEOUT_MS 100
  45. #define IBS_BTSOC_TX_IDLE_TIMEOUT_MS 200
  46. #define IBS_HOST_TX_IDLE_TIMEOUT_MS 2000
  47. #define CMD_TRANS_TIMEOUT_MS 100
  48. #define MEMDUMP_TIMEOUT_MS 8000
  49. #define IBS_DISABLE_SSR_TIMEOUT_MS \
  50. (MEMDUMP_TIMEOUT_MS + FW_DOWNLOAD_TIMEOUT_MS)
  51. #define FW_DOWNLOAD_TIMEOUT_MS 3000
  52. /* susclk rate */
  53. #define SUSCLK_RATE_32KHZ 32768
  54. /* Controller debug log header */
  55. #define QCA_DEBUG_HANDLE 0x2EDC
  56. /* max retry count when init fails */
  57. #define MAX_INIT_RETRIES 3
  58. /* Controller dump header */
  59. #define QCA_SSR_DUMP_HANDLE 0x0108
  60. #define QCA_DUMP_PACKET_SIZE 255
  61. #define QCA_LAST_SEQUENCE_NUM 0xFFFF
  62. #define QCA_CRASHBYTE_PACKET_LEN 1096
  63. #define QCA_MEMDUMP_BYTE 0xFB
  64. enum qca_flags {
  65. QCA_IBS_DISABLED,
  66. QCA_DROP_VENDOR_EVENT,
  67. QCA_SUSPENDING,
  68. QCA_MEMDUMP_COLLECTION,
  69. QCA_HW_ERROR_EVENT,
  70. QCA_SSR_TRIGGERED,
  71. QCA_BT_OFF,
  72. QCA_ROM_FW,
  73. QCA_DEBUGFS_CREATED,
  74. };
  75. enum qca_capabilities {
  76. QCA_CAP_WIDEBAND_SPEECH = BIT(0),
  77. QCA_CAP_VALID_LE_STATES = BIT(1),
  78. };
  79. /* HCI_IBS transmit side sleep protocol states */
  80. enum tx_ibs_states {
  81. HCI_IBS_TX_ASLEEP,
  82. HCI_IBS_TX_WAKING,
  83. HCI_IBS_TX_AWAKE,
  84. };
  85. /* HCI_IBS receive side sleep protocol states */
  86. enum rx_states {
  87. HCI_IBS_RX_ASLEEP,
  88. HCI_IBS_RX_AWAKE,
  89. };
  90. /* HCI_IBS transmit and receive side clock state vote */
  91. enum hci_ibs_clock_state_vote {
  92. HCI_IBS_VOTE_STATS_UPDATE,
  93. HCI_IBS_TX_VOTE_CLOCK_ON,
  94. HCI_IBS_TX_VOTE_CLOCK_OFF,
  95. HCI_IBS_RX_VOTE_CLOCK_ON,
  96. HCI_IBS_RX_VOTE_CLOCK_OFF,
  97. };
  98. /* Controller memory dump states */
  99. enum qca_memdump_states {
  100. QCA_MEMDUMP_IDLE,
  101. QCA_MEMDUMP_COLLECTING,
  102. QCA_MEMDUMP_COLLECTED,
  103. QCA_MEMDUMP_TIMEOUT,
  104. };
  105. struct qca_memdump_info {
  106. u32 current_seq_no;
  107. u32 received_dump;
  108. u32 ram_dump_size;
  109. };
  110. struct qca_memdump_event_hdr {
  111. __u8 evt;
  112. __u8 plen;
  113. __u16 opcode;
  114. __le16 seq_no;
  115. __u8 reserved;
  116. } __packed;
  117. struct qca_dump_size {
  118. __le32 dump_size;
  119. } __packed;
  120. struct qca_data {
  121. struct hci_uart *hu;
  122. struct sk_buff *rx_skb;
  123. struct sk_buff_head txq;
  124. struct sk_buff_head tx_wait_q; /* HCI_IBS wait queue */
  125. struct sk_buff_head rx_memdump_q; /* Memdump wait queue */
  126. spinlock_t hci_ibs_lock; /* HCI_IBS state lock */
  127. u8 tx_ibs_state; /* HCI_IBS transmit side power state*/
  128. u8 rx_ibs_state; /* HCI_IBS receive side power state */
  129. bool tx_vote; /* Clock must be on for TX */
  130. bool rx_vote; /* Clock must be on for RX */
  131. struct timer_list tx_idle_timer;
  132. u32 tx_idle_delay;
  133. struct timer_list wake_retrans_timer;
  134. u32 wake_retrans;
  135. struct workqueue_struct *workqueue;
  136. struct work_struct ws_awake_rx;
  137. struct work_struct ws_awake_device;
  138. struct work_struct ws_rx_vote_off;
  139. struct work_struct ws_tx_vote_off;
  140. struct work_struct ctrl_memdump_evt;
  141. struct delayed_work ctrl_memdump_timeout;
  142. struct qca_memdump_info *qca_memdump;
  143. unsigned long flags;
  144. struct completion drop_ev_comp;
  145. wait_queue_head_t suspend_wait_q;
  146. enum qca_memdump_states memdump_state;
  147. struct mutex hci_memdump_lock;
  148. u16 fw_version;
  149. u16 controller_id;
  150. /* For debugging purpose */
  151. u64 ibs_sent_wacks;
  152. u64 ibs_sent_slps;
  153. u64 ibs_sent_wakes;
  154. u64 ibs_recv_wacks;
  155. u64 ibs_recv_slps;
  156. u64 ibs_recv_wakes;
  157. u64 vote_last_jif;
  158. u32 vote_on_ms;
  159. u32 vote_off_ms;
  160. u64 tx_votes_on;
  161. u64 rx_votes_on;
  162. u64 tx_votes_off;
  163. u64 rx_votes_off;
  164. u64 votes_on;
  165. u64 votes_off;
  166. };
  167. enum qca_speed_type {
  168. QCA_INIT_SPEED = 1,
  169. QCA_OPER_SPEED
  170. };
  171. /*
  172. * Voltage regulator information required for configuring the
  173. * QCA Bluetooth chipset
  174. */
  175. struct qca_vreg {
  176. const char *name;
  177. unsigned int load_uA;
  178. };
  179. struct qca_device_data {
  180. enum qca_btsoc_type soc_type;
  181. struct qca_vreg *vregs;
  182. size_t num_vregs;
  183. uint32_t capabilities;
  184. };
  185. /*
  186. * Platform data for the QCA Bluetooth power driver.
  187. */
  188. struct qca_power {
  189. struct device *dev;
  190. struct regulator_bulk_data *vreg_bulk;
  191. int num_vregs;
  192. bool vregs_on;
  193. struct pwrseq_desc *pwrseq;
  194. };
  195. struct qca_serdev {
  196. struct hci_uart serdev_hu;
  197. struct gpio_desc *bt_en;
  198. struct gpio_desc *sw_ctrl;
  199. struct clk *susclk;
  200. enum qca_btsoc_type btsoc_type;
  201. struct qca_power *bt_power;
  202. u32 init_speed;
  203. u32 oper_speed;
  204. bool bdaddr_property_broken;
  205. const char *firmware_name;
  206. };
  207. static int qca_regulator_enable(struct qca_serdev *qcadev);
  208. static void qca_regulator_disable(struct qca_serdev *qcadev);
  209. static void qca_power_shutdown(struct hci_uart *hu);
  210. static int qca_power_off(struct hci_dev *hdev);
  211. static void qca_controller_memdump(struct work_struct *work);
  212. static void qca_dmp_hdr(struct hci_dev *hdev, struct sk_buff *skb);
  213. static enum qca_btsoc_type qca_soc_type(struct hci_uart *hu)
  214. {
  215. enum qca_btsoc_type soc_type;
  216. if (hu->serdev) {
  217. struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev);
  218. soc_type = qsd->btsoc_type;
  219. } else {
  220. soc_type = QCA_ROME;
  221. }
  222. return soc_type;
  223. }
  224. static const char *qca_get_firmware_name(struct hci_uart *hu)
  225. {
  226. if (hu->serdev) {
  227. struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev);
  228. return qsd->firmware_name;
  229. } else {
  230. return NULL;
  231. }
  232. }
  233. static void __serial_clock_on(struct tty_struct *tty)
  234. {
  235. /* TODO: Some chipset requires to enable UART clock on client
  236. * side to save power consumption or manual work is required.
  237. * Please put your code to control UART clock here if needed
  238. */
  239. }
  240. static void __serial_clock_off(struct tty_struct *tty)
  241. {
  242. /* TODO: Some chipset requires to disable UART clock on client
  243. * side to save power consumption or manual work is required.
  244. * Please put your code to control UART clock off here if needed
  245. */
  246. }
  247. /* serial_clock_vote needs to be called with the ibs lock held */
  248. static void serial_clock_vote(unsigned long vote, struct hci_uart *hu)
  249. {
  250. struct qca_data *qca = hu->priv;
  251. unsigned int diff;
  252. bool old_vote = (qca->tx_vote | qca->rx_vote);
  253. bool new_vote;
  254. switch (vote) {
  255. case HCI_IBS_VOTE_STATS_UPDATE:
  256. diff = jiffies_to_msecs(jiffies - qca->vote_last_jif);
  257. if (old_vote)
  258. qca->vote_off_ms += diff;
  259. else
  260. qca->vote_on_ms += diff;
  261. return;
  262. case HCI_IBS_TX_VOTE_CLOCK_ON:
  263. qca->tx_vote = true;
  264. qca->tx_votes_on++;
  265. break;
  266. case HCI_IBS_RX_VOTE_CLOCK_ON:
  267. qca->rx_vote = true;
  268. qca->rx_votes_on++;
  269. break;
  270. case HCI_IBS_TX_VOTE_CLOCK_OFF:
  271. qca->tx_vote = false;
  272. qca->tx_votes_off++;
  273. break;
  274. case HCI_IBS_RX_VOTE_CLOCK_OFF:
  275. qca->rx_vote = false;
  276. qca->rx_votes_off++;
  277. break;
  278. default:
  279. BT_ERR("Voting irregularity");
  280. return;
  281. }
  282. new_vote = qca->rx_vote | qca->tx_vote;
  283. if (new_vote != old_vote) {
  284. if (new_vote)
  285. __serial_clock_on(hu->tty);
  286. else
  287. __serial_clock_off(hu->tty);
  288. BT_DBG("Vote serial clock %s(%s)", new_vote ? "true" : "false",
  289. vote ? "true" : "false");
  290. diff = jiffies_to_msecs(jiffies - qca->vote_last_jif);
  291. if (new_vote) {
  292. qca->votes_on++;
  293. qca->vote_off_ms += diff;
  294. } else {
  295. qca->votes_off++;
  296. qca->vote_on_ms += diff;
  297. }
  298. qca->vote_last_jif = jiffies;
  299. }
  300. }
  301. /* Builds and sends an HCI_IBS command packet.
  302. * These are very simple packets with only 1 cmd byte.
  303. */
  304. static int send_hci_ibs_cmd(u8 cmd, struct hci_uart *hu)
  305. {
  306. int err = 0;
  307. struct sk_buff *skb = NULL;
  308. struct qca_data *qca = hu->priv;
  309. BT_DBG("hu %p send hci ibs cmd 0x%x", hu, cmd);
  310. skb = bt_skb_alloc(1, GFP_ATOMIC);
  311. if (!skb) {
  312. BT_ERR("Failed to allocate memory for HCI_IBS packet");
  313. return -ENOMEM;
  314. }
  315. /* Assign HCI_IBS type */
  316. skb_put_u8(skb, cmd);
  317. skb_queue_tail(&qca->txq, skb);
  318. return err;
  319. }
  320. static void qca_wq_awake_device(struct work_struct *work)
  321. {
  322. struct qca_data *qca = container_of(work, struct qca_data,
  323. ws_awake_device);
  324. struct hci_uart *hu = qca->hu;
  325. unsigned long retrans_delay;
  326. unsigned long flags;
  327. BT_DBG("hu %p wq awake device", hu);
  328. /* Vote for serial clock */
  329. serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_ON, hu);
  330. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  331. /* Send wake indication to device */
  332. if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0)
  333. BT_ERR("Failed to send WAKE to device");
  334. qca->ibs_sent_wakes++;
  335. /* Start retransmit timer */
  336. retrans_delay = msecs_to_jiffies(qca->wake_retrans);
  337. mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay);
  338. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  339. /* Actually send the packets */
  340. hci_uart_tx_wakeup(hu);
  341. }
  342. static void qca_wq_awake_rx(struct work_struct *work)
  343. {
  344. struct qca_data *qca = container_of(work, struct qca_data,
  345. ws_awake_rx);
  346. struct hci_uart *hu = qca->hu;
  347. unsigned long flags;
  348. BT_DBG("hu %p wq awake rx", hu);
  349. serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_ON, hu);
  350. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  351. qca->rx_ibs_state = HCI_IBS_RX_AWAKE;
  352. /* Always acknowledge device wake up,
  353. * sending IBS message doesn't count as TX ON.
  354. */
  355. if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0)
  356. BT_ERR("Failed to acknowledge device wake up");
  357. qca->ibs_sent_wacks++;
  358. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  359. /* Actually send the packets */
  360. hci_uart_tx_wakeup(hu);
  361. }
  362. static void qca_wq_serial_rx_clock_vote_off(struct work_struct *work)
  363. {
  364. struct qca_data *qca = container_of(work, struct qca_data,
  365. ws_rx_vote_off);
  366. struct hci_uart *hu = qca->hu;
  367. BT_DBG("hu %p rx clock vote off", hu);
  368. serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_OFF, hu);
  369. }
  370. static void qca_wq_serial_tx_clock_vote_off(struct work_struct *work)
  371. {
  372. struct qca_data *qca = container_of(work, struct qca_data,
  373. ws_tx_vote_off);
  374. struct hci_uart *hu = qca->hu;
  375. BT_DBG("hu %p tx clock vote off", hu);
  376. /* Run HCI tx handling unlocked */
  377. hci_uart_tx_wakeup(hu);
  378. /* Now that message queued to tty driver, vote for tty clocks off.
  379. * It is up to the tty driver to pend the clocks off until tx done.
  380. */
  381. serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu);
  382. }
  383. static void hci_ibs_tx_idle_timeout(struct timer_list *t)
  384. {
  385. struct qca_data *qca = from_timer(qca, t, tx_idle_timer);
  386. struct hci_uart *hu = qca->hu;
  387. unsigned long flags;
  388. BT_DBG("hu %p idle timeout in %d state", hu, qca->tx_ibs_state);
  389. spin_lock_irqsave_nested(&qca->hci_ibs_lock,
  390. flags, SINGLE_DEPTH_NESTING);
  391. switch (qca->tx_ibs_state) {
  392. case HCI_IBS_TX_AWAKE:
  393. /* TX_IDLE, go to SLEEP */
  394. if (send_hci_ibs_cmd(HCI_IBS_SLEEP_IND, hu) < 0) {
  395. BT_ERR("Failed to send SLEEP to device");
  396. break;
  397. }
  398. qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
  399. qca->ibs_sent_slps++;
  400. queue_work(qca->workqueue, &qca->ws_tx_vote_off);
  401. break;
  402. case HCI_IBS_TX_ASLEEP:
  403. case HCI_IBS_TX_WAKING:
  404. default:
  405. BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state);
  406. break;
  407. }
  408. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  409. }
  410. static void hci_ibs_wake_retrans_timeout(struct timer_list *t)
  411. {
  412. struct qca_data *qca = from_timer(qca, t, wake_retrans_timer);
  413. struct hci_uart *hu = qca->hu;
  414. unsigned long flags, retrans_delay;
  415. bool retransmit = false;
  416. BT_DBG("hu %p wake retransmit timeout in %d state",
  417. hu, qca->tx_ibs_state);
  418. spin_lock_irqsave_nested(&qca->hci_ibs_lock,
  419. flags, SINGLE_DEPTH_NESTING);
  420. /* Don't retransmit the HCI_IBS_WAKE_IND when suspending. */
  421. if (test_bit(QCA_SUSPENDING, &qca->flags)) {
  422. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  423. return;
  424. }
  425. switch (qca->tx_ibs_state) {
  426. case HCI_IBS_TX_WAKING:
  427. /* No WAKE_ACK, retransmit WAKE */
  428. retransmit = true;
  429. if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0) {
  430. BT_ERR("Failed to acknowledge device wake up");
  431. break;
  432. }
  433. qca->ibs_sent_wakes++;
  434. retrans_delay = msecs_to_jiffies(qca->wake_retrans);
  435. mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay);
  436. break;
  437. case HCI_IBS_TX_ASLEEP:
  438. case HCI_IBS_TX_AWAKE:
  439. default:
  440. BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state);
  441. break;
  442. }
  443. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  444. if (retransmit)
  445. hci_uart_tx_wakeup(hu);
  446. }
  447. static void qca_controller_memdump_timeout(struct work_struct *work)
  448. {
  449. struct qca_data *qca = container_of(work, struct qca_data,
  450. ctrl_memdump_timeout.work);
  451. struct hci_uart *hu = qca->hu;
  452. mutex_lock(&qca->hci_memdump_lock);
  453. if (test_bit(QCA_MEMDUMP_COLLECTION, &qca->flags)) {
  454. qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
  455. if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) {
  456. /* Inject hw error event to reset the device
  457. * and driver.
  458. */
  459. hci_reset_dev(hu->hdev);
  460. }
  461. }
  462. mutex_unlock(&qca->hci_memdump_lock);
  463. }
  464. /* Initialize protocol */
  465. static int qca_open(struct hci_uart *hu)
  466. {
  467. struct qca_serdev *qcadev;
  468. struct qca_data *qca;
  469. BT_DBG("hu %p qca_open", hu);
  470. if (!hci_uart_has_flow_control(hu))
  471. return -EOPNOTSUPP;
  472. qca = kzalloc(sizeof(*qca), GFP_KERNEL);
  473. if (!qca)
  474. return -ENOMEM;
  475. skb_queue_head_init(&qca->txq);
  476. skb_queue_head_init(&qca->tx_wait_q);
  477. skb_queue_head_init(&qca->rx_memdump_q);
  478. spin_lock_init(&qca->hci_ibs_lock);
  479. mutex_init(&qca->hci_memdump_lock);
  480. qca->workqueue = alloc_ordered_workqueue("qca_wq", 0);
  481. if (!qca->workqueue) {
  482. BT_ERR("QCA Workqueue not initialized properly");
  483. kfree(qca);
  484. return -ENOMEM;
  485. }
  486. INIT_WORK(&qca->ws_awake_rx, qca_wq_awake_rx);
  487. INIT_WORK(&qca->ws_awake_device, qca_wq_awake_device);
  488. INIT_WORK(&qca->ws_rx_vote_off, qca_wq_serial_rx_clock_vote_off);
  489. INIT_WORK(&qca->ws_tx_vote_off, qca_wq_serial_tx_clock_vote_off);
  490. INIT_WORK(&qca->ctrl_memdump_evt, qca_controller_memdump);
  491. INIT_DELAYED_WORK(&qca->ctrl_memdump_timeout,
  492. qca_controller_memdump_timeout);
  493. init_waitqueue_head(&qca->suspend_wait_q);
  494. qca->hu = hu;
  495. init_completion(&qca->drop_ev_comp);
  496. /* Assume we start with both sides asleep -- extra wakes OK */
  497. qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
  498. qca->rx_ibs_state = HCI_IBS_RX_ASLEEP;
  499. qca->vote_last_jif = jiffies;
  500. hu->priv = qca;
  501. if (hu->serdev) {
  502. qcadev = serdev_device_get_drvdata(hu->serdev);
  503. switch (qcadev->btsoc_type) {
  504. case QCA_WCN3988:
  505. case QCA_WCN3990:
  506. case QCA_WCN3991:
  507. case QCA_WCN3998:
  508. case QCA_WCN6750:
  509. hu->init_speed = qcadev->init_speed;
  510. break;
  511. default:
  512. break;
  513. }
  514. if (qcadev->oper_speed)
  515. hu->oper_speed = qcadev->oper_speed;
  516. }
  517. timer_setup(&qca->wake_retrans_timer, hci_ibs_wake_retrans_timeout, 0);
  518. qca->wake_retrans = IBS_WAKE_RETRANS_TIMEOUT_MS;
  519. timer_setup(&qca->tx_idle_timer, hci_ibs_tx_idle_timeout, 0);
  520. qca->tx_idle_delay = IBS_HOST_TX_IDLE_TIMEOUT_MS;
  521. BT_DBG("HCI_UART_QCA open, tx_idle_delay=%u, wake_retrans=%u",
  522. qca->tx_idle_delay, qca->wake_retrans);
  523. return 0;
  524. }
  525. static void qca_debugfs_init(struct hci_dev *hdev)
  526. {
  527. struct hci_uart *hu = hci_get_drvdata(hdev);
  528. struct qca_data *qca = hu->priv;
  529. struct dentry *ibs_dir;
  530. umode_t mode;
  531. if (!hdev->debugfs)
  532. return;
  533. if (test_and_set_bit(QCA_DEBUGFS_CREATED, &qca->flags))
  534. return;
  535. ibs_dir = debugfs_create_dir("ibs", hdev->debugfs);
  536. /* read only */
  537. mode = 0444;
  538. debugfs_create_u8("tx_ibs_state", mode, ibs_dir, &qca->tx_ibs_state);
  539. debugfs_create_u8("rx_ibs_state", mode, ibs_dir, &qca->rx_ibs_state);
  540. debugfs_create_u64("ibs_sent_sleeps", mode, ibs_dir,
  541. &qca->ibs_sent_slps);
  542. debugfs_create_u64("ibs_sent_wakes", mode, ibs_dir,
  543. &qca->ibs_sent_wakes);
  544. debugfs_create_u64("ibs_sent_wake_acks", mode, ibs_dir,
  545. &qca->ibs_sent_wacks);
  546. debugfs_create_u64("ibs_recv_sleeps", mode, ibs_dir,
  547. &qca->ibs_recv_slps);
  548. debugfs_create_u64("ibs_recv_wakes", mode, ibs_dir,
  549. &qca->ibs_recv_wakes);
  550. debugfs_create_u64("ibs_recv_wake_acks", mode, ibs_dir,
  551. &qca->ibs_recv_wacks);
  552. debugfs_create_bool("tx_vote", mode, ibs_dir, &qca->tx_vote);
  553. debugfs_create_u64("tx_votes_on", mode, ibs_dir, &qca->tx_votes_on);
  554. debugfs_create_u64("tx_votes_off", mode, ibs_dir, &qca->tx_votes_off);
  555. debugfs_create_bool("rx_vote", mode, ibs_dir, &qca->rx_vote);
  556. debugfs_create_u64("rx_votes_on", mode, ibs_dir, &qca->rx_votes_on);
  557. debugfs_create_u64("rx_votes_off", mode, ibs_dir, &qca->rx_votes_off);
  558. debugfs_create_u64("votes_on", mode, ibs_dir, &qca->votes_on);
  559. debugfs_create_u64("votes_off", mode, ibs_dir, &qca->votes_off);
  560. debugfs_create_u32("vote_on_ms", mode, ibs_dir, &qca->vote_on_ms);
  561. debugfs_create_u32("vote_off_ms", mode, ibs_dir, &qca->vote_off_ms);
  562. /* read/write */
  563. mode = 0644;
  564. debugfs_create_u32("wake_retrans", mode, ibs_dir, &qca->wake_retrans);
  565. debugfs_create_u32("tx_idle_delay", mode, ibs_dir,
  566. &qca->tx_idle_delay);
  567. }
  568. /* Flush protocol data */
  569. static int qca_flush(struct hci_uart *hu)
  570. {
  571. struct qca_data *qca = hu->priv;
  572. BT_DBG("hu %p qca flush", hu);
  573. skb_queue_purge(&qca->tx_wait_q);
  574. skb_queue_purge(&qca->txq);
  575. return 0;
  576. }
  577. /* Close protocol */
  578. static int qca_close(struct hci_uart *hu)
  579. {
  580. struct qca_data *qca = hu->priv;
  581. BT_DBG("hu %p qca close", hu);
  582. serial_clock_vote(HCI_IBS_VOTE_STATS_UPDATE, hu);
  583. skb_queue_purge(&qca->tx_wait_q);
  584. skb_queue_purge(&qca->txq);
  585. skb_queue_purge(&qca->rx_memdump_q);
  586. /*
  587. * Shut the timers down so they can't be rearmed when
  588. * destroy_workqueue() drains pending work which in turn might try
  589. * to arm a timer. After shutdown rearm attempts are silently
  590. * ignored by the timer core code.
  591. */
  592. timer_shutdown_sync(&qca->tx_idle_timer);
  593. timer_shutdown_sync(&qca->wake_retrans_timer);
  594. destroy_workqueue(qca->workqueue);
  595. qca->hu = NULL;
  596. kfree_skb(qca->rx_skb);
  597. hu->priv = NULL;
  598. kfree(qca);
  599. return 0;
  600. }
  601. /* Called upon a wake-up-indication from the device.
  602. */
  603. static void device_want_to_wakeup(struct hci_uart *hu)
  604. {
  605. unsigned long flags;
  606. struct qca_data *qca = hu->priv;
  607. BT_DBG("hu %p want to wake up", hu);
  608. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  609. qca->ibs_recv_wakes++;
  610. /* Don't wake the rx up when suspending. */
  611. if (test_bit(QCA_SUSPENDING, &qca->flags)) {
  612. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  613. return;
  614. }
  615. switch (qca->rx_ibs_state) {
  616. case HCI_IBS_RX_ASLEEP:
  617. /* Make sure clock is on - we may have turned clock off since
  618. * receiving the wake up indicator awake rx clock.
  619. */
  620. queue_work(qca->workqueue, &qca->ws_awake_rx);
  621. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  622. return;
  623. case HCI_IBS_RX_AWAKE:
  624. /* Always acknowledge device wake up,
  625. * sending IBS message doesn't count as TX ON.
  626. */
  627. if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0) {
  628. BT_ERR("Failed to acknowledge device wake up");
  629. break;
  630. }
  631. qca->ibs_sent_wacks++;
  632. break;
  633. default:
  634. /* Any other state is illegal */
  635. BT_ERR("Received HCI_IBS_WAKE_IND in rx state %d",
  636. qca->rx_ibs_state);
  637. break;
  638. }
  639. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  640. /* Actually send the packets */
  641. hci_uart_tx_wakeup(hu);
  642. }
  643. /* Called upon a sleep-indication from the device.
  644. */
  645. static void device_want_to_sleep(struct hci_uart *hu)
  646. {
  647. unsigned long flags;
  648. struct qca_data *qca = hu->priv;
  649. BT_DBG("hu %p want to sleep in %d state", hu, qca->rx_ibs_state);
  650. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  651. qca->ibs_recv_slps++;
  652. switch (qca->rx_ibs_state) {
  653. case HCI_IBS_RX_AWAKE:
  654. /* Update state */
  655. qca->rx_ibs_state = HCI_IBS_RX_ASLEEP;
  656. /* Vote off rx clock under workqueue */
  657. queue_work(qca->workqueue, &qca->ws_rx_vote_off);
  658. break;
  659. case HCI_IBS_RX_ASLEEP:
  660. break;
  661. default:
  662. /* Any other state is illegal */
  663. BT_ERR("Received HCI_IBS_SLEEP_IND in rx state %d",
  664. qca->rx_ibs_state);
  665. break;
  666. }
  667. wake_up_interruptible(&qca->suspend_wait_q);
  668. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  669. }
  670. /* Called upon wake-up-acknowledgement from the device
  671. */
  672. static void device_woke_up(struct hci_uart *hu)
  673. {
  674. unsigned long flags, idle_delay;
  675. struct qca_data *qca = hu->priv;
  676. struct sk_buff *skb = NULL;
  677. BT_DBG("hu %p woke up", hu);
  678. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  679. qca->ibs_recv_wacks++;
  680. /* Don't react to the wake-up-acknowledgment when suspending. */
  681. if (test_bit(QCA_SUSPENDING, &qca->flags)) {
  682. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  683. return;
  684. }
  685. switch (qca->tx_ibs_state) {
  686. case HCI_IBS_TX_AWAKE:
  687. /* Expect one if we send 2 WAKEs */
  688. BT_DBG("Received HCI_IBS_WAKE_ACK in tx state %d",
  689. qca->tx_ibs_state);
  690. break;
  691. case HCI_IBS_TX_WAKING:
  692. /* Send pending packets */
  693. while ((skb = skb_dequeue(&qca->tx_wait_q)))
  694. skb_queue_tail(&qca->txq, skb);
  695. /* Switch timers and change state to HCI_IBS_TX_AWAKE */
  696. del_timer(&qca->wake_retrans_timer);
  697. idle_delay = msecs_to_jiffies(qca->tx_idle_delay);
  698. mod_timer(&qca->tx_idle_timer, jiffies + idle_delay);
  699. qca->tx_ibs_state = HCI_IBS_TX_AWAKE;
  700. break;
  701. case HCI_IBS_TX_ASLEEP:
  702. default:
  703. BT_ERR("Received HCI_IBS_WAKE_ACK in tx state %d",
  704. qca->tx_ibs_state);
  705. break;
  706. }
  707. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  708. /* Actually send the packets */
  709. hci_uart_tx_wakeup(hu);
  710. }
  711. /* Enqueue frame for transmittion (padding, crc, etc) may be called from
  712. * two simultaneous tasklets.
  713. */
  714. static int qca_enqueue(struct hci_uart *hu, struct sk_buff *skb)
  715. {
  716. unsigned long flags = 0, idle_delay;
  717. struct qca_data *qca = hu->priv;
  718. BT_DBG("hu %p qca enq skb %p tx_ibs_state %d", hu, skb,
  719. qca->tx_ibs_state);
  720. if (test_bit(QCA_SSR_TRIGGERED, &qca->flags)) {
  721. /* As SSR is in progress, ignore the packets */
  722. bt_dev_dbg(hu->hdev, "SSR is in progress");
  723. kfree_skb(skb);
  724. return 0;
  725. }
  726. /* Prepend skb with frame type */
  727. memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1);
  728. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  729. /* Don't go to sleep in middle of patch download or
  730. * Out-Of-Band(GPIOs control) sleep is selected.
  731. * Don't wake the device up when suspending.
  732. */
  733. if (test_bit(QCA_IBS_DISABLED, &qca->flags) ||
  734. test_bit(QCA_SUSPENDING, &qca->flags)) {
  735. skb_queue_tail(&qca->txq, skb);
  736. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  737. return 0;
  738. }
  739. /* Act according to current state */
  740. switch (qca->tx_ibs_state) {
  741. case HCI_IBS_TX_AWAKE:
  742. BT_DBG("Device awake, sending normally");
  743. skb_queue_tail(&qca->txq, skb);
  744. idle_delay = msecs_to_jiffies(qca->tx_idle_delay);
  745. mod_timer(&qca->tx_idle_timer, jiffies + idle_delay);
  746. break;
  747. case HCI_IBS_TX_ASLEEP:
  748. BT_DBG("Device asleep, waking up and queueing packet");
  749. /* Save packet for later */
  750. skb_queue_tail(&qca->tx_wait_q, skb);
  751. qca->tx_ibs_state = HCI_IBS_TX_WAKING;
  752. /* Schedule a work queue to wake up device */
  753. queue_work(qca->workqueue, &qca->ws_awake_device);
  754. break;
  755. case HCI_IBS_TX_WAKING:
  756. BT_DBG("Device waking up, queueing packet");
  757. /* Transient state; just keep packet for later */
  758. skb_queue_tail(&qca->tx_wait_q, skb);
  759. break;
  760. default:
  761. BT_ERR("Illegal tx state: %d (losing packet)",
  762. qca->tx_ibs_state);
  763. dev_kfree_skb_irq(skb);
  764. break;
  765. }
  766. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  767. return 0;
  768. }
  769. static int qca_ibs_sleep_ind(struct hci_dev *hdev, struct sk_buff *skb)
  770. {
  771. struct hci_uart *hu = hci_get_drvdata(hdev);
  772. BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_SLEEP_IND);
  773. device_want_to_sleep(hu);
  774. kfree_skb(skb);
  775. return 0;
  776. }
  777. static int qca_ibs_wake_ind(struct hci_dev *hdev, struct sk_buff *skb)
  778. {
  779. struct hci_uart *hu = hci_get_drvdata(hdev);
  780. BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_IND);
  781. device_want_to_wakeup(hu);
  782. kfree_skb(skb);
  783. return 0;
  784. }
  785. static int qca_ibs_wake_ack(struct hci_dev *hdev, struct sk_buff *skb)
  786. {
  787. struct hci_uart *hu = hci_get_drvdata(hdev);
  788. BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_ACK);
  789. device_woke_up(hu);
  790. kfree_skb(skb);
  791. return 0;
  792. }
  793. static int qca_recv_acl_data(struct hci_dev *hdev, struct sk_buff *skb)
  794. {
  795. /* We receive debug logs from chip as an ACL packets.
  796. * Instead of sending the data to ACL to decode the
  797. * received data, we are pushing them to the above layers
  798. * as a diagnostic packet.
  799. */
  800. if (get_unaligned_le16(skb->data) == QCA_DEBUG_HANDLE)
  801. return hci_recv_diag(hdev, skb);
  802. return hci_recv_frame(hdev, skb);
  803. }
  804. static void qca_dmp_hdr(struct hci_dev *hdev, struct sk_buff *skb)
  805. {
  806. struct hci_uart *hu = hci_get_drvdata(hdev);
  807. struct qca_data *qca = hu->priv;
  808. char buf[80];
  809. snprintf(buf, sizeof(buf), "Controller Name: 0x%x\n",
  810. qca->controller_id);
  811. skb_put_data(skb, buf, strlen(buf));
  812. snprintf(buf, sizeof(buf), "Firmware Version: 0x%x\n",
  813. qca->fw_version);
  814. skb_put_data(skb, buf, strlen(buf));
  815. snprintf(buf, sizeof(buf), "Vendor:Qualcomm\n");
  816. skb_put_data(skb, buf, strlen(buf));
  817. snprintf(buf, sizeof(buf), "Driver: %s\n",
  818. hu->serdev->dev.driver->name);
  819. skb_put_data(skb, buf, strlen(buf));
  820. }
  821. static void qca_controller_memdump(struct work_struct *work)
  822. {
  823. struct qca_data *qca = container_of(work, struct qca_data,
  824. ctrl_memdump_evt);
  825. struct hci_uart *hu = qca->hu;
  826. struct sk_buff *skb;
  827. struct qca_memdump_event_hdr *cmd_hdr;
  828. struct qca_memdump_info *qca_memdump = qca->qca_memdump;
  829. struct qca_dump_size *dump;
  830. u16 seq_no;
  831. u32 rx_size;
  832. int ret = 0;
  833. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  834. while ((skb = skb_dequeue(&qca->rx_memdump_q))) {
  835. mutex_lock(&qca->hci_memdump_lock);
  836. /* Skip processing the received packets if timeout detected
  837. * or memdump collection completed.
  838. */
  839. if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT ||
  840. qca->memdump_state == QCA_MEMDUMP_COLLECTED) {
  841. mutex_unlock(&qca->hci_memdump_lock);
  842. return;
  843. }
  844. if (!qca_memdump) {
  845. qca_memdump = kzalloc(sizeof(*qca_memdump), GFP_ATOMIC);
  846. if (!qca_memdump) {
  847. mutex_unlock(&qca->hci_memdump_lock);
  848. return;
  849. }
  850. qca->qca_memdump = qca_memdump;
  851. }
  852. qca->memdump_state = QCA_MEMDUMP_COLLECTING;
  853. cmd_hdr = (void *) skb->data;
  854. seq_no = __le16_to_cpu(cmd_hdr->seq_no);
  855. skb_pull(skb, sizeof(struct qca_memdump_event_hdr));
  856. if (!seq_no) {
  857. /* This is the first frame of memdump packet from
  858. * the controller, Disable IBS to recevie dump
  859. * with out any interruption, ideally time required for
  860. * the controller to send the dump is 8 seconds. let us
  861. * start timer to handle this asynchronous activity.
  862. */
  863. set_bit(QCA_IBS_DISABLED, &qca->flags);
  864. set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  865. dump = (void *) skb->data;
  866. qca_memdump->ram_dump_size = __le32_to_cpu(dump->dump_size);
  867. if (!(qca_memdump->ram_dump_size)) {
  868. bt_dev_err(hu->hdev, "Rx invalid memdump size");
  869. kfree(qca_memdump);
  870. kfree_skb(skb);
  871. mutex_unlock(&qca->hci_memdump_lock);
  872. return;
  873. }
  874. queue_delayed_work(qca->workqueue,
  875. &qca->ctrl_memdump_timeout,
  876. msecs_to_jiffies(MEMDUMP_TIMEOUT_MS));
  877. skb_pull(skb, sizeof(qca_memdump->ram_dump_size));
  878. qca_memdump->current_seq_no = 0;
  879. qca_memdump->received_dump = 0;
  880. ret = hci_devcd_init(hu->hdev, qca_memdump->ram_dump_size);
  881. bt_dev_info(hu->hdev, "hci_devcd_init Return:%d",
  882. ret);
  883. if (ret < 0) {
  884. kfree(qca->qca_memdump);
  885. qca->qca_memdump = NULL;
  886. qca->memdump_state = QCA_MEMDUMP_COLLECTED;
  887. cancel_delayed_work(&qca->ctrl_memdump_timeout);
  888. clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  889. clear_bit(QCA_IBS_DISABLED, &qca->flags);
  890. mutex_unlock(&qca->hci_memdump_lock);
  891. return;
  892. }
  893. bt_dev_info(hu->hdev, "QCA collecting dump of size:%u",
  894. qca_memdump->ram_dump_size);
  895. }
  896. /* If sequence no 0 is missed then there is no point in
  897. * accepting the other sequences.
  898. */
  899. if (!test_bit(QCA_MEMDUMP_COLLECTION, &qca->flags)) {
  900. bt_dev_err(hu->hdev, "QCA: Discarding other packets");
  901. kfree(qca_memdump);
  902. kfree_skb(skb);
  903. mutex_unlock(&qca->hci_memdump_lock);
  904. return;
  905. }
  906. /* There could be chance of missing some packets from
  907. * the controller. In such cases let us store the dummy
  908. * packets in the buffer.
  909. */
  910. /* For QCA6390, controller does not lost packets but
  911. * sequence number field of packet sometimes has error
  912. * bits, so skip this checking for missing packet.
  913. */
  914. while ((seq_no > qca_memdump->current_seq_no + 1) &&
  915. (soc_type != QCA_QCA6390) &&
  916. seq_no != QCA_LAST_SEQUENCE_NUM) {
  917. bt_dev_err(hu->hdev, "QCA controller missed packet:%d",
  918. qca_memdump->current_seq_no);
  919. rx_size = qca_memdump->received_dump;
  920. rx_size += QCA_DUMP_PACKET_SIZE;
  921. if (rx_size > qca_memdump->ram_dump_size) {
  922. bt_dev_err(hu->hdev,
  923. "QCA memdump received %d, no space for missed packet",
  924. qca_memdump->received_dump);
  925. break;
  926. }
  927. hci_devcd_append_pattern(hu->hdev, 0x00,
  928. QCA_DUMP_PACKET_SIZE);
  929. qca_memdump->received_dump += QCA_DUMP_PACKET_SIZE;
  930. qca_memdump->current_seq_no++;
  931. }
  932. rx_size = qca_memdump->received_dump + skb->len;
  933. if (rx_size <= qca_memdump->ram_dump_size) {
  934. if ((seq_no != QCA_LAST_SEQUENCE_NUM) &&
  935. (seq_no != qca_memdump->current_seq_no)) {
  936. bt_dev_err(hu->hdev,
  937. "QCA memdump unexpected packet %d",
  938. seq_no);
  939. }
  940. bt_dev_dbg(hu->hdev,
  941. "QCA memdump packet %d with length %d",
  942. seq_no, skb->len);
  943. hci_devcd_append(hu->hdev, skb);
  944. qca_memdump->current_seq_no += 1;
  945. qca_memdump->received_dump = rx_size;
  946. } else {
  947. bt_dev_err(hu->hdev,
  948. "QCA memdump received no space for packet %d",
  949. qca_memdump->current_seq_no);
  950. }
  951. if (seq_no == QCA_LAST_SEQUENCE_NUM) {
  952. bt_dev_info(hu->hdev,
  953. "QCA memdump Done, received %d, total %d",
  954. qca_memdump->received_dump,
  955. qca_memdump->ram_dump_size);
  956. hci_devcd_complete(hu->hdev);
  957. cancel_delayed_work(&qca->ctrl_memdump_timeout);
  958. kfree(qca->qca_memdump);
  959. qca->qca_memdump = NULL;
  960. qca->memdump_state = QCA_MEMDUMP_COLLECTED;
  961. clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  962. }
  963. mutex_unlock(&qca->hci_memdump_lock);
  964. }
  965. }
  966. static int qca_controller_memdump_event(struct hci_dev *hdev,
  967. struct sk_buff *skb)
  968. {
  969. struct hci_uart *hu = hci_get_drvdata(hdev);
  970. struct qca_data *qca = hu->priv;
  971. set_bit(QCA_SSR_TRIGGERED, &qca->flags);
  972. skb_queue_tail(&qca->rx_memdump_q, skb);
  973. queue_work(qca->workqueue, &qca->ctrl_memdump_evt);
  974. return 0;
  975. }
  976. static int qca_recv_event(struct hci_dev *hdev, struct sk_buff *skb)
  977. {
  978. struct hci_uart *hu = hci_get_drvdata(hdev);
  979. struct qca_data *qca = hu->priv;
  980. if (test_bit(QCA_DROP_VENDOR_EVENT, &qca->flags)) {
  981. struct hci_event_hdr *hdr = (void *)skb->data;
  982. /* For the WCN3990 the vendor command for a baudrate change
  983. * isn't sent as synchronous HCI command, because the
  984. * controller sends the corresponding vendor event with the
  985. * new baudrate. The event is received and properly decoded
  986. * after changing the baudrate of the host port. It needs to
  987. * be dropped, otherwise it can be misinterpreted as
  988. * response to a later firmware download command (also a
  989. * vendor command).
  990. */
  991. if (hdr->evt == HCI_EV_VENDOR)
  992. complete(&qca->drop_ev_comp);
  993. kfree_skb(skb);
  994. return 0;
  995. }
  996. /* We receive chip memory dump as an event packet, With a dedicated
  997. * handler followed by a hardware error event. When this event is
  998. * received we store dump into a file before closing hci. This
  999. * dump will help in triaging the issues.
  1000. */
  1001. if ((skb->data[0] == HCI_VENDOR_PKT) &&
  1002. (get_unaligned_be16(skb->data + 2) == QCA_SSR_DUMP_HANDLE))
  1003. return qca_controller_memdump_event(hdev, skb);
  1004. return hci_recv_frame(hdev, skb);
  1005. }
  1006. #define QCA_IBS_SLEEP_IND_EVENT \
  1007. .type = HCI_IBS_SLEEP_IND, \
  1008. .hlen = 0, \
  1009. .loff = 0, \
  1010. .lsize = 0, \
  1011. .maxlen = HCI_MAX_IBS_SIZE
  1012. #define QCA_IBS_WAKE_IND_EVENT \
  1013. .type = HCI_IBS_WAKE_IND, \
  1014. .hlen = 0, \
  1015. .loff = 0, \
  1016. .lsize = 0, \
  1017. .maxlen = HCI_MAX_IBS_SIZE
  1018. #define QCA_IBS_WAKE_ACK_EVENT \
  1019. .type = HCI_IBS_WAKE_ACK, \
  1020. .hlen = 0, \
  1021. .loff = 0, \
  1022. .lsize = 0, \
  1023. .maxlen = HCI_MAX_IBS_SIZE
  1024. static const struct h4_recv_pkt qca_recv_pkts[] = {
  1025. { H4_RECV_ACL, .recv = qca_recv_acl_data },
  1026. { H4_RECV_SCO, .recv = hci_recv_frame },
  1027. { H4_RECV_EVENT, .recv = qca_recv_event },
  1028. { QCA_IBS_WAKE_IND_EVENT, .recv = qca_ibs_wake_ind },
  1029. { QCA_IBS_WAKE_ACK_EVENT, .recv = qca_ibs_wake_ack },
  1030. { QCA_IBS_SLEEP_IND_EVENT, .recv = qca_ibs_sleep_ind },
  1031. };
  1032. static int qca_recv(struct hci_uart *hu, const void *data, int count)
  1033. {
  1034. struct qca_data *qca = hu->priv;
  1035. if (!test_bit(HCI_UART_REGISTERED, &hu->flags))
  1036. return -EUNATCH;
  1037. qca->rx_skb = h4_recv_buf(hu->hdev, qca->rx_skb, data, count,
  1038. qca_recv_pkts, ARRAY_SIZE(qca_recv_pkts));
  1039. if (IS_ERR(qca->rx_skb)) {
  1040. int err = PTR_ERR(qca->rx_skb);
  1041. bt_dev_err(hu->hdev, "Frame reassembly failed (%d)", err);
  1042. qca->rx_skb = NULL;
  1043. return err;
  1044. }
  1045. return count;
  1046. }
  1047. static struct sk_buff *qca_dequeue(struct hci_uart *hu)
  1048. {
  1049. struct qca_data *qca = hu->priv;
  1050. return skb_dequeue(&qca->txq);
  1051. }
  1052. static uint8_t qca_get_baudrate_value(int speed)
  1053. {
  1054. switch (speed) {
  1055. case 9600:
  1056. return QCA_BAUDRATE_9600;
  1057. case 19200:
  1058. return QCA_BAUDRATE_19200;
  1059. case 38400:
  1060. return QCA_BAUDRATE_38400;
  1061. case 57600:
  1062. return QCA_BAUDRATE_57600;
  1063. case 115200:
  1064. return QCA_BAUDRATE_115200;
  1065. case 230400:
  1066. return QCA_BAUDRATE_230400;
  1067. case 460800:
  1068. return QCA_BAUDRATE_460800;
  1069. case 500000:
  1070. return QCA_BAUDRATE_500000;
  1071. case 921600:
  1072. return QCA_BAUDRATE_921600;
  1073. case 1000000:
  1074. return QCA_BAUDRATE_1000000;
  1075. case 2000000:
  1076. return QCA_BAUDRATE_2000000;
  1077. case 3000000:
  1078. return QCA_BAUDRATE_3000000;
  1079. case 3200000:
  1080. return QCA_BAUDRATE_3200000;
  1081. case 3500000:
  1082. return QCA_BAUDRATE_3500000;
  1083. default:
  1084. return QCA_BAUDRATE_115200;
  1085. }
  1086. }
  1087. static int qca_set_baudrate(struct hci_dev *hdev, uint8_t baudrate)
  1088. {
  1089. struct hci_uart *hu = hci_get_drvdata(hdev);
  1090. struct qca_data *qca = hu->priv;
  1091. struct sk_buff *skb;
  1092. u8 cmd[] = { 0x01, 0x48, 0xFC, 0x01, 0x00 };
  1093. if (baudrate > QCA_BAUDRATE_3200000)
  1094. return -EINVAL;
  1095. cmd[4] = baudrate;
  1096. skb = bt_skb_alloc(sizeof(cmd), GFP_KERNEL);
  1097. if (!skb) {
  1098. bt_dev_err(hdev, "Failed to allocate baudrate packet");
  1099. return -ENOMEM;
  1100. }
  1101. /* Assign commands to change baudrate and packet type. */
  1102. skb_put_data(skb, cmd, sizeof(cmd));
  1103. hci_skb_pkt_type(skb) = HCI_COMMAND_PKT;
  1104. skb_queue_tail(&qca->txq, skb);
  1105. hci_uart_tx_wakeup(hu);
  1106. /* Wait for the baudrate change request to be sent */
  1107. while (!skb_queue_empty(&qca->txq))
  1108. usleep_range(100, 200);
  1109. if (hu->serdev)
  1110. serdev_device_wait_until_sent(hu->serdev,
  1111. msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS));
  1112. /* Give the controller time to process the request */
  1113. switch (qca_soc_type(hu)) {
  1114. case QCA_WCN3988:
  1115. case QCA_WCN3990:
  1116. case QCA_WCN3991:
  1117. case QCA_WCN3998:
  1118. case QCA_WCN6750:
  1119. case QCA_WCN6855:
  1120. case QCA_WCN7850:
  1121. usleep_range(1000, 10000);
  1122. break;
  1123. default:
  1124. msleep(300);
  1125. }
  1126. return 0;
  1127. }
  1128. static inline void host_set_baudrate(struct hci_uart *hu, unsigned int speed)
  1129. {
  1130. if (hu->serdev)
  1131. serdev_device_set_baudrate(hu->serdev, speed);
  1132. else
  1133. hci_uart_set_baudrate(hu, speed);
  1134. }
  1135. static int qca_send_power_pulse(struct hci_uart *hu, bool on)
  1136. {
  1137. int ret;
  1138. int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS);
  1139. u8 cmd = on ? QCA_WCN3990_POWERON_PULSE : QCA_WCN3990_POWEROFF_PULSE;
  1140. /* These power pulses are single byte command which are sent
  1141. * at required baudrate to wcn3990. On wcn3990, we have an external
  1142. * circuit at Tx pin which decodes the pulse sent at specific baudrate.
  1143. * For example, wcn3990 supports RF COEX antenna for both Wi-Fi/BT
  1144. * and also we use the same power inputs to turn on and off for
  1145. * Wi-Fi/BT. Powering up the power sources will not enable BT, until
  1146. * we send a power on pulse at 115200 bps. This algorithm will help to
  1147. * save power. Disabling hardware flow control is mandatory while
  1148. * sending power pulses to SoC.
  1149. */
  1150. bt_dev_dbg(hu->hdev, "sending power pulse %02x to controller", cmd);
  1151. serdev_device_write_flush(hu->serdev);
  1152. hci_uart_set_flow_control(hu, true);
  1153. ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd));
  1154. if (ret < 0) {
  1155. bt_dev_err(hu->hdev, "failed to send power pulse %02x", cmd);
  1156. return ret;
  1157. }
  1158. serdev_device_wait_until_sent(hu->serdev, timeout);
  1159. hci_uart_set_flow_control(hu, false);
  1160. /* Give to controller time to boot/shutdown */
  1161. if (on)
  1162. msleep(100);
  1163. else
  1164. usleep_range(1000, 10000);
  1165. return 0;
  1166. }
  1167. static unsigned int qca_get_speed(struct hci_uart *hu,
  1168. enum qca_speed_type speed_type)
  1169. {
  1170. unsigned int speed = 0;
  1171. if (speed_type == QCA_INIT_SPEED) {
  1172. if (hu->init_speed)
  1173. speed = hu->init_speed;
  1174. else if (hu->proto->init_speed)
  1175. speed = hu->proto->init_speed;
  1176. } else {
  1177. if (hu->oper_speed)
  1178. speed = hu->oper_speed;
  1179. else if (hu->proto->oper_speed)
  1180. speed = hu->proto->oper_speed;
  1181. }
  1182. return speed;
  1183. }
  1184. static int qca_check_speeds(struct hci_uart *hu)
  1185. {
  1186. switch (qca_soc_type(hu)) {
  1187. case QCA_WCN3988:
  1188. case QCA_WCN3990:
  1189. case QCA_WCN3991:
  1190. case QCA_WCN3998:
  1191. case QCA_WCN6750:
  1192. case QCA_WCN6855:
  1193. case QCA_WCN7850:
  1194. if (!qca_get_speed(hu, QCA_INIT_SPEED) &&
  1195. !qca_get_speed(hu, QCA_OPER_SPEED))
  1196. return -EINVAL;
  1197. break;
  1198. default:
  1199. if (!qca_get_speed(hu, QCA_INIT_SPEED) ||
  1200. !qca_get_speed(hu, QCA_OPER_SPEED))
  1201. return -EINVAL;
  1202. }
  1203. return 0;
  1204. }
  1205. static int qca_set_speed(struct hci_uart *hu, enum qca_speed_type speed_type)
  1206. {
  1207. unsigned int speed, qca_baudrate;
  1208. struct qca_data *qca = hu->priv;
  1209. int ret = 0;
  1210. if (speed_type == QCA_INIT_SPEED) {
  1211. speed = qca_get_speed(hu, QCA_INIT_SPEED);
  1212. if (speed)
  1213. host_set_baudrate(hu, speed);
  1214. } else {
  1215. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1216. speed = qca_get_speed(hu, QCA_OPER_SPEED);
  1217. if (!speed)
  1218. return 0;
  1219. /* Disable flow control for wcn3990 to deassert RTS while
  1220. * changing the baudrate of chip and host.
  1221. */
  1222. switch (soc_type) {
  1223. case QCA_WCN3988:
  1224. case QCA_WCN3990:
  1225. case QCA_WCN3991:
  1226. case QCA_WCN3998:
  1227. case QCA_WCN6750:
  1228. case QCA_WCN6855:
  1229. case QCA_WCN7850:
  1230. hci_uart_set_flow_control(hu, true);
  1231. break;
  1232. default:
  1233. break;
  1234. }
  1235. switch (soc_type) {
  1236. case QCA_WCN3990:
  1237. reinit_completion(&qca->drop_ev_comp);
  1238. set_bit(QCA_DROP_VENDOR_EVENT, &qca->flags);
  1239. break;
  1240. default:
  1241. break;
  1242. }
  1243. qca_baudrate = qca_get_baudrate_value(speed);
  1244. bt_dev_dbg(hu->hdev, "Set UART speed to %d", speed);
  1245. ret = qca_set_baudrate(hu->hdev, qca_baudrate);
  1246. if (ret)
  1247. goto error;
  1248. host_set_baudrate(hu, speed);
  1249. error:
  1250. switch (soc_type) {
  1251. case QCA_WCN3988:
  1252. case QCA_WCN3990:
  1253. case QCA_WCN3991:
  1254. case QCA_WCN3998:
  1255. case QCA_WCN6750:
  1256. case QCA_WCN6855:
  1257. case QCA_WCN7850:
  1258. hci_uart_set_flow_control(hu, false);
  1259. break;
  1260. default:
  1261. break;
  1262. }
  1263. switch (soc_type) {
  1264. case QCA_WCN3990:
  1265. /* Wait for the controller to send the vendor event
  1266. * for the baudrate change command.
  1267. */
  1268. if (!wait_for_completion_timeout(&qca->drop_ev_comp,
  1269. msecs_to_jiffies(100))) {
  1270. bt_dev_err(hu->hdev,
  1271. "Failed to change controller baudrate\n");
  1272. ret = -ETIMEDOUT;
  1273. }
  1274. clear_bit(QCA_DROP_VENDOR_EVENT, &qca->flags);
  1275. break;
  1276. default:
  1277. break;
  1278. }
  1279. }
  1280. return ret;
  1281. }
  1282. static int qca_send_crashbuffer(struct hci_uart *hu)
  1283. {
  1284. struct qca_data *qca = hu->priv;
  1285. struct sk_buff *skb;
  1286. skb = bt_skb_alloc(QCA_CRASHBYTE_PACKET_LEN, GFP_KERNEL);
  1287. if (!skb) {
  1288. bt_dev_err(hu->hdev, "Failed to allocate memory for skb packet");
  1289. return -ENOMEM;
  1290. }
  1291. /* We forcefully crash the controller, by sending 0xfb byte for
  1292. * 1024 times. We also might have chance of losing data, To be
  1293. * on safer side we send 1096 bytes to the SoC.
  1294. */
  1295. memset(skb_put(skb, QCA_CRASHBYTE_PACKET_LEN), QCA_MEMDUMP_BYTE,
  1296. QCA_CRASHBYTE_PACKET_LEN);
  1297. hci_skb_pkt_type(skb) = HCI_COMMAND_PKT;
  1298. bt_dev_info(hu->hdev, "crash the soc to collect controller dump");
  1299. skb_queue_tail(&qca->txq, skb);
  1300. hci_uart_tx_wakeup(hu);
  1301. return 0;
  1302. }
  1303. static void qca_wait_for_dump_collection(struct hci_dev *hdev)
  1304. {
  1305. struct hci_uart *hu = hci_get_drvdata(hdev);
  1306. struct qca_data *qca = hu->priv;
  1307. wait_on_bit_timeout(&qca->flags, QCA_MEMDUMP_COLLECTION,
  1308. TASK_UNINTERRUPTIBLE, MEMDUMP_TIMEOUT_MS);
  1309. clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  1310. }
  1311. static void qca_hw_error(struct hci_dev *hdev, u8 code)
  1312. {
  1313. struct hci_uart *hu = hci_get_drvdata(hdev);
  1314. struct qca_data *qca = hu->priv;
  1315. set_bit(QCA_SSR_TRIGGERED, &qca->flags);
  1316. set_bit(QCA_HW_ERROR_EVENT, &qca->flags);
  1317. bt_dev_info(hdev, "mem_dump_status: %d", qca->memdump_state);
  1318. if (qca->memdump_state == QCA_MEMDUMP_IDLE) {
  1319. /* If hardware error event received for other than QCA
  1320. * soc memory dump event, then we need to crash the SOC
  1321. * and wait here for 8 seconds to get the dump packets.
  1322. * This will block main thread to be on hold until we
  1323. * collect dump.
  1324. */
  1325. set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  1326. qca_send_crashbuffer(hu);
  1327. qca_wait_for_dump_collection(hdev);
  1328. } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) {
  1329. /* Let us wait here until memory dump collected or
  1330. * memory dump timer expired.
  1331. */
  1332. bt_dev_info(hdev, "waiting for dump to complete");
  1333. qca_wait_for_dump_collection(hdev);
  1334. }
  1335. mutex_lock(&qca->hci_memdump_lock);
  1336. if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) {
  1337. bt_dev_err(hu->hdev, "clearing allocated memory due to memdump timeout");
  1338. hci_devcd_abort(hu->hdev);
  1339. if (qca->qca_memdump) {
  1340. kfree(qca->qca_memdump);
  1341. qca->qca_memdump = NULL;
  1342. }
  1343. qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
  1344. cancel_delayed_work(&qca->ctrl_memdump_timeout);
  1345. }
  1346. mutex_unlock(&qca->hci_memdump_lock);
  1347. if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT ||
  1348. qca->memdump_state == QCA_MEMDUMP_COLLECTED) {
  1349. cancel_work_sync(&qca->ctrl_memdump_evt);
  1350. skb_queue_purge(&qca->rx_memdump_q);
  1351. }
  1352. clear_bit(QCA_HW_ERROR_EVENT, &qca->flags);
  1353. }
  1354. static void qca_cmd_timeout(struct hci_dev *hdev)
  1355. {
  1356. struct hci_uart *hu = hci_get_drvdata(hdev);
  1357. struct qca_data *qca = hu->priv;
  1358. set_bit(QCA_SSR_TRIGGERED, &qca->flags);
  1359. if (qca->memdump_state == QCA_MEMDUMP_IDLE) {
  1360. set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  1361. qca_send_crashbuffer(hu);
  1362. qca_wait_for_dump_collection(hdev);
  1363. } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) {
  1364. /* Let us wait here until memory dump collected or
  1365. * memory dump timer expired.
  1366. */
  1367. bt_dev_info(hdev, "waiting for dump to complete");
  1368. qca_wait_for_dump_collection(hdev);
  1369. }
  1370. mutex_lock(&qca->hci_memdump_lock);
  1371. if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) {
  1372. qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
  1373. if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) {
  1374. /* Inject hw error event to reset the device
  1375. * and driver.
  1376. */
  1377. hci_reset_dev(hu->hdev);
  1378. }
  1379. }
  1380. mutex_unlock(&qca->hci_memdump_lock);
  1381. }
  1382. static bool qca_wakeup(struct hci_dev *hdev)
  1383. {
  1384. struct hci_uart *hu = hci_get_drvdata(hdev);
  1385. bool wakeup;
  1386. if (!hu->serdev)
  1387. return true;
  1388. /* BT SoC attached through the serial bus is handled by the serdev driver.
  1389. * So we need to use the device handle of the serdev driver to get the
  1390. * status of device may wakeup.
  1391. */
  1392. wakeup = device_may_wakeup(&hu->serdev->ctrl->dev);
  1393. bt_dev_dbg(hu->hdev, "wakeup status : %d", wakeup);
  1394. return wakeup;
  1395. }
  1396. static int qca_port_reopen(struct hci_uart *hu)
  1397. {
  1398. int ret;
  1399. /* Now the device is in ready state to communicate with host.
  1400. * To sync host with device we need to reopen port.
  1401. * Without this, we will have RTS and CTS synchronization
  1402. * issues.
  1403. */
  1404. serdev_device_close(hu->serdev);
  1405. ret = serdev_device_open(hu->serdev);
  1406. if (ret) {
  1407. bt_dev_err(hu->hdev, "failed to open port");
  1408. return ret;
  1409. }
  1410. hci_uart_set_flow_control(hu, false);
  1411. return 0;
  1412. }
  1413. static int qca_regulator_init(struct hci_uart *hu)
  1414. {
  1415. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1416. struct qca_serdev *qcadev;
  1417. int ret;
  1418. bool sw_ctrl_state;
  1419. /* Check for vregs status, may be hci down has turned
  1420. * off the voltage regulator.
  1421. */
  1422. qcadev = serdev_device_get_drvdata(hu->serdev);
  1423. if (!qcadev->bt_power->vregs_on) {
  1424. serdev_device_close(hu->serdev);
  1425. ret = qca_regulator_enable(qcadev);
  1426. if (ret)
  1427. return ret;
  1428. ret = serdev_device_open(hu->serdev);
  1429. if (ret) {
  1430. bt_dev_err(hu->hdev, "failed to open port");
  1431. return ret;
  1432. }
  1433. }
  1434. switch (soc_type) {
  1435. case QCA_WCN3988:
  1436. case QCA_WCN3990:
  1437. case QCA_WCN3991:
  1438. case QCA_WCN3998:
  1439. /* Forcefully enable wcn399x to enter in to boot mode. */
  1440. host_set_baudrate(hu, 2400);
  1441. ret = qca_send_power_pulse(hu, false);
  1442. if (ret)
  1443. return ret;
  1444. break;
  1445. default:
  1446. break;
  1447. }
  1448. /* For wcn6750 need to enable gpio bt_en */
  1449. if (qcadev->bt_en) {
  1450. gpiod_set_value_cansleep(qcadev->bt_en, 0);
  1451. msleep(50);
  1452. gpiod_set_value_cansleep(qcadev->bt_en, 1);
  1453. msleep(50);
  1454. if (qcadev->sw_ctrl) {
  1455. sw_ctrl_state = gpiod_get_value_cansleep(qcadev->sw_ctrl);
  1456. bt_dev_dbg(hu->hdev, "SW_CTRL is %d", sw_ctrl_state);
  1457. }
  1458. }
  1459. qca_set_speed(hu, QCA_INIT_SPEED);
  1460. switch (soc_type) {
  1461. case QCA_WCN3988:
  1462. case QCA_WCN3990:
  1463. case QCA_WCN3991:
  1464. case QCA_WCN3998:
  1465. ret = qca_send_power_pulse(hu, true);
  1466. if (ret)
  1467. return ret;
  1468. break;
  1469. default:
  1470. break;
  1471. }
  1472. return qca_port_reopen(hu);
  1473. }
  1474. static int qca_power_on(struct hci_dev *hdev)
  1475. {
  1476. struct hci_uart *hu = hci_get_drvdata(hdev);
  1477. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1478. struct qca_serdev *qcadev;
  1479. struct qca_data *qca = hu->priv;
  1480. int ret = 0;
  1481. /* Non-serdev device usually is powered by external power
  1482. * and don't need additional action in driver for power on
  1483. */
  1484. if (!hu->serdev)
  1485. return 0;
  1486. switch (soc_type) {
  1487. case QCA_WCN3988:
  1488. case QCA_WCN3990:
  1489. case QCA_WCN3991:
  1490. case QCA_WCN3998:
  1491. case QCA_WCN6750:
  1492. case QCA_WCN6855:
  1493. case QCA_WCN7850:
  1494. case QCA_QCA6390:
  1495. ret = qca_regulator_init(hu);
  1496. break;
  1497. default:
  1498. qcadev = serdev_device_get_drvdata(hu->serdev);
  1499. if (qcadev->bt_en) {
  1500. gpiod_set_value_cansleep(qcadev->bt_en, 1);
  1501. /* Controller needs time to bootup. */
  1502. msleep(150);
  1503. }
  1504. }
  1505. clear_bit(QCA_BT_OFF, &qca->flags);
  1506. return ret;
  1507. }
  1508. static void hci_coredump_qca(struct hci_dev *hdev)
  1509. {
  1510. int err;
  1511. static const u8 param[] = { 0x26 };
  1512. err = __hci_cmd_send(hdev, 0xfc0c, 1, param);
  1513. if (err < 0)
  1514. bt_dev_err(hdev, "%s: trigger crash failed (%d)", __func__, err);
  1515. }
  1516. static int qca_get_data_path_id(struct hci_dev *hdev, __u8 *data_path_id)
  1517. {
  1518. /* QCA uses 1 as non-HCI data path id for HFP */
  1519. *data_path_id = 1;
  1520. return 0;
  1521. }
  1522. static int qca_configure_hfp_offload(struct hci_dev *hdev)
  1523. {
  1524. bt_dev_info(hdev, "HFP non-HCI data transport is supported");
  1525. hdev->get_data_path_id = qca_get_data_path_id;
  1526. /* Do not need to send HCI_Configure_Data_Path to configure non-HCI
  1527. * data transport path for QCA controllers, so set below field as NULL.
  1528. */
  1529. hdev->get_codec_config_data = NULL;
  1530. return 0;
  1531. }
  1532. static int qca_setup(struct hci_uart *hu)
  1533. {
  1534. struct hci_dev *hdev = hu->hdev;
  1535. struct qca_data *qca = hu->priv;
  1536. unsigned int speed, qca_baudrate = QCA_BAUDRATE_115200;
  1537. unsigned int retries = 0;
  1538. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1539. const char *firmware_name = qca_get_firmware_name(hu);
  1540. int ret;
  1541. struct qca_btsoc_version ver;
  1542. struct qca_serdev *qcadev;
  1543. const char *soc_name;
  1544. ret = qca_check_speeds(hu);
  1545. if (ret)
  1546. return ret;
  1547. clear_bit(QCA_ROM_FW, &qca->flags);
  1548. /* Patch downloading has to be done without IBS mode */
  1549. set_bit(QCA_IBS_DISABLED, &qca->flags);
  1550. /* Enable controller to do both LE scan and BR/EDR inquiry
  1551. * simultaneously.
  1552. */
  1553. set_bit(HCI_QUIRK_SIMULTANEOUS_DISCOVERY, &hdev->quirks);
  1554. switch (soc_type) {
  1555. case QCA_QCA2066:
  1556. soc_name = "qca2066";
  1557. break;
  1558. case QCA_WCN3988:
  1559. case QCA_WCN3990:
  1560. case QCA_WCN3991:
  1561. case QCA_WCN3998:
  1562. soc_name = "wcn399x";
  1563. break;
  1564. case QCA_WCN6750:
  1565. soc_name = "wcn6750";
  1566. break;
  1567. case QCA_WCN6855:
  1568. soc_name = "wcn6855";
  1569. break;
  1570. case QCA_WCN7850:
  1571. soc_name = "wcn7850";
  1572. break;
  1573. default:
  1574. soc_name = "ROME/QCA6390";
  1575. }
  1576. bt_dev_info(hdev, "setting up %s", soc_name);
  1577. qca->memdump_state = QCA_MEMDUMP_IDLE;
  1578. retry:
  1579. ret = qca_power_on(hdev);
  1580. if (ret)
  1581. goto out;
  1582. clear_bit(QCA_SSR_TRIGGERED, &qca->flags);
  1583. switch (soc_type) {
  1584. case QCA_WCN3988:
  1585. case QCA_WCN3990:
  1586. case QCA_WCN3991:
  1587. case QCA_WCN3998:
  1588. case QCA_WCN6750:
  1589. case QCA_WCN6855:
  1590. case QCA_WCN7850:
  1591. qcadev = serdev_device_get_drvdata(hu->serdev);
  1592. if (qcadev->bdaddr_property_broken)
  1593. set_bit(HCI_QUIRK_BDADDR_PROPERTY_BROKEN, &hdev->quirks);
  1594. hci_set_aosp_capable(hdev);
  1595. ret = qca_read_soc_version(hdev, &ver, soc_type);
  1596. if (ret)
  1597. goto out;
  1598. break;
  1599. default:
  1600. qca_set_speed(hu, QCA_INIT_SPEED);
  1601. }
  1602. /* Setup user speed if needed */
  1603. speed = qca_get_speed(hu, QCA_OPER_SPEED);
  1604. if (speed) {
  1605. ret = qca_set_speed(hu, QCA_OPER_SPEED);
  1606. if (ret)
  1607. goto out;
  1608. qca_baudrate = qca_get_baudrate_value(speed);
  1609. }
  1610. switch (soc_type) {
  1611. case QCA_WCN3988:
  1612. case QCA_WCN3990:
  1613. case QCA_WCN3991:
  1614. case QCA_WCN3998:
  1615. case QCA_WCN6750:
  1616. case QCA_WCN6855:
  1617. case QCA_WCN7850:
  1618. break;
  1619. default:
  1620. /* Get QCA version information */
  1621. ret = qca_read_soc_version(hdev, &ver, soc_type);
  1622. if (ret)
  1623. goto out;
  1624. }
  1625. /* Setup patch / NVM configurations */
  1626. ret = qca_uart_setup(hdev, qca_baudrate, soc_type, ver,
  1627. firmware_name);
  1628. if (!ret) {
  1629. clear_bit(QCA_IBS_DISABLED, &qca->flags);
  1630. qca_debugfs_init(hdev);
  1631. hu->hdev->hw_error = qca_hw_error;
  1632. hu->hdev->cmd_timeout = qca_cmd_timeout;
  1633. if (hu->serdev) {
  1634. if (device_can_wakeup(hu->serdev->ctrl->dev.parent))
  1635. hu->hdev->wakeup = qca_wakeup;
  1636. }
  1637. } else if (ret == -ENOENT) {
  1638. /* No patch/nvm-config found, run with original fw/config */
  1639. set_bit(QCA_ROM_FW, &qca->flags);
  1640. ret = 0;
  1641. } else if (ret == -EAGAIN) {
  1642. /*
  1643. * Userspace firmware loader will return -EAGAIN in case no
  1644. * patch/nvm-config is found, so run with original fw/config.
  1645. */
  1646. set_bit(QCA_ROM_FW, &qca->flags);
  1647. ret = 0;
  1648. }
  1649. out:
  1650. if (ret && retries < MAX_INIT_RETRIES) {
  1651. bt_dev_warn(hdev, "Retry BT power ON:%d", retries);
  1652. qca_power_shutdown(hu);
  1653. if (hu->serdev) {
  1654. serdev_device_close(hu->serdev);
  1655. ret = serdev_device_open(hu->serdev);
  1656. if (ret) {
  1657. bt_dev_err(hdev, "failed to open port");
  1658. return ret;
  1659. }
  1660. }
  1661. retries++;
  1662. goto retry;
  1663. }
  1664. /* Setup bdaddr */
  1665. if (soc_type == QCA_ROME)
  1666. hu->hdev->set_bdaddr = qca_set_bdaddr_rome;
  1667. else
  1668. hu->hdev->set_bdaddr = qca_set_bdaddr;
  1669. if (soc_type == QCA_QCA2066)
  1670. qca_configure_hfp_offload(hdev);
  1671. qca->fw_version = le16_to_cpu(ver.patch_ver);
  1672. qca->controller_id = le16_to_cpu(ver.rom_ver);
  1673. hci_devcd_register(hdev, hci_coredump_qca, qca_dmp_hdr, NULL);
  1674. return ret;
  1675. }
  1676. static const struct hci_uart_proto qca_proto = {
  1677. .id = HCI_UART_QCA,
  1678. .name = "QCA",
  1679. .manufacturer = 29,
  1680. .init_speed = 115200,
  1681. .oper_speed = 3000000,
  1682. .open = qca_open,
  1683. .close = qca_close,
  1684. .flush = qca_flush,
  1685. .setup = qca_setup,
  1686. .recv = qca_recv,
  1687. .enqueue = qca_enqueue,
  1688. .dequeue = qca_dequeue,
  1689. };
  1690. static const struct qca_device_data qca_soc_data_wcn3988 __maybe_unused = {
  1691. .soc_type = QCA_WCN3988,
  1692. .vregs = (struct qca_vreg []) {
  1693. { "vddio", 15000 },
  1694. { "vddxo", 80000 },
  1695. { "vddrf", 300000 },
  1696. { "vddch0", 450000 },
  1697. },
  1698. .num_vregs = 4,
  1699. };
  1700. static const struct qca_device_data qca_soc_data_wcn3990 __maybe_unused = {
  1701. .soc_type = QCA_WCN3990,
  1702. .vregs = (struct qca_vreg []) {
  1703. { "vddio", 15000 },
  1704. { "vddxo", 80000 },
  1705. { "vddrf", 300000 },
  1706. { "vddch0", 450000 },
  1707. },
  1708. .num_vregs = 4,
  1709. };
  1710. static const struct qca_device_data qca_soc_data_wcn3991 __maybe_unused = {
  1711. .soc_type = QCA_WCN3991,
  1712. .vregs = (struct qca_vreg []) {
  1713. { "vddio", 15000 },
  1714. { "vddxo", 80000 },
  1715. { "vddrf", 300000 },
  1716. { "vddch0", 450000 },
  1717. },
  1718. .num_vregs = 4,
  1719. .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES,
  1720. };
  1721. static const struct qca_device_data qca_soc_data_wcn3998 __maybe_unused = {
  1722. .soc_type = QCA_WCN3998,
  1723. .vregs = (struct qca_vreg []) {
  1724. { "vddio", 10000 },
  1725. { "vddxo", 80000 },
  1726. { "vddrf", 300000 },
  1727. { "vddch0", 450000 },
  1728. },
  1729. .num_vregs = 4,
  1730. };
  1731. static const struct qca_device_data qca_soc_data_qca2066 __maybe_unused = {
  1732. .soc_type = QCA_QCA2066,
  1733. .num_vregs = 0,
  1734. .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES,
  1735. };
  1736. static const struct qca_device_data qca_soc_data_qca6390 __maybe_unused = {
  1737. .soc_type = QCA_QCA6390,
  1738. .num_vregs = 0,
  1739. };
  1740. static const struct qca_device_data qca_soc_data_wcn6750 __maybe_unused = {
  1741. .soc_type = QCA_WCN6750,
  1742. .vregs = (struct qca_vreg []) {
  1743. { "vddio", 5000 },
  1744. { "vddaon", 26000 },
  1745. { "vddbtcxmx", 126000 },
  1746. { "vddrfacmn", 12500 },
  1747. { "vddrfa0p8", 102000 },
  1748. { "vddrfa1p7", 302000 },
  1749. { "vddrfa1p2", 257000 },
  1750. { "vddrfa2p2", 1700000 },
  1751. { "vddasd", 200 },
  1752. },
  1753. .num_vregs = 9,
  1754. .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES,
  1755. };
  1756. static const struct qca_device_data qca_soc_data_wcn6855 __maybe_unused = {
  1757. .soc_type = QCA_WCN6855,
  1758. .vregs = (struct qca_vreg []) {
  1759. { "vddio", 5000 },
  1760. { "vddbtcxmx", 126000 },
  1761. { "vddrfacmn", 12500 },
  1762. { "vddrfa0p8", 102000 },
  1763. { "vddrfa1p7", 302000 },
  1764. { "vddrfa1p2", 257000 },
  1765. },
  1766. .num_vregs = 6,
  1767. .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES,
  1768. };
  1769. static const struct qca_device_data qca_soc_data_wcn7850 __maybe_unused = {
  1770. .soc_type = QCA_WCN7850,
  1771. .vregs = (struct qca_vreg []) {
  1772. { "vddio", 5000 },
  1773. { "vddaon", 26000 },
  1774. { "vdddig", 126000 },
  1775. { "vddrfa0p8", 102000 },
  1776. { "vddrfa1p2", 257000 },
  1777. { "vddrfa1p9", 302000 },
  1778. },
  1779. .num_vregs = 6,
  1780. .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES,
  1781. };
  1782. static void qca_power_shutdown(struct hci_uart *hu)
  1783. {
  1784. struct qca_serdev *qcadev;
  1785. struct qca_data *qca = hu->priv;
  1786. unsigned long flags;
  1787. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1788. bool sw_ctrl_state;
  1789. struct qca_power *power;
  1790. /* From this point we go into power off state. But serial port is
  1791. * still open, stop queueing the IBS data and flush all the buffered
  1792. * data in skb's.
  1793. */
  1794. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  1795. set_bit(QCA_IBS_DISABLED, &qca->flags);
  1796. qca_flush(hu);
  1797. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  1798. /* Non-serdev device usually is powered by external power
  1799. * and don't need additional action in driver for power down
  1800. */
  1801. if (!hu->serdev)
  1802. return;
  1803. qcadev = serdev_device_get_drvdata(hu->serdev);
  1804. power = qcadev->bt_power;
  1805. if (power && power->pwrseq) {
  1806. pwrseq_power_off(power->pwrseq);
  1807. set_bit(QCA_BT_OFF, &qca->flags);
  1808. return;
  1809. }
  1810. switch (soc_type) {
  1811. case QCA_WCN3988:
  1812. case QCA_WCN3990:
  1813. case QCA_WCN3991:
  1814. case QCA_WCN3998:
  1815. host_set_baudrate(hu, 2400);
  1816. qca_send_power_pulse(hu, false);
  1817. qca_regulator_disable(qcadev);
  1818. break;
  1819. case QCA_WCN6750:
  1820. case QCA_WCN6855:
  1821. gpiod_set_value_cansleep(qcadev->bt_en, 0);
  1822. msleep(100);
  1823. qca_regulator_disable(qcadev);
  1824. if (qcadev->sw_ctrl) {
  1825. sw_ctrl_state = gpiod_get_value_cansleep(qcadev->sw_ctrl);
  1826. bt_dev_dbg(hu->hdev, "SW_CTRL is %d", sw_ctrl_state);
  1827. }
  1828. break;
  1829. default:
  1830. gpiod_set_value_cansleep(qcadev->bt_en, 0);
  1831. }
  1832. set_bit(QCA_BT_OFF, &qca->flags);
  1833. }
  1834. static int qca_power_off(struct hci_dev *hdev)
  1835. {
  1836. struct hci_uart *hu = hci_get_drvdata(hdev);
  1837. struct qca_data *qca = hu->priv;
  1838. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1839. hu->hdev->hw_error = NULL;
  1840. hu->hdev->cmd_timeout = NULL;
  1841. del_timer_sync(&qca->wake_retrans_timer);
  1842. del_timer_sync(&qca->tx_idle_timer);
  1843. /* Stop sending shutdown command if soc crashes. */
  1844. if (soc_type != QCA_ROME
  1845. && qca->memdump_state == QCA_MEMDUMP_IDLE) {
  1846. qca_send_pre_shutdown_cmd(hdev);
  1847. usleep_range(8000, 10000);
  1848. }
  1849. qca_power_shutdown(hu);
  1850. return 0;
  1851. }
  1852. static int qca_regulator_enable(struct qca_serdev *qcadev)
  1853. {
  1854. struct qca_power *power = qcadev->bt_power;
  1855. int ret;
  1856. if (power->pwrseq)
  1857. return pwrseq_power_on(power->pwrseq);
  1858. /* Already enabled */
  1859. if (power->vregs_on)
  1860. return 0;
  1861. BT_DBG("enabling %d regulators)", power->num_vregs);
  1862. ret = regulator_bulk_enable(power->num_vregs, power->vreg_bulk);
  1863. if (ret)
  1864. return ret;
  1865. power->vregs_on = true;
  1866. ret = clk_prepare_enable(qcadev->susclk);
  1867. if (ret)
  1868. qca_regulator_disable(qcadev);
  1869. return ret;
  1870. }
  1871. static void qca_regulator_disable(struct qca_serdev *qcadev)
  1872. {
  1873. struct qca_power *power;
  1874. if (!qcadev)
  1875. return;
  1876. power = qcadev->bt_power;
  1877. /* Already disabled? */
  1878. if (!power->vregs_on)
  1879. return;
  1880. regulator_bulk_disable(power->num_vregs, power->vreg_bulk);
  1881. power->vregs_on = false;
  1882. clk_disable_unprepare(qcadev->susclk);
  1883. }
  1884. static int qca_init_regulators(struct qca_power *qca,
  1885. const struct qca_vreg *vregs, size_t num_vregs)
  1886. {
  1887. struct regulator_bulk_data *bulk;
  1888. int ret;
  1889. int i;
  1890. bulk = devm_kcalloc(qca->dev, num_vregs, sizeof(*bulk), GFP_KERNEL);
  1891. if (!bulk)
  1892. return -ENOMEM;
  1893. for (i = 0; i < num_vregs; i++)
  1894. bulk[i].supply = vregs[i].name;
  1895. ret = devm_regulator_bulk_get(qca->dev, num_vregs, bulk);
  1896. if (ret < 0)
  1897. return ret;
  1898. for (i = 0; i < num_vregs; i++) {
  1899. ret = regulator_set_load(bulk[i].consumer, vregs[i].load_uA);
  1900. if (ret)
  1901. return ret;
  1902. }
  1903. qca->vreg_bulk = bulk;
  1904. qca->num_vregs = num_vregs;
  1905. return 0;
  1906. }
  1907. static void qca_clk_disable_unprepare(void *data)
  1908. {
  1909. struct clk *clk = data;
  1910. clk_disable_unprepare(clk);
  1911. }
  1912. static int qca_serdev_probe(struct serdev_device *serdev)
  1913. {
  1914. struct qca_serdev *qcadev;
  1915. struct hci_dev *hdev;
  1916. const struct qca_device_data *data;
  1917. int err;
  1918. bool power_ctrl_enabled = true;
  1919. qcadev = devm_kzalloc(&serdev->dev, sizeof(*qcadev), GFP_KERNEL);
  1920. if (!qcadev)
  1921. return -ENOMEM;
  1922. qcadev->serdev_hu.serdev = serdev;
  1923. data = device_get_match_data(&serdev->dev);
  1924. serdev_device_set_drvdata(serdev, qcadev);
  1925. device_property_read_string(&serdev->dev, "firmware-name",
  1926. &qcadev->firmware_name);
  1927. device_property_read_u32(&serdev->dev, "max-speed",
  1928. &qcadev->oper_speed);
  1929. if (!qcadev->oper_speed)
  1930. BT_DBG("UART will pick default operating speed");
  1931. qcadev->bdaddr_property_broken = device_property_read_bool(&serdev->dev,
  1932. "qcom,local-bd-address-broken");
  1933. if (data)
  1934. qcadev->btsoc_type = data->soc_type;
  1935. else
  1936. qcadev->btsoc_type = QCA_ROME;
  1937. switch (qcadev->btsoc_type) {
  1938. case QCA_WCN3988:
  1939. case QCA_WCN3990:
  1940. case QCA_WCN3991:
  1941. case QCA_WCN3998:
  1942. case QCA_WCN6750:
  1943. case QCA_WCN6855:
  1944. case QCA_WCN7850:
  1945. case QCA_QCA6390:
  1946. qcadev->bt_power = devm_kzalloc(&serdev->dev,
  1947. sizeof(struct qca_power),
  1948. GFP_KERNEL);
  1949. if (!qcadev->bt_power)
  1950. return -ENOMEM;
  1951. break;
  1952. default:
  1953. break;
  1954. }
  1955. switch (qcadev->btsoc_type) {
  1956. case QCA_WCN6855:
  1957. case QCA_WCN7850:
  1958. if (!device_property_present(&serdev->dev, "enable-gpios")) {
  1959. /*
  1960. * Backward compatibility with old DT sources. If the
  1961. * node doesn't have the 'enable-gpios' property then
  1962. * let's use the power sequencer. Otherwise, let's
  1963. * drive everything outselves.
  1964. */
  1965. qcadev->bt_power->pwrseq = devm_pwrseq_get(&serdev->dev,
  1966. "bluetooth");
  1967. if (IS_ERR(qcadev->bt_power->pwrseq))
  1968. return PTR_ERR(qcadev->bt_power->pwrseq);
  1969. break;
  1970. }
  1971. fallthrough;
  1972. case QCA_WCN3988:
  1973. case QCA_WCN3990:
  1974. case QCA_WCN3991:
  1975. case QCA_WCN3998:
  1976. case QCA_WCN6750:
  1977. qcadev->bt_power->dev = &serdev->dev;
  1978. err = qca_init_regulators(qcadev->bt_power, data->vregs,
  1979. data->num_vregs);
  1980. if (err) {
  1981. BT_ERR("Failed to init regulators:%d", err);
  1982. return err;
  1983. }
  1984. qcadev->bt_power->vregs_on = false;
  1985. qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable",
  1986. GPIOD_OUT_LOW);
  1987. if (IS_ERR(qcadev->bt_en) &&
  1988. (data->soc_type == QCA_WCN6750 ||
  1989. data->soc_type == QCA_WCN6855)) {
  1990. dev_err(&serdev->dev, "failed to acquire BT_EN gpio\n");
  1991. return PTR_ERR(qcadev->bt_en);
  1992. }
  1993. if (!qcadev->bt_en)
  1994. power_ctrl_enabled = false;
  1995. qcadev->sw_ctrl = devm_gpiod_get_optional(&serdev->dev, "swctrl",
  1996. GPIOD_IN);
  1997. if (IS_ERR(qcadev->sw_ctrl) &&
  1998. (data->soc_type == QCA_WCN6750 ||
  1999. data->soc_type == QCA_WCN6855 ||
  2000. data->soc_type == QCA_WCN7850)) {
  2001. dev_err(&serdev->dev, "failed to acquire SW_CTRL gpio\n");
  2002. return PTR_ERR(qcadev->sw_ctrl);
  2003. }
  2004. qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL);
  2005. if (IS_ERR(qcadev->susclk)) {
  2006. dev_err(&serdev->dev, "failed to acquire clk\n");
  2007. return PTR_ERR(qcadev->susclk);
  2008. }
  2009. break;
  2010. case QCA_QCA6390:
  2011. if (dev_of_node(&serdev->dev)) {
  2012. qcadev->bt_power->pwrseq = devm_pwrseq_get(&serdev->dev,
  2013. "bluetooth");
  2014. if (IS_ERR(qcadev->bt_power->pwrseq))
  2015. return PTR_ERR(qcadev->bt_power->pwrseq);
  2016. break;
  2017. }
  2018. fallthrough;
  2019. default:
  2020. qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable",
  2021. GPIOD_OUT_LOW);
  2022. if (IS_ERR(qcadev->bt_en)) {
  2023. dev_err(&serdev->dev, "failed to acquire enable gpio\n");
  2024. return PTR_ERR(qcadev->bt_en);
  2025. }
  2026. if (!qcadev->bt_en)
  2027. power_ctrl_enabled = false;
  2028. qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL);
  2029. if (IS_ERR(qcadev->susclk)) {
  2030. dev_warn(&serdev->dev, "failed to acquire clk\n");
  2031. return PTR_ERR(qcadev->susclk);
  2032. }
  2033. err = clk_set_rate(qcadev->susclk, SUSCLK_RATE_32KHZ);
  2034. if (err)
  2035. return err;
  2036. err = clk_prepare_enable(qcadev->susclk);
  2037. if (err)
  2038. return err;
  2039. err = devm_add_action_or_reset(&serdev->dev,
  2040. qca_clk_disable_unprepare,
  2041. qcadev->susclk);
  2042. if (err)
  2043. return err;
  2044. }
  2045. err = hci_uart_register_device(&qcadev->serdev_hu, &qca_proto);
  2046. if (err) {
  2047. BT_ERR("serdev registration failed");
  2048. return err;
  2049. }
  2050. hdev = qcadev->serdev_hu.hdev;
  2051. if (power_ctrl_enabled) {
  2052. set_bit(HCI_QUIRK_NON_PERSISTENT_SETUP, &hdev->quirks);
  2053. hdev->shutdown = qca_power_off;
  2054. }
  2055. if (data) {
  2056. /* Wideband speech support must be set per driver since it can't
  2057. * be queried via hci. Same with the valid le states quirk.
  2058. */
  2059. if (data->capabilities & QCA_CAP_WIDEBAND_SPEECH)
  2060. set_bit(HCI_QUIRK_WIDEBAND_SPEECH_SUPPORTED,
  2061. &hdev->quirks);
  2062. if (!(data->capabilities & QCA_CAP_VALID_LE_STATES))
  2063. set_bit(HCI_QUIRK_BROKEN_LE_STATES, &hdev->quirks);
  2064. }
  2065. return 0;
  2066. }
  2067. static void qca_serdev_remove(struct serdev_device *serdev)
  2068. {
  2069. struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
  2070. struct qca_power *power = qcadev->bt_power;
  2071. switch (qcadev->btsoc_type) {
  2072. case QCA_WCN3988:
  2073. case QCA_WCN3990:
  2074. case QCA_WCN3991:
  2075. case QCA_WCN3998:
  2076. case QCA_WCN6750:
  2077. case QCA_WCN6855:
  2078. case QCA_WCN7850:
  2079. if (power->vregs_on)
  2080. qca_power_shutdown(&qcadev->serdev_hu);
  2081. break;
  2082. default:
  2083. break;
  2084. }
  2085. hci_uart_unregister_device(&qcadev->serdev_hu);
  2086. }
  2087. static void qca_serdev_shutdown(struct device *dev)
  2088. {
  2089. int ret;
  2090. int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS);
  2091. struct serdev_device *serdev = to_serdev_device(dev);
  2092. struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
  2093. struct hci_uart *hu = &qcadev->serdev_hu;
  2094. struct hci_dev *hdev = hu->hdev;
  2095. const u8 ibs_wake_cmd[] = { 0xFD };
  2096. const u8 edl_reset_soc_cmd[] = { 0x01, 0x00, 0xFC, 0x01, 0x05 };
  2097. if (qcadev->btsoc_type == QCA_QCA6390) {
  2098. /* The purpose of sending the VSC is to reset SOC into a initial
  2099. * state and the state will ensure next hdev->setup() success.
  2100. * if HCI_QUIRK_NON_PERSISTENT_SETUP is set, it means that
  2101. * hdev->setup() can do its job regardless of SoC state, so
  2102. * don't need to send the VSC.
  2103. * if HCI_SETUP is set, it means that hdev->setup() was never
  2104. * invoked and the SOC is already in the initial state, so
  2105. * don't also need to send the VSC.
  2106. */
  2107. if (test_bit(HCI_QUIRK_NON_PERSISTENT_SETUP, &hdev->quirks) ||
  2108. hci_dev_test_flag(hdev, HCI_SETUP))
  2109. return;
  2110. /* The serdev must be in open state when conrol logic arrives
  2111. * here, so also fix the use-after-free issue caused by that
  2112. * the serdev is flushed or wrote after it is closed.
  2113. */
  2114. serdev_device_write_flush(serdev);
  2115. ret = serdev_device_write_buf(serdev, ibs_wake_cmd,
  2116. sizeof(ibs_wake_cmd));
  2117. if (ret < 0) {
  2118. BT_ERR("QCA send IBS_WAKE_IND error: %d", ret);
  2119. return;
  2120. }
  2121. serdev_device_wait_until_sent(serdev, timeout);
  2122. usleep_range(8000, 10000);
  2123. serdev_device_write_flush(serdev);
  2124. ret = serdev_device_write_buf(serdev, edl_reset_soc_cmd,
  2125. sizeof(edl_reset_soc_cmd));
  2126. if (ret < 0) {
  2127. BT_ERR("QCA send EDL_RESET_REQ error: %d", ret);
  2128. return;
  2129. }
  2130. serdev_device_wait_until_sent(serdev, timeout);
  2131. usleep_range(8000, 10000);
  2132. }
  2133. }
  2134. static int __maybe_unused qca_suspend(struct device *dev)
  2135. {
  2136. struct serdev_device *serdev = to_serdev_device(dev);
  2137. struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
  2138. struct hci_uart *hu = &qcadev->serdev_hu;
  2139. struct qca_data *qca = hu->priv;
  2140. unsigned long flags;
  2141. bool tx_pending = false;
  2142. int ret = 0;
  2143. u8 cmd;
  2144. u32 wait_timeout = 0;
  2145. set_bit(QCA_SUSPENDING, &qca->flags);
  2146. /* if BT SoC is running with default firmware then it does not
  2147. * support in-band sleep
  2148. */
  2149. if (test_bit(QCA_ROM_FW, &qca->flags))
  2150. return 0;
  2151. /* During SSR after memory dump collection, controller will be
  2152. * powered off and then powered on.If controller is powered off
  2153. * during SSR then we should wait until SSR is completed.
  2154. */
  2155. if (test_bit(QCA_BT_OFF, &qca->flags) &&
  2156. !test_bit(QCA_SSR_TRIGGERED, &qca->flags))
  2157. return 0;
  2158. if (test_bit(QCA_IBS_DISABLED, &qca->flags) ||
  2159. test_bit(QCA_SSR_TRIGGERED, &qca->flags)) {
  2160. wait_timeout = test_bit(QCA_SSR_TRIGGERED, &qca->flags) ?
  2161. IBS_DISABLE_SSR_TIMEOUT_MS :
  2162. FW_DOWNLOAD_TIMEOUT_MS;
  2163. /* QCA_IBS_DISABLED flag is set to true, During FW download
  2164. * and during memory dump collection. It is reset to false,
  2165. * After FW download complete.
  2166. */
  2167. wait_on_bit_timeout(&qca->flags, QCA_IBS_DISABLED,
  2168. TASK_UNINTERRUPTIBLE, msecs_to_jiffies(wait_timeout));
  2169. if (test_bit(QCA_IBS_DISABLED, &qca->flags)) {
  2170. bt_dev_err(hu->hdev, "SSR or FW download time out");
  2171. ret = -ETIMEDOUT;
  2172. goto error;
  2173. }
  2174. }
  2175. cancel_work_sync(&qca->ws_awake_device);
  2176. cancel_work_sync(&qca->ws_awake_rx);
  2177. spin_lock_irqsave_nested(&qca->hci_ibs_lock,
  2178. flags, SINGLE_DEPTH_NESTING);
  2179. switch (qca->tx_ibs_state) {
  2180. case HCI_IBS_TX_WAKING:
  2181. del_timer(&qca->wake_retrans_timer);
  2182. fallthrough;
  2183. case HCI_IBS_TX_AWAKE:
  2184. del_timer(&qca->tx_idle_timer);
  2185. serdev_device_write_flush(hu->serdev);
  2186. cmd = HCI_IBS_SLEEP_IND;
  2187. ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd));
  2188. if (ret < 0) {
  2189. BT_ERR("Failed to send SLEEP to device");
  2190. break;
  2191. }
  2192. qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
  2193. qca->ibs_sent_slps++;
  2194. tx_pending = true;
  2195. break;
  2196. case HCI_IBS_TX_ASLEEP:
  2197. break;
  2198. default:
  2199. BT_ERR("Spurious tx state %d", qca->tx_ibs_state);
  2200. ret = -EINVAL;
  2201. break;
  2202. }
  2203. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  2204. if (ret < 0)
  2205. goto error;
  2206. if (tx_pending) {
  2207. serdev_device_wait_until_sent(hu->serdev,
  2208. msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS));
  2209. serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu);
  2210. }
  2211. /* Wait for HCI_IBS_SLEEP_IND sent by device to indicate its Tx is going
  2212. * to sleep, so that the packet does not wake the system later.
  2213. */
  2214. ret = wait_event_interruptible_timeout(qca->suspend_wait_q,
  2215. qca->rx_ibs_state == HCI_IBS_RX_ASLEEP,
  2216. msecs_to_jiffies(IBS_BTSOC_TX_IDLE_TIMEOUT_MS));
  2217. if (ret == 0) {
  2218. ret = -ETIMEDOUT;
  2219. goto error;
  2220. }
  2221. return 0;
  2222. error:
  2223. clear_bit(QCA_SUSPENDING, &qca->flags);
  2224. return ret;
  2225. }
  2226. static int __maybe_unused qca_resume(struct device *dev)
  2227. {
  2228. struct serdev_device *serdev = to_serdev_device(dev);
  2229. struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
  2230. struct hci_uart *hu = &qcadev->serdev_hu;
  2231. struct qca_data *qca = hu->priv;
  2232. clear_bit(QCA_SUSPENDING, &qca->flags);
  2233. return 0;
  2234. }
  2235. static SIMPLE_DEV_PM_OPS(qca_pm_ops, qca_suspend, qca_resume);
  2236. #ifdef CONFIG_OF
  2237. static const struct of_device_id qca_bluetooth_of_match[] = {
  2238. { .compatible = "qcom,qca2066-bt", .data = &qca_soc_data_qca2066},
  2239. { .compatible = "qcom,qca6174-bt" },
  2240. { .compatible = "qcom,qca6390-bt", .data = &qca_soc_data_qca6390},
  2241. { .compatible = "qcom,qca9377-bt" },
  2242. { .compatible = "qcom,wcn3988-bt", .data = &qca_soc_data_wcn3988},
  2243. { .compatible = "qcom,wcn3990-bt", .data = &qca_soc_data_wcn3990},
  2244. { .compatible = "qcom,wcn3991-bt", .data = &qca_soc_data_wcn3991},
  2245. { .compatible = "qcom,wcn3998-bt", .data = &qca_soc_data_wcn3998},
  2246. { .compatible = "qcom,wcn6750-bt", .data = &qca_soc_data_wcn6750},
  2247. { .compatible = "qcom,wcn6855-bt", .data = &qca_soc_data_wcn6855},
  2248. { .compatible = "qcom,wcn7850-bt", .data = &qca_soc_data_wcn7850},
  2249. { /* sentinel */ }
  2250. };
  2251. MODULE_DEVICE_TABLE(of, qca_bluetooth_of_match);
  2252. #endif
  2253. #ifdef CONFIG_ACPI
  2254. static const struct acpi_device_id qca_bluetooth_acpi_match[] = {
  2255. { "QCOM2066", (kernel_ulong_t)&qca_soc_data_qca2066 },
  2256. { "QCOM6390", (kernel_ulong_t)&qca_soc_data_qca6390 },
  2257. { "DLA16390", (kernel_ulong_t)&qca_soc_data_qca6390 },
  2258. { "DLB16390", (kernel_ulong_t)&qca_soc_data_qca6390 },
  2259. { "DLB26390", (kernel_ulong_t)&qca_soc_data_qca6390 },
  2260. { },
  2261. };
  2262. MODULE_DEVICE_TABLE(acpi, qca_bluetooth_acpi_match);
  2263. #endif
  2264. #ifdef CONFIG_DEV_COREDUMP
  2265. static void hciqca_coredump(struct device *dev)
  2266. {
  2267. struct serdev_device *serdev = to_serdev_device(dev);
  2268. struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
  2269. struct hci_uart *hu = &qcadev->serdev_hu;
  2270. struct hci_dev *hdev = hu->hdev;
  2271. if (hdev->dump.coredump)
  2272. hdev->dump.coredump(hdev);
  2273. }
  2274. #endif
  2275. static struct serdev_device_driver qca_serdev_driver = {
  2276. .probe = qca_serdev_probe,
  2277. .remove = qca_serdev_remove,
  2278. .driver = {
  2279. .name = "hci_uart_qca",
  2280. .of_match_table = of_match_ptr(qca_bluetooth_of_match),
  2281. .acpi_match_table = ACPI_PTR(qca_bluetooth_acpi_match),
  2282. .shutdown = qca_serdev_shutdown,
  2283. .pm = &qca_pm_ops,
  2284. #ifdef CONFIG_DEV_COREDUMP
  2285. .coredump = hciqca_coredump,
  2286. #endif
  2287. },
  2288. };
  2289. int __init qca_init(void)
  2290. {
  2291. serdev_device_driver_register(&qca_serdev_driver);
  2292. return hci_uart_register_proto(&qca_proto);
  2293. }
  2294. int __exit qca_deinit(void)
  2295. {
  2296. serdev_device_driver_unregister(&qca_serdev_driver);
  2297. return hci_uart_unregister_proto(&qca_proto);
  2298. }