cp500.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) KEBA Industrial Automation Gmbh 2024
  4. *
  5. * Driver for KEBA system FPGA
  6. *
  7. * The KEBA system FPGA implements various devices. This driver registers
  8. * auxiliary devices for every device within the FPGA.
  9. */
  10. #include <linux/device.h>
  11. #include <linux/i2c.h>
  12. #include <linux/misc/keba.h>
  13. #include <linux/module.h>
  14. #include <linux/pci.h>
  15. #define CP500 "cp500"
  16. #define PCI_VENDOR_ID_KEBA 0xCEBA
  17. #define PCI_DEVICE_ID_KEBA_CP035 0x2706
  18. #define PCI_DEVICE_ID_KEBA_CP505 0x2703
  19. #define PCI_DEVICE_ID_KEBA_CP520 0x2696
  20. #define CP500_SYS_BAR 0
  21. #define CP500_ECM_BAR 1
  22. /* BAR 0 registers */
  23. #define CP500_VERSION_REG 0x00
  24. #define CP500_RECONFIG_REG 0x11 /* upper 8-bits of STARTUP register */
  25. #define CP500_AXI_REG 0x40
  26. /* Bits in BUILD_REG */
  27. #define CP500_BUILD_TEST 0x8000 /* FPGA test version */
  28. /* Bits in RECONFIG_REG */
  29. #define CP500_RECFG_REQ 0x01 /* reconfigure FPGA on next reset */
  30. /* MSIX */
  31. #define CP500_AXI_MSIX 3
  32. #define CP500_NUM_MSIX 8
  33. #define CP500_NUM_MSIX_NO_MMI 2
  34. #define CP500_NUM_MSIX_NO_AXI 3
  35. /* EEPROM */
  36. #define CP500_HW_CPU_EEPROM_NAME "cp500_cpu_eeprom"
  37. #define CP500_IS_CP035(dev) ((dev)->pci_dev->device == PCI_DEVICE_ID_KEBA_CP035)
  38. #define CP500_IS_CP505(dev) ((dev)->pci_dev->device == PCI_DEVICE_ID_KEBA_CP505)
  39. #define CP500_IS_CP520(dev) ((dev)->pci_dev->device == PCI_DEVICE_ID_KEBA_CP520)
  40. struct cp500_dev_info {
  41. off_t offset;
  42. size_t size;
  43. };
  44. struct cp500_devs {
  45. struct cp500_dev_info startup;
  46. struct cp500_dev_info i2c;
  47. };
  48. /* list of devices within FPGA of CP035 family (CP035, CP056, CP057) */
  49. static struct cp500_devs cp035_devices = {
  50. .startup = { 0x0000, SZ_4K },
  51. .i2c = { 0x4000, SZ_4K },
  52. };
  53. /* list of devices within FPGA of CP505 family (CP503, CP505, CP507) */
  54. static struct cp500_devs cp505_devices = {
  55. .startup = { 0x0000, SZ_4K },
  56. .i2c = { 0x5000, SZ_4K },
  57. };
  58. /* list of devices within FPGA of CP520 family (CP520, CP530) */
  59. static struct cp500_devs cp520_devices = {
  60. .startup = { 0x0000, SZ_4K },
  61. .i2c = { 0x5000, SZ_4K },
  62. };
  63. struct cp500 {
  64. struct pci_dev *pci_dev;
  65. struct cp500_devs *devs;
  66. int msix_num;
  67. struct {
  68. int major;
  69. int minor;
  70. int build;
  71. } version;
  72. /* system FPGA BAR */
  73. resource_size_t sys_hwbase;
  74. struct keba_i2c_auxdev *i2c;
  75. /* ECM EtherCAT BAR */
  76. resource_size_t ecm_hwbase;
  77. void __iomem *system_startup_addr;
  78. };
  79. /* I2C devices */
  80. static struct i2c_board_info cp500_i2c_info[] = {
  81. { /* temperature sensor */
  82. I2C_BOARD_INFO("emc1403", 0x4c),
  83. },
  84. { /*
  85. * CPU EEPROM
  86. * CP035 family: CPU board
  87. * CP505 family: bridge board
  88. * CP520 family: carrier board
  89. */
  90. I2C_BOARD_INFO("24c32", 0x50),
  91. .dev_name = CP500_HW_CPU_EEPROM_NAME,
  92. },
  93. { /* interface board EEPROM */
  94. I2C_BOARD_INFO("24c32", 0x51),
  95. },
  96. { /*
  97. * EEPROM (optional)
  98. * CP505 family: CPU board
  99. * CP520 family: MMI board
  100. */
  101. I2C_BOARD_INFO("24c32", 0x52),
  102. },
  103. { /* extension module 0 EEPROM (optional) */
  104. I2C_BOARD_INFO("24c32", 0x53),
  105. },
  106. { /* extension module 1 EEPROM (optional) */
  107. I2C_BOARD_INFO("24c32", 0x54),
  108. },
  109. { /* extension module 2 EEPROM (optional) */
  110. I2C_BOARD_INFO("24c32", 0x55),
  111. },
  112. { /* extension module 3 EEPROM (optional) */
  113. I2C_BOARD_INFO("24c32", 0x56),
  114. }
  115. };
  116. static ssize_t cp500_get_fpga_version(struct cp500 *cp500, char *buf,
  117. size_t max_len)
  118. {
  119. int n;
  120. if (CP500_IS_CP035(cp500))
  121. n = scnprintf(buf, max_len, "CP035");
  122. else if (CP500_IS_CP505(cp500))
  123. n = scnprintf(buf, max_len, "CP505");
  124. else
  125. n = scnprintf(buf, max_len, "CP500");
  126. n += scnprintf(buf + n, max_len - n, "_FPGA_%d.%02d",
  127. cp500->version.major, cp500->version.minor);
  128. /* test versions have test bit set */
  129. if (cp500->version.build & CP500_BUILD_TEST)
  130. n += scnprintf(buf + n, max_len - n, "Test%d",
  131. cp500->version.build & ~CP500_BUILD_TEST);
  132. n += scnprintf(buf + n, max_len - n, "\n");
  133. return n;
  134. }
  135. static ssize_t version_show(struct device *dev, struct device_attribute *attr,
  136. char *buf)
  137. {
  138. struct cp500 *cp500 = dev_get_drvdata(dev);
  139. return cp500_get_fpga_version(cp500, buf, PAGE_SIZE);
  140. }
  141. static DEVICE_ATTR_RO(version);
  142. static ssize_t keep_cfg_show(struct device *dev, struct device_attribute *attr,
  143. char *buf)
  144. {
  145. struct cp500 *cp500 = dev_get_drvdata(dev);
  146. unsigned long keep_cfg = 1;
  147. /*
  148. * FPGA configuration stream is kept during reset when RECONFIG bit is
  149. * zero
  150. */
  151. if (ioread8(cp500->system_startup_addr + CP500_RECONFIG_REG) &
  152. CP500_RECFG_REQ)
  153. keep_cfg = 0;
  154. return sysfs_emit(buf, "%lu\n", keep_cfg);
  155. }
  156. static ssize_t keep_cfg_store(struct device *dev, struct device_attribute *attr,
  157. const char *buf, size_t count)
  158. {
  159. struct cp500 *cp500 = dev_get_drvdata(dev);
  160. unsigned long keep_cfg;
  161. if (kstrtoul(buf, 10, &keep_cfg) < 0)
  162. return -EINVAL;
  163. /*
  164. * In normal operation "keep_cfg" is "1". This means that the FPGA keeps
  165. * its configuration stream during a reset.
  166. * In case of a firmware update of the FPGA, the configuration stream
  167. * needs to be reloaded. This can be done without a powercycle by
  168. * writing a "0" into the "keep_cfg" attribute. After a reset/reboot th
  169. * new configuration stream will be loaded.
  170. */
  171. if (keep_cfg)
  172. iowrite8(0, cp500->system_startup_addr + CP500_RECONFIG_REG);
  173. else
  174. iowrite8(CP500_RECFG_REQ,
  175. cp500->system_startup_addr + CP500_RECONFIG_REG);
  176. return count;
  177. }
  178. static DEVICE_ATTR_RW(keep_cfg);
  179. static struct attribute *cp500_attrs[] = {
  180. &dev_attr_version.attr,
  181. &dev_attr_keep_cfg.attr,
  182. NULL
  183. };
  184. ATTRIBUTE_GROUPS(cp500);
  185. static void cp500_i2c_release(struct device *dev)
  186. {
  187. struct keba_i2c_auxdev *i2c =
  188. container_of(dev, struct keba_i2c_auxdev, auxdev.dev);
  189. kfree(i2c);
  190. }
  191. static int cp500_register_i2c(struct cp500 *cp500)
  192. {
  193. int retval;
  194. cp500->i2c = kzalloc(sizeof(*cp500->i2c), GFP_KERNEL);
  195. if (!cp500->i2c)
  196. return -ENOMEM;
  197. cp500->i2c->auxdev.name = "i2c";
  198. cp500->i2c->auxdev.id = 0;
  199. cp500->i2c->auxdev.dev.release = cp500_i2c_release;
  200. cp500->i2c->auxdev.dev.parent = &cp500->pci_dev->dev;
  201. cp500->i2c->io = (struct resource) {
  202. /* I2C register area */
  203. .start = (resource_size_t) cp500->sys_hwbase +
  204. cp500->devs->i2c.offset,
  205. .end = (resource_size_t) cp500->sys_hwbase +
  206. cp500->devs->i2c.offset +
  207. cp500->devs->i2c.size - 1,
  208. .flags = IORESOURCE_MEM,
  209. };
  210. cp500->i2c->info_size = ARRAY_SIZE(cp500_i2c_info);
  211. cp500->i2c->info = cp500_i2c_info;
  212. retval = auxiliary_device_init(&cp500->i2c->auxdev);
  213. if (retval) {
  214. kfree(cp500->i2c);
  215. cp500->i2c = NULL;
  216. return retval;
  217. }
  218. retval = __auxiliary_device_add(&cp500->i2c->auxdev, "keba");
  219. if (retval) {
  220. auxiliary_device_uninit(&cp500->i2c->auxdev);
  221. cp500->i2c = NULL;
  222. return retval;
  223. }
  224. return 0;
  225. }
  226. static void cp500_register_auxiliary_devs(struct cp500 *cp500)
  227. {
  228. struct device *dev = &cp500->pci_dev->dev;
  229. if (cp500_register_i2c(cp500))
  230. dev_warn(dev, "Failed to register i2c!\n");
  231. }
  232. static void cp500_unregister_dev(struct auxiliary_device *auxdev)
  233. {
  234. auxiliary_device_delete(auxdev);
  235. auxiliary_device_uninit(auxdev);
  236. }
  237. static void cp500_unregister_auxiliary_devs(struct cp500 *cp500)
  238. {
  239. if (cp500->i2c) {
  240. cp500_unregister_dev(&cp500->i2c->auxdev);
  241. cp500->i2c = NULL;
  242. }
  243. }
  244. static irqreturn_t cp500_axi_handler(int irq, void *dev)
  245. {
  246. struct cp500 *cp500 = dev;
  247. u32 axi_address = ioread32(cp500->system_startup_addr + CP500_AXI_REG);
  248. /*
  249. * FPGA signals AXI response error, print AXI address to indicate which
  250. * IP core was affected
  251. */
  252. dev_err(&cp500->pci_dev->dev, "AXI response error at 0x%08x\n",
  253. axi_address);
  254. return IRQ_HANDLED;
  255. }
  256. static int cp500_enable(struct cp500 *cp500)
  257. {
  258. int axi_irq = -1;
  259. int ret;
  260. if (cp500->msix_num > CP500_NUM_MSIX_NO_AXI) {
  261. axi_irq = pci_irq_vector(cp500->pci_dev, CP500_AXI_MSIX);
  262. ret = request_irq(axi_irq, cp500_axi_handler, 0,
  263. CP500, cp500);
  264. if (ret != 0) {
  265. dev_err(&cp500->pci_dev->dev,
  266. "Failed to register AXI response error!\n");
  267. return ret;
  268. }
  269. }
  270. return 0;
  271. }
  272. static void cp500_disable(struct cp500 *cp500)
  273. {
  274. int axi_irq;
  275. if (cp500->msix_num > CP500_NUM_MSIX_NO_AXI) {
  276. axi_irq = pci_irq_vector(cp500->pci_dev, CP500_AXI_MSIX);
  277. free_irq(axi_irq, cp500);
  278. }
  279. }
  280. static int cp500_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
  281. {
  282. struct device *dev = &pci_dev->dev;
  283. struct resource startup;
  284. struct cp500 *cp500;
  285. u32 cp500_vers;
  286. char buf[64];
  287. int ret;
  288. cp500 = devm_kzalloc(dev, sizeof(*cp500), GFP_KERNEL);
  289. if (!cp500)
  290. return -ENOMEM;
  291. cp500->pci_dev = pci_dev;
  292. cp500->sys_hwbase = pci_resource_start(pci_dev, CP500_SYS_BAR);
  293. cp500->ecm_hwbase = pci_resource_start(pci_dev, CP500_ECM_BAR);
  294. if (!cp500->sys_hwbase || !cp500->ecm_hwbase)
  295. return -ENODEV;
  296. if (CP500_IS_CP035(cp500))
  297. cp500->devs = &cp035_devices;
  298. else if (CP500_IS_CP505(cp500))
  299. cp500->devs = &cp505_devices;
  300. else if (CP500_IS_CP520(cp500))
  301. cp500->devs = &cp520_devices;
  302. else
  303. return -ENODEV;
  304. ret = pci_enable_device(pci_dev);
  305. if (ret)
  306. return ret;
  307. pci_set_master(pci_dev);
  308. startup = *pci_resource_n(pci_dev, CP500_SYS_BAR);
  309. startup.end = startup.start + cp500->devs->startup.size - 1;
  310. cp500->system_startup_addr = devm_ioremap_resource(&pci_dev->dev,
  311. &startup);
  312. if (IS_ERR(cp500->system_startup_addr)) {
  313. ret = PTR_ERR(cp500->system_startup_addr);
  314. goto out_disable;
  315. }
  316. cp500->msix_num = pci_alloc_irq_vectors(pci_dev, CP500_NUM_MSIX_NO_MMI,
  317. CP500_NUM_MSIX, PCI_IRQ_MSIX);
  318. if (cp500->msix_num < CP500_NUM_MSIX_NO_MMI) {
  319. dev_err(&pci_dev->dev,
  320. "Hardware does not support enough MSI-X interrupts\n");
  321. ret = -ENODEV;
  322. goto out_disable;
  323. }
  324. cp500_vers = ioread32(cp500->system_startup_addr + CP500_VERSION_REG);
  325. cp500->version.major = (cp500_vers & 0xff);
  326. cp500->version.minor = (cp500_vers >> 8) & 0xff;
  327. cp500->version.build = (cp500_vers >> 16) & 0xffff;
  328. cp500_get_fpga_version(cp500, buf, sizeof(buf));
  329. dev_info(&pci_dev->dev, "FPGA version %s", buf);
  330. pci_set_drvdata(pci_dev, cp500);
  331. ret = cp500_enable(cp500);
  332. if (ret != 0)
  333. goto out_free_irq;
  334. cp500_register_auxiliary_devs(cp500);
  335. return 0;
  336. out_free_irq:
  337. pci_free_irq_vectors(pci_dev);
  338. out_disable:
  339. pci_clear_master(pci_dev);
  340. pci_disable_device(pci_dev);
  341. return ret;
  342. }
  343. static void cp500_remove(struct pci_dev *pci_dev)
  344. {
  345. struct cp500 *cp500 = pci_get_drvdata(pci_dev);
  346. cp500_unregister_auxiliary_devs(cp500);
  347. cp500_disable(cp500);
  348. pci_set_drvdata(pci_dev, 0);
  349. pci_free_irq_vectors(pci_dev);
  350. pci_clear_master(pci_dev);
  351. pci_disable_device(pci_dev);
  352. }
  353. static struct pci_device_id cp500_ids[] = {
  354. { PCI_DEVICE(PCI_VENDOR_ID_KEBA, PCI_DEVICE_ID_KEBA_CP035) },
  355. { PCI_DEVICE(PCI_VENDOR_ID_KEBA, PCI_DEVICE_ID_KEBA_CP505) },
  356. { PCI_DEVICE(PCI_VENDOR_ID_KEBA, PCI_DEVICE_ID_KEBA_CP520) },
  357. { }
  358. };
  359. MODULE_DEVICE_TABLE(pci, cp500_ids);
  360. static struct pci_driver cp500_driver = {
  361. .name = CP500,
  362. .id_table = cp500_ids,
  363. .probe = cp500_probe,
  364. .remove = cp500_remove,
  365. .dev_groups = cp500_groups,
  366. };
  367. module_pci_driver(cp500_driver);
  368. MODULE_AUTHOR("Gerhard Engleder <eg@keba.com>");
  369. MODULE_DESCRIPTION("KEBA CP500 system FPGA driver");
  370. MODULE_LICENSE("GPL");